mcxa153::chip::port 命名空間(Namespace)參考文件

複合項目
struct	Config
	PORT Pin Configuration Structure. 更多...
class	Port
	MCXA153 埠控制暫存器 (Port Control Register) 管理靜態工具類別 更多...
struct	Register
	PORT (Pin Multiplexing and Control) Peripheral Register Structure. 更多...
struct	Version
	PORT Peripheral Version Information Structure. 更多...

列舉型態
enum struct	DriveStrength : bool { LOW = 0U , HIGH = 1U }
	GPIO Pin Drive Strength Configuration. 更多...
enum struct	DriveStrengthDouble : bool { NORMAL = 0U , DOUBLE = 1U }
	GPIO Pin Double Drive Strength Configuration. 更多...
enum struct	InputBuffer : bool { DISABLE = 0U , ENABLE = 1U }
	GPIO Pin Digital Input Buffer Configuration. 更多...
enum struct	Inverted : bool { F:/mframe/doxy-document/src/mcxa153/src/mcxa153/chip/port/Inverted.h , NORMAL = 0U , Applications , INVERT = 1U }
	GPIO Pin Digital Input Signal Inversion Configuration. 更多...
enum struct	Lock : bool { Use , UNLOCK = 0U , Use , LOCK = 1U }
	GPIO Pin Control Register Lock Configuration. 更多...
enum struct	Mask : unsigned int {   VERID_FEATURE = 0xFFFFU , VERID_MINOR = 0xFF0000U , VERID_MAJOR = 0xFF000000U , GPCLR_GPWD = 0xFFFFU ,   GPCLR_GPWE0 = 0x10000U , GPCLR_GPWE1 = 0x20000U , GPCLR_GPWE2 = 0x40000U , GPCLR_GPWE3 = 0x80000U ,   GPCLR_GPWE4 = 0x100000U , GPCLR_GPWE5 = 0x200000U , GPCLR_GPWE6 = 0x400000U , GPCLR_GPWE7 = 0x800000U ,   GPCLR_GPWE8 = 0x1000000U , GPCLR_GPWE9 = 0x2000000U , GPCLR_GPWE10 = 0x4000000U , GPCLR_GPWE11 = 0x8000000U ,   GPCLR_GPWE12 = 0x10000000U , GPCLR_GPWE13 = 0x20000000U , GPCLR_GPWE14 = 0x40000000U , GPCLR_GPWE15 = 0x80000000U ,   GPCHR_GPWD = 0xFFFFU , GPCHR_GPWE16 = 0x10000U , GPCHR_GPWE17 = 0x20000U , GPCHR_GPWE18 = 0x40000U ,   GPCHR_GPWE19 = 0x80000U , GPCHR_GPWE20 = 0x100000U , GPCHR_GPWE21 = 0x200000U , GPCHR_GPWE22 = 0x400000U ,   GPCHR_GPWE23 = 0x800000U , GPCHR_GPWE24 = 0x1000000U , GPCHR_GPWE25 = 0x2000000U , GPCHR_GPWE26 = 0x4000000U ,   GPCHR_GPWE27 = 0x8000000U , GPCHR_GPWE28 = 0x10000000U , GPCHR_GPWE29 = 0x20000000U , GPCHR_GPWE30 = 0x40000000U ,   GPCHR_GPWE31 = 0x80000000U , CONFIG_RANGE = 0x1U , CALIB0_NCAL = 0x3FU , CALIB0_PCAL = 0x3F0000U ,   CALIB1_NCAL = 0x3FU , CALIB1_PCAL = 0x3F0000U , PCR_PS = 0x1U , PCR_PE = 0x2U ,   PCR_PV = 0x4U , PCR_SRE = 0x8U , PCR_PFE = 0x10U , PCR_ODE = 0x20U ,   PCR_DSE = 0x40U , PCR_DSE1 = 0x80U , PCR_MUX = 0xF00U , PCR_IBE = 0x1000U ,   PCR_INV = 0x2000U , PCR_LK = 0x8000U }
	PORT Pin Control Register Bit Masks. 更多...
enum struct	Mux : unsigned char {   GPIO = 0U , ALT0 = 0U , ALT1 = 1U , ALT2 = 2U ,   ALT3 = 3U , ALT4 = 4U , ALT5 = 5U , ALT6 = 6U ,   ALT7 = 7U , ALT8 = 8U , ALT9 = 9U , ALT10 = 10U ,   ALT11 = 11U , ALT12 = 12U , ALT13 = 13U , ALT14 = 14U ,   ALT15 = 15U }
	GPIO Pin Multiplexer (MUX) Function Selection. 更多...
enum struct	OpenDrain : bool {   Applications , DISABLE = 0U , Applications , Wire-OR ,   ENABLE = 1U }
	GPIO Pin Open Drain Output Configuration. 更多...
enum struct	PassiveFilter : bool {   Use , DISABLE = 0U , Use , Typical ,   ENABLE = 1U }
	GPIO Pin Passive Input Filter Configuration. 更多...
enum struct	Pull : unsigned char {   Use , DISABLE = 0U , Use , Circuit ,   DOWN = 2U , Use , Circuit , UP = 3U }
	GPIO Pin Internal Pull Resistor Configuration. 更多...
enum struct	PullResistor : bool {   Use , Power , LOW = 0U , Use ,   I2C , Power , HIGH = 1U }
	GPIO Pin Internal Pull Resistor Strength Configuration. 更多...
enum struct	Rate : bool {   Use , Timing , Performance , FAST = 0U ,   Use , EMI , Power , Signal ,   SLOW = 1U }
	GPIO Pin Output Slew Rate Configuration. 更多...
enum struct	Shift : unsigned int {   VERID_FEATURE = 0U , VERID_MINOR = 16U , VERID_MAJOR = 24U , GPCLR_GPWD = 0U ,   GPCLR_GPWE0 = 16U , GPCLR_GPWE1 = 17U , GPCLR_GPWE2 = 18U , GPCLR_GPWE3 = 19U ,   GPCLR_GPWE4 = 20U , GPCLR_GPWE5 = 21U , GPCLR_GPWE6 = 22U , GPCLR_GPWE7 = 23U ,   GPCLR_GPWE8 = 24U , GPCLR_GPWE9 = 25U , GPCLR_GPWE10 = 26U , GPCLR_GPWE11 = 27U ,   GPCLR_GPWE12 = 28U , GPCLR_GPWE13 = 29U , GPCLR_GPWE14 = 30U , GPCLR_GPWE15 = 31U ,   GPCHR_GPWD = 0U , GPCHR_GPWE16 = 16U , GPCHR_GPWE17 = 17U , GPCHR_GPWE18 = 18U ,   GPCHR_GPWE19 = 19U , GPCHR_GPWE20 = 20U , GPCHR_GPWE21 = 21U , GPCHR_GPWE22 = 22U ,   GPCHR_GPWE23 = 23U , GPCHR_GPWE24 = 24U , GPCHR_GPWE25 = 25U , GPCHR_GPWE26 = 26U ,   GPCHR_GPWE27 = 27U , GPCHR_GPWE28 = 28U , GPCHR_GPWE29 = 29U , GPCHR_GPWE30 = 30U ,   GPCHR_GPWE31 = 31U , CONFIG_RANGE = 0U , CALIB0_NCAL = 0U , CALIB0_PCAL = 16U ,   CALIB1_NCAL = 0U , CALIB1_PCAL = 16U , PCR_PS = 0U , PCR_PE = 1U ,   PCR_PV = 2U , PCR_SRE = 3U , PCR_PFE = 4U , PCR_ODE = 5U ,   PCR_DSE = 6U , PCR_DSE1 = 7U , PCR_MUX = 8U , PCR_IBE = 12U ,   PCR_INV = 13U , PCR_LK = 15U }
	Shift Enumeration for Port Control Register Bit Positions. 更多...
enum struct	VoltageRange : bool {   Use , Battery , Electrical , RANGE_1V71_3V6 = 0x0U ,   Use , Standard , Improved , Typical ,   RANGE_2V70_3V6 = 0x1U }
	GPIO Port Operating Voltage Range Configuration. 更多...

函式
constexpr bool	operator+ (DriveStrength e)
	Operator Overload - Convert DriveStrength enum to bool.
constexpr bool	operator+ (DriveStrengthDouble e)
	Operator Overload - Convert DriveStrengthDouble enum to bool.
constexpr bool	operator+ (InputBuffer e)
	Operator Overload - Convert InputBuffer enum to bool.
constexpr bool	operator+ (Inverted e)
	Operator Overload - Convert Inverted enum to bool.
constexpr bool	operator+ (Lock e)
	Operator Overload - Convert Lock enum to bool.
constexpr unsigned int	operator+ (Mask e)
constexpr unsigned char	operator+ (Mux e)
	Operator Overload - Convert Mux enum to unsigned char.
constexpr bool	operator+ (OpenDrain e)
	Operator Overload - Convert OpenDrain enum to bool.
constexpr bool	operator+ (PassiveFilter e)
	Operator Overload - Convert PassiveFilter enum to bool.
constexpr unsigned char	operator+ (Pull e)
	Operator Overload - Convert Pull enum to unsigned char.
constexpr bool	operator+ (PullResistor e)
	Operator Overload - Convert PullResistor enum to bool.
constexpr bool	operator+ (Rate e)
	Operator Overload - Convert Rate enum to bool.
constexpr unsigned int	operator+ (Shift e)
	Shift Operator Overloading - Convert Enum To Unsigned Integer.
constexpr bool	operator+ (VoltageRange e)
	Operator Overload - Convert VoltageRange enum to bool.

變數
Register &	PORT0
Register &	PORT1
Register &	PORT2
Register &	PORT3
Register *const	PORT [4]

詳細描述

Copyright (c) 2020 ZxyKira All rights reserved.

SPDX-License-Identifier: MIT

列舉型態說明文件

DriveStrength

enum struct mcxa153::chip::port::DriveStrength : bool

strong

GPIO Pin Drive Strength Configuration.

Enumeration for configuring the output drive strength of GPIO pins. Drive strength determines the pin's current sourcing/sinking capability and affects signal rise/fall times, power consumption, and EMI characteristics.

GPIO引腳輸出驅動強度配置列舉。 驅動強度決定引腳的電流源/沉能力，影響信號上升/下降時間、功耗和EMI特性。

• Controls output driver transistor strength
• Affects maximum load driving capability
• Influences power consumption and heat generation
• Impacts electromagnetic interference (EMI) characteristics
• Used in conjunction with DriveStrengthDouble for enhanced capability

註

Higher drive strength increases power consumption

Lower drive strength may not adequately drive heavy loads

Consider load requirements and power constraints when selecting

參閱

mcxa153::chip::port::DriveStrengthDouble for additional drive enhancement

mcxa153::chip::port::Config for complete pin configuration

自

v1.0.0

列舉值
LOW	Low Drive Strength Configuration. Configures the pin for low drive strength operation. Provides reduced current sourcing/sinking capability with lower power consumption. Suitable for light loads and power-sensitive applications. 低驅動強度配置，適用於輕負載和功耗敏感應用 Reduced current drive capability Lower power consumption Slower signal edge rates (reduced EMI) Suitable for: LEDs, low-current devices, internal connections May struggle with: Heavy capacitive loads, long traces, high-speed signals 註 Choose for power-sensitive applications May not drive heavy loads adequately
HIGH	High Drive Strength Configuration. Configures the pin for high drive strength operation. Provides enhanced current sourcing/sinking capability for driving heavy loads. Suitable for high-current devices and long trace connections. 高驅動強度配置，適用於重負載和長走線連接 Enhanced current drive capability Higher power consumption Faster signal edge rates (may increase EMI) Suitable for: Motors, relays, heavy capacitive loads, long traces Trade-offs: Increased power consumption and potential EMI 註 Required for driving heavy loads Increases power consumption and heat generation May require EMI mitigation techniques

DriveStrengthDouble

enum struct mcxa153::chip::port::DriveStrengthDouble : bool

strong

GPIO Pin Double Drive Strength Configuration.

Enumeration for enabling/disabling double drive strength mode on GPIO pins. Double drive strength provides maximum current sourcing/sinking capability by activating additional output driver transistors in parallel with the standard drivers.

GPIO引腳雙倍驅動強度配置列舉。 雙倍驅動強度通過並聯額外的輸出驅動電晶體提供最大電流源/沉能力。

• Works in conjunction with DriveStrength setting
• Doubles the effective current drive capability
• Significantly increases power consumption
• Provides maximum load driving capability
• Useful for driving heavy capacitive loads or long traces

註

Only use when maximum drive capability is required

Dramatically increases power consumption and heat generation

May require additional power supply and thermal considerations

Can increase electromagnetic interference (EMI)

參閱

mcxa153::chip::port::DriveStrength for base drive strength configuration

mcxa153::chip::port::Config for complete pin configuration

自

v1.0.0

列舉值
NORMAL	Normal Drive Strength Mode. Disables double drive strength, using only the standard output drivers. Provides normal current sourcing/sinking capability with standard power consumption. Suitable for most standard applications and moderate load requirements. 標準驅動強度模式，適用於大多數標準應用和中等負載需求 Uses only standard output driver transistors Normal power consumption profile Standard current drive capability Adequate for: Standard GPIO operations, moderate loads, typical PCB traces Power efficient for battery-operated applications 註 Default and recommended setting for most applications Provides good balance between performance and power consumption Sufficient for typical GPIO interfacing requirements
DOUBLE	Double Drive Strength Mode. Enables double drive strength by activating additional output drivers in parallel. Provides maximum current sourcing/sinking capability for driving the heaviest loads. Should only be used when maximum drive capability is absolutely required. 雙倍驅動強度模式，適用於需要最大驅動能力的重負載應用 Activates additional parallel output driver transistors Approximately doubles the current drive capability Significantly increases power consumption (2x or more) Enhanced heat generation requiring thermal management Suitable for: Heavy motors, high-current relays, large capacitive loads May increase EMI emissions due to faster edge rates 警告 Dramatically increases power consumption and heat generation Use only when normal + high drive strength is insufficient May require upgraded power supply and thermal design Can impact system EMI compliance 註 Reserve for applications with extreme drive requirements Consider power budget and thermal implications May require EMI filtering and shielding measures

InputBuffer

enum struct mcxa153::chip::port::InputBuffer : bool

strong

GPIO Pin Digital Input Buffer Configuration.

Enumeration for enabling/disabling the digital input buffer on GPIO pins. The input buffer controls whether a pin can be read as a digital input signal. When disabled, the pin cannot be used for digital input operations, reducing power consumption.

GPIO引腳數位輸入緩衝器配置列舉。 輸入緩衝器控制引腳是否可以作為數位輸入信號讀取。

• Controls digital input path activation
• Affects power consumption when disabled
• Required for all digital input operations
• Independent of pin direction (input/output) setting
• Must be enabled for peripheral input functions

註

Disabling saves power but prevents digital input reading

Required for GPIO input, interrupt inputs, and peripheral inputs

Analog-only pins should have input buffer disabled

Input buffer setting is independent of pin multiplexer configuration

參閱

mcxa153::chip::port::Config for complete pin configuration

自

v1.0.0

列舉值
DISABLE	Digital Input Buffer Disabled. Disables the digital input buffer, preventing the pin from being read as digital input. Pin cannot be used for digital input operations, GPIO reading, or interrupt generation. This configuration saves power and is recommended for analog-only or output-only pins. 關閉數位輸入緩衝器，適用於純類比或純輸出引腳 Pin cannot be read as digital input Reduces power consumption GPIO input operations will not function Interrupt generation from pin is disabled Peripheral input functions are unavailable Suitable for: Analog inputs (ADC), DAC outputs, PWM outputs, output-only pins 註 Use for analog-only pins to minimize power consumption Pin direction can still be set to input, but reading will not work Recommended for pins dedicated to analog functions 警告 Digital input operations will not function with buffer disabled Interrupts and peripheral inputs require enabled input buffer
ENABLE	Digital Input Buffer Enabled. Enables the digital input buffer, allowing the pin to be read as digital input. Pin can be used for digital input operations, GPIO reading, interrupt generation, and peripheral input functions. This is the standard configuration for digital I/O. 啟用數位輸入緩衝器，允許引腳作為數位輸入使用 Pin can be read as digital input Enables GPIO input operations Allows interrupt generation from pin state changes Required for peripheral input functions (UART RX, SPI MISO, I2C SDA/SCL, etc.) Supports both input and output operations on the same pin Suitable for: GPIO inputs, bidirectional signals, peripheral I/O, interrupt sources 註 Required for all digital input operations Must be enabled for interrupt-capable pins Necessary for bidirectional communication protocols Standard setting for most GPIO applications 警告 Increases power consumption compared to disabled buffer 註 Even output pins may need input buffer for read-back verification

Inverted

enum struct mcxa153::chip::port::Inverted : bool

strong

GPIO Pin Digital Input Signal Inversion Configuration.

Enumeration for configuring digital input signal inversion at the pin level. When enabled, the logic level of input signals is inverted before being processed by the microcontroller, effectively converting active-low signals to active-high.

GPIO引腳數位輸入信號反相配置列舉。 啟用時，輸入信號的邏輯電平在被微控制器處理前會被反相。

• Inversion occurs at the pin input stage, before peripheral processing
• Affects all digital input readings from the pin
• Useful for interfacing with active-low signal sources
• Does not affect output signal polarity
• Independent of pull-up/pull-down resistor configuration

註

Inversion applies to GPIO reads, interrupts, and peripheral inputs

Does not affect analog signal levels or ADC readings

Useful for simplifying software logic when dealing with inverted signals

Output signals are not affected by this setting

參閱

mcxa153::chip::port::Config for complete pin configuration

自

v1.0.0

列舉值
F:/mframe/doxy-document/src/mcxa153/src/mcxa153/chip/port/Inverted.h	Normal Input Signal Polarity. Input signals are processed without inversion, maintaining their original polarity. Logic high (VDD) on the pin is read as logical '1', logic low (GND) as logical '0'. This is the standard configuration for most digital interface applications. 正常輸入信號極性，適用於大多數標準數位介面應用 Pin voltage directly corresponds to logical value High voltage (VDD) → Logical '1' Low voltage (GND/VSS) → Logical '0' Standard behavior for most digital protocols Compatible with typical push-pull outputs Suitable for: Standard GPIO, UART, SPI, I2C, positive logic systems 註 Default and most common configuration Use when interfacing with standard digital outputs Compatible with most communication protocols and peripherals Button with pull-up: Pressed = 0, Released = 1 LED cathode control: On = 0, Off = 1 (requires software inversion) Standard UART/SPI signals: Direct voltage-to-logic mapping
Applications	Inverted Input Signal Polarity. Input signals are inverted before processing, reversing their logical polarity. Logic high (VDD) on the pin is read as logical '0', logic low (GND) as logical '1'. Useful for interfacing with active-low signals and simplifying software logic. 反相輸入信號極性，適用於主動低電平信號介面 Pin voltage is inverted before logical processing High voltage (VDD) → Logical '0' Low voltage (GND/VSS) → Logical '1' Simplifies active-low signal handling Eliminates need for software inversion Suitable for: Active-low buttons, open-drain outputs, inverted logic systems 註 Useful for active-low signal sources Simplifies software when dealing with inverted logic Common with open-drain/open-collector outputs : Active-low button: Pressed = 1, Released = 0 (no software inversion needed) Open-drain interrupt signals: Active = 1, Idle = 0 Inverted enable signals: Enabled = 1, Disabled = 0 Reset buttons: Pressed = 1, Released = 0 註 Particularly useful for: Interrupt inputs from active-low sources Open-drain bus signals (I2C-style) Reset and enable pins with active-low polarity Simplifying conditional logic in software

範例

F:/mframe/doxy-document/src/mcxa153/src/mcxa153/chip/port/Inverted.h.

Lock

enum struct mcxa153::chip::port::Lock : bool

strong

GPIO Pin Control Register Lock Configuration.

Enumeration for controlling the write protection of GPIO Pin Control Register (PCR) fields. When locked, the pin configuration becomes read-only and cannot be modified until the next system reset, providing protection against accidental configuration changes.

GPIO引腳控制暫存器鎖定配置列舉。 鎖定後，引腳配置變為唯讀，直到下次系統復位才能解鎖。

• Controls write protection for PCR bits [15:0]
• Lock status persists until system reset
• Prevents accidental configuration modification
• Useful for critical pin configurations
• Lock bit itself (bit 15) is also protected when set

註

Once locked, configuration cannot be changed until reset

Lock applies to all configuration bits except the lock bit can be read

Useful for protecting critical system pins from software errors

Does not affect pin data register (GPIO output values)

警告

Locking is irreversible until system reset

參閱

mcxa153::chip::port::Config for complete pin configuration

自

v1.0.0

列舉值
Use	Pin Control Register Unlocked State. Pin Control Register fields [15:0] are not write-protected and can be modified. All pin configuration parameters can be changed dynamically during runtime. This is the default state allowing normal pin configuration operations. 引腳控制暫存器未鎖定狀態，允許正常的引腳配置操作 All PCR configuration bits [14:0] are writable Pin multiplexer, drive strength, pull resistors, etc. can be modified Lock bit [15] can be set to transition to locked state Normal operational mode for dynamic pin reconfiguration Allows runtime adaptation of pin functions 註 Default state after system reset Enables flexible pin function switching during operation Required for applications needing dynamic pin reconfiguration Cases: Dynamic peripheral switching (GPIO ↔ UART ↔ SPI) Power mode dependent pin configurations Runtime optimization of electrical characteristics Debugging and development flexibility 警告 Vulnerable to accidental configuration changes Software errors could modify critical pin settings
Use	Pin Control Register Locked State. Pin Control Register fields [15:0] are write-protected and cannot be modified. Once locked, the pin configuration is frozen until the next system reset, providing robust protection against accidental or malicious configuration changes. 引腳控制暫存器鎖定狀態，提供配置保護直到系統復位 All PCR configuration bits [14:0] become read-only Lock bit [15] itself also becomes read-only (self-protecting) Configuration remains fixed until system reset Prevents modification of: MUX, drive strength, pull resistors, filters, etc. GPIO data register (pin output values) remains writable Pin direction control may still be available depending on MUX setting 註 Locking is irreversible without system reset Provides hardware-level protection against configuration corruption Recommended for safety-critical and security-sensitive applications Cases: Safety-critical system pins (emergency stops, watchdog) Security-sensitive configurations (crypto interfaces) Production firmware protecting bootloader pins Preventing accidental reconfiguration of critical communication interfaces EMI-sensitive RF applications requiring stable pin characteristics 警告 Cannot be unlocked without system reset Ensure configuration is correct before locking May complicate debugging if locked during development 註 Best Practices: Lock only after verifying configuration is correct Document all locked pins for maintenance Use sparingly during development phase Consider reset requirements for field updates

Mask

enum struct mcxa153::chip::port::Mask : unsigned int

strong

PORT Pin Control Register Bit Masks.

Enumeration defining bit masks for the PORT Pin Control Register (PCR). Each mask corresponds to a specific configuration option for GPIO pins, allowing for flexible pin control and configuration.

PORT引腳控制暫存器位元遮罩列舉。 每個遮罩對應於GPIO引腳的特定配置選項，允許靈活的引腳控制和配置。

註

Use these masks with bitwise operations to configure pin settings

自

v1.0.0

列舉值
VERID_FEATURE	VERID - FEATURE. Version ID - Feature Specification Number [0b0000000000000000]Basic implementation
VERID_MINOR	VERID - MINOR. Version ID - Minor Version Number
VERID_MAJOR	VERID - MAJOR. Version ID - Major Version Number
GPCLR_GPWD	GPCLR - GPWD. Global Pin Control Low - Global Pin Write Data
GPCLR_GPWE0	GPCLR - GPWE0. Global Pin Control Low - Global Pin Write Enable [0b0]Not updated [0b1]Updated
GPCLR_GPWE1	GPCLR - GPWE1. Global Pin Control Low - Global Pin Write Enable [0b0]Not updated [0b1]Updated
GPCLR_GPWE2	GPCLR - GPWE2. Global Pin Control Low - Global Pin Write Enable [0b0]Not updated [0b1]Updated
GPCLR_GPWE3	GPCLR - GPWE3. Global Pin Control Low - Global Pin Write Enable [0b0]Not updated [0b1]Updated
GPCLR_GPWE4	GPCLR - GPWE4. Global Pin Control Low - Global Pin Write Enable [0b0]Not updated [0b1]Updated
GPCLR_GPWE5	GPCLR - GPWE5. Global Pin Control Low - Global Pin Write Enable [0b0]Not updated [0b1]Updated
GPCLR_GPWE6	GPCLR - GPWE6. Global Pin Control Low - Global Pin Write Enable [0b0]Not updated [0b1]Updated
GPCLR_GPWE7	GPCLR - GPWE7. Global Pin Control Low - Global Pin Write Enable [0b0]Not updated [0b1]Updated
GPCLR_GPWE8	GPCLR - GPWE8. Global Pin Control Low - Global Pin Write Enable [0b0]Not updated [0b1]Updated
GPCLR_GPWE9	GPCLR - GPWE9. Global Pin Control Low - Global Pin Write Enable [0b0]Not updated [0b1]Updated
GPCLR_GPWE10	GPCLR - GPWE10. Global Pin Control Low - Global Pin Write Enable [0b0]Not updated [0b1]Updated
GPCLR_GPWE11	GPCLR - GPWE11. Global Pin Control Low - Global Pin Write Enable [0b0]Not updated [0b1]Updated
GPCLR_GPWE12	GPCLR - GPWE12. Global Pin Control Low - Global Pin Write Enable [0b0]Not updated [0b1]Updated
GPCLR_GPWE13	GPCLR - GPWE13. Global Pin Control Low - Global Pin Write Enable [0b0]Not updated [0b1]Updated
GPCLR_GPWE14	GPCLR - GPWE14. Global Pin Control Low - Global Pin Write Enable [0b0]Not updated [0b1]Updated
GPCLR_GPWE15	GPCLR - GPWE15. Global Pin Control Low - Global Pin Write Enable [0b0]Not updated [0b1]Updated
GPCHR_GPWD	GPCHR - GPWD. Global Pin Control High - Global Pin Write Data
GPCHR_GPWE16	GPCHR - GPWE16. Global Pin Control High - Global Pin Write Enable [0b0]Not updated [0b1]Updated
GPCHR_GPWE17	GPCHR - GPWE17. Global Pin Control High - Global Pin Write Enable [0b0]Not updated [0b1]Updated
GPCHR_GPWE18	GPCHR - GPWE18. Global Pin Control High - Global Pin Write Enable [0b0]Not updated [0b1]Updated
GPCHR_GPWE19	GPCHR - GPWE19. Global Pin Control High - Global Pin Write Enable [0b0]Not updated [0b1]Updated
GPCHR_GPWE20	GPCHR - GPWE20. Global Pin Control High - Global Pin Write Enable [0b0]Not updated [0b1]Updated
GPCHR_GPWE21	GPCHR - GPWE21. Global Pin Control High - Global Pin Write Enable [0b0]Not updated [0b1]Updated
GPCHR_GPWE22	GPCHR - GPWE22. Global Pin Control High - Global Pin Write Enable [0b0]Not updated [0b1]Updated
GPCHR_GPWE23	GPCHR - GPWE23. Global Pin Control High - Global Pin Write Enable [0b0]Not updated [0b1]Updated
GPCHR_GPWE24	GPCHR - GPWE24. Global Pin Control High - Global Pin Write Enable [0b0]Not updated [0b1]Updated
GPCHR_GPWE25	GPCHR - GPWE25. Global Pin Control High - Global Pin Write Enable [0b0]Not updated [0b1]Updated
GPCHR_GPWE26	GPCHR - GPWE26. Global Pin Control High - Global Pin Write Enable [0b0]Not updated [0b1]Updated
GPCHR_GPWE27	GPCHR - GPWE27. Global Pin Control High - Global Pin Write Enable [0b0]Not updated [0b1]Updated
GPCHR_GPWE28	GPCHR - GPWE28. Global Pin Control High - Global Pin Write Enable [0b0]Not updated [0b1]Updated
GPCHR_GPWE29	GPCHR - GPWE29. Global Pin Control High - Global Pin Write Enable [0b0]Not updated [0b1]Updated
GPCHR_GPWE30	GPCHR - GPWE30. Global Pin Control High - Global Pin Write Enable [0b0]Not updated [0b1]Updated
GPCHR_GPWE31	GPCHR - GPWE31. Global Pin Control High - Global Pin Write Enable [0b0]Not updated [0b1]Updated
CONFIG_RANGE	CONFIG - RANGE. Configuration - Port Voltage Range [0b0]1.71 V-3.6 V [0b1]2.70 V-3.6 V
CALIB0_NCAL	CALIB0 - NCAL. Calibration 0 - Calibration of NMOS Output Driver
CALIB0_PCAL	CALIB0 - PCAL. Calibration 0 - Calibration of PMOS Output Driver
CALIB1_NCAL	CALIB1 - NCAL. Calibration 1 - Calibration of NMOS Output Driver
CALIB1_PCAL	CALIB1 - PCAL. Calibration 1 - Calibration of PMOS Output Driver
PCR_PS	PCR - PS. Pin Control 0..Pin Control 31 - Pull Select [0b0]Enables internal pulldown resistor [0b1]Enables internal pullup resistor
PCR_PE	PCR - PE. Pin Control 0..Pin Control 31 - Pull Enable [0b0]Disables [0b1]Enables
PCR_PV	PCR - PV. Pin Control 0..Pin Control 31 - Pull Value [0b0]Low [0b1]High
PCR_SRE	PCR - SRE. Pin Control 0..Pin Control 31 - Slew Rate Enable [0b0]Fast [0b1]Slow
PCR_PFE	PCR - PFE. Pin Control 0..Pin Control 31 - Passive Filter Enable [0b0]Disables [0b1]Enables
PCR_ODE	PCR - ODE. Pin Control 0..Pin Control 31 - Open Drain Enable [0b0]Disables [0b1]Enables
PCR_DSE	PCR - DSE. Pin Control 0..Pin Control 31 - Drive Strength Enable [0b0]Low [0b1]High
PCR_DSE1	PCR - DSE1. Pin Control 0..Pin Control 31 - Drive Strength Enable [0b0]Normal [0b1]Double
PCR_MUX	PCR - MUX. Pin Control 0..Pin Control 31 - Pin Multiplex Control [0b0000]Alternative 0 (GPIO) [0b0001]Alternative 1 (chip-specific) [0b0010]Alternative 2 (chip-specific) [0b0011]Alternative 3 (chip-specific) [0b0100]Alternative 4 (chip-specific) [0b0101]Alternative 5 (chip-specific) [0b0110]Alternative 6 (chip-specific) [0b0111]Alternative 7 (chip-specific) [0b1000]Alternative 8 (chip-specific) [0b1001]Alternative 9 (chip-specific) [0b1010]Alternative 10 (chip-specific) [0b1011]Alternative 11 (chip-specific) [0b1100]Alternative 12 (chip-specific) [0b1101]Alternative 13 (chip-specific)
PCR_IBE	PCR - IBE. Pin Control 0..Pin Control 31 - Input Buffer Enable [0b0]Disables [0b1]Enables
PCR_INV	PCR - INV. Pin Control 0..Pin Control 31 - Invert Input [0b0]Does not invert [0b1]Inverts
PCR_LK	PCR - LK. Pin Control 0..Pin Control 31 - Lock Register [0b0]Does not lock [0b1]Locks

Mux

enum struct mcxa153::chip::port::Mux : unsigned char

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GPIO Pin Multiplexer (MUX) Function Selection.

Enumeration for selecting the peripheral function assigned to each GPIO pin. The multiplexer determines which peripheral (GPIO, UART, SPI, I2C, etc.) has control over the pin's input/output behavior. Each pin supports multiple alternative functions, and this setting selects which one is active.

GPIO引腳多工器(MUX)功能選擇列舉。 多工器決定哪個周邊裝置(GPIO、UART、SPI、I2C等)控制引腳的輸入/輸出行為。

• 4-bit field supporting up to 16 different functions per pin
• Function assignments are pin-specific and defined in pin mapping tables
• ALT0 typically corresponds to GPIO function
• Higher ALT numbers assign specialized peripheral functions
• Pin electrical characteristics (drive strength, pull resistors) remain active

註

Function availability varies by pin - consult pin mapping documentation

Some functions may require additional peripheral configuration

Pin electrical settings (pull resistors, drive strength) remain effective

Invalid combinations may result in undefined behavior

參閱

MCXA153 Pin Mapping Tables for specific function assignments

mcxa153::chip::port::Config for complete pin configuration

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GPIO	GPIO Function / Alternative Function 0. Configures the pin as General Purpose Input/Output (GPIO). Pin is controlled directly by GPIO registers and can be used for basic digital input/output operations under software control. 配置引腳為通用輸入/輸出(GPIO)功能 Pin controlled by GPIO data direction and output registers Software can directly read input state and control output state Default function for most pins after reset Supports interrupt generation on state changes Compatible with all electrical configuration options 註 ALT0 and GPIO are equivalent (both = 0) Most flexible function for general-purpose applications Interrupt capability depends on pin and GPIO controller features
ALT0	Alternative Function 0 (GPIO) Identical to GPIO function. Provided for consistency with alternative function naming convention. 與GPIO功能相同，為保持替代功能命名一致性而提供 註 Functionally identical to GPIO Some documentation may refer to GPIO as ALT0
ALT1	Alternative Function 1. Assigns pin to first alternative peripheral function. Specific function varies by pin and is defined in chip pin mapping tables. 指派引腳給第一個替代周邊功能 Pin-specific function assignment Common assignments: UART TX/RX, SPI CLK/MOSI/MISO, I2C SDA/SCL Peripheral takes control of pin direction and output values Input buffer should be enabled for input functions 註 Consult MCXA153 pin mapping documentation for specific functions Peripheral must be properly configured and enabled
ALT2	Alternative Function 2. Assigns pin to second alternative peripheral function. Specific function varies by pin and is defined in chip pin mapping tables. 指派引腳給第二個替代周邊功能 Pin-specific function assignment May include: Timer PWM outputs, ADC triggers, Comparator outputs Function availability depends on pin location and peripheral routing 註 Consult pin mapping tables for available functions Some pins may not support all alternative functions
ALT3	Alternative Function 3. Assigns pin to third alternative peripheral function. Specific function varies by pin and is defined in chip pin mapping tables. 指派引腳給第三個替代周邊功能
ALT4	Alternative Function 4. Assigns pin to fourth alternative peripheral function. Specific function varies by pin and is defined in chip pin mapping tables. 指派引腳給第四個替代周邊功能
ALT5	Alternative Function 5. Assigns pin to fifth alternative peripheral function. Specific function varies by pin and is defined in chip pin mapping tables. 指派引腳給第五個替代周邊功能
ALT6	Alternative Function 6. Assigns pin to sixth alternative peripheral function. Specific function varies by pin and is defined in chip pin mapping tables. 指派引腳給第六個替代周邊功能
ALT7	Alternative Function 7. Assigns pin to seventh alternative peripheral function. Specific function varies by pin and is defined in chip pin mapping tables. 指派引腳給第七個替代周邊功能
ALT8	Alternative Function 8. Assigns pin to eighth alternative peripheral function. Specific function varies by pin and is defined in chip pin mapping tables. 指派引腳給第八個替代周邊功能
ALT9	Alternative Function 9. Assigns pin to ninth alternative peripheral function. Specific function varies by pin and is defined in chip pin mapping tables. 指派引腳給第九個替代周邊功能
ALT10	Alternative Function 10. Assigns pin to tenth alternative peripheral function. Specific function varies by pin and is defined in chip pin mapping tables. 指派引腳給第十個替代周邊功能
ALT11	Alternative Function 11. Assigns pin to eleventh alternative peripheral function. Specific function varies by pin and is defined in chip pin mapping tables. 指派引腳給第十一個替代周邊功能
ALT12	Alternative Function 12. Assigns pin to twelfth alternative peripheral function. Specific function varies by pin and is defined in chip pin mapping tables. 指派引腳給第十二個替代周邊功能
ALT13	Alternative Function 13. Assigns pin to thirteenth alternative peripheral function. Specific function varies by pin and is defined in chip pin mapping tables. 指派引腳給第十三個替代周邊功能
ALT14	Alternative Function 14. Assigns pin to fourteenth alternative peripheral function. Specific function varies by pin and is defined in chip pin mapping tables. 指派引腳給第十四個替代周邊功能
ALT15	Alternative Function 15. Assigns pin to fifteenth alternative peripheral function. Specific function varies by pin and is defined in chip pin mapping tables. 指派引腳給第十五個替代周邊功能 註 Highest numbered alternative function May be reserved or unused on some pins

OpenDrain

enum struct mcxa153::chip::port::OpenDrain : bool

strong

GPIO Pin Open Drain Output Configuration.

Enumeration for configuring GPIO pins to operate in open drain (open collector) mode. In open drain mode, the pin can only actively pull low or float (high impedance), requiring an external pull-up resistor to achieve logic high levels.

GPIO引腳開漏輸出配置列舉。 在開漏模式下，引腳只能主動拉低或浮空，需要外部上拉電阻達到邏輯高電平。

• Output stage consists of N-channel transistor only (no P-channel)
• Can only sink current, cannot source current
• Logic high achieved by external pull-up resistor
• Multiple open drain outputs can be wire-OR connected
• Commonly used in I2C, 1-Wire, and multi-master bus applications

註

Requires external pull-up resistor for proper logic high operation

Internal pull-up resistors may be insufficient for some applications

Wire-OR capability allows multiple devices to share the same signal line

Current sinking capability still controlled by drive strength settings

參閱

mcxa153::chip::port::Pull for internal pull-up resistor configuration

mcxa153::chip::port::DriveStrength for current sinking capability

mcxa153::chip::port::Config for complete pin configuration

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Applications	Push-Pull Output Mode (Open Drain Disabled) Configures the pin for standard push-pull output operation. Pin can actively drive both logic high (VDD) and logic low (GND) levels using complementary P-channel and N-channel output transistors. 標準推拉輸出模式，適用於大多數數位輸出應用 Both P-channel (pull-up) and N-channel (pull-down) transistors active Can actively source current for logic high output Can actively sink current for logic low output No external pull-up resistor required Provides strongest drive capability and fastest switching Standard mode for most digital interfaces 註 Default output mode for most GPIO applications Provides fastest signal transitions and lowest output impedance Cannot be wire-OR connected with other outputs Suitable for: LEDs, digital control signals, clock outputs : LED control (direct drive capability) Chip select signals for SPI devices Enable/disable control pins Clock signal generation Standard digital communication (UART TX)
Applications	Open Drain Output Mode (Open Drain Enabled) Configures the pin for open drain (open collector) output operation. Pin can only actively pull low (GND) or float (high impedance). Logic high levels must be provided by external pull-up resistors. 開漏輸出模式，適用於多主控匯流排和線或(Wired-OR)應用 Only N-channel (pull-down) transistor is active P-channel (pull-up) transistor is permanently disabled Logic low: Pin actively pulls to GND Logic high: Pin floats, external pull-up provides VDD level Multiple open drain outputs can be connected together (wire-OR) Current sinking capability controlled by drive strength setting 註 Requires external pull-up resistor for logic high operation Internal pull-up may be insufficient for some applications Essential for multi-master bus communication protocols : I2C bus communication (SDA and SCL lines) 1-Wire communication protocols Multi-master bus arbitration Interrupt signals from multiple sources Reset networks with multiple reset sources LED current sinking (with current limiting resistor)
Wire-OR	Configuration: Device A (OD) ----+---- Pull-up ---- VDD Device B (OD) ----+ Device C (OD) ----+---- Signal Line 警告 External pull-up resistor is mandatory for proper operation Pull-up resistor value affects signal timing and power consumption Not suitable for high-speed signals without careful design 註 Pull-up resistor selection considerations: Lower resistance: Faster rise times, higher power consumption Higher resistance: Slower rise times, lower power consumption Must handle total sink current from all connected devices

PassiveFilter

enum struct mcxa153::chip::port::PassiveFilter : bool

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GPIO Pin Passive Input Filter Configuration.

Enumeration for enabling/disabling the passive input filter on GPIO pins. The passive filter helps reduce noise sensitivity by filtering out high-frequency noise and glitches on input signals, improving system reliability in noisy environments.

GPIO引腳被動輸入濾波器配置列舉。 被動濾波器通過濾除輸入信號上的高頻噪聲和毛刺來降低噪聲敏感性。

• Implements RC-style low-pass filtering at pin input stage
• Reduces susceptibility to electromagnetic interference (EMI)
• Filters out short-duration voltage spikes and glitches
• Particularly effective against switch bounce and transmission line reflections
• Filter characteristics are hardware-defined and not user-configurable

註

Filtering introduces slight input delay and may affect timing-critical signals

Filter effectiveness depends on noise frequency characteristics

Most beneficial in electrically noisy environments or with long PCB traces

Does not affect output signal characteristics

參閱

mcxa153::chip::port::InputBuffer for digital input buffer configuration

mcxa153::chip::port::Config for complete pin configuration

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Use	Passive Input Filter Disabled. Disables the passive input filter, allowing all input signal frequencies to pass through. Provides fastest input response time but offers no protection against high-frequency noise. Suitable for clean electrical environments and timing-critical applications. 關閉被動輸入濾波器，適用於乾淨的電氣環境和時序關鍵應用 No filtering applied to input signals Minimal input delay for fastest response times Full sensitivity to all signal frequencies including noise Maximum bandwidth for high-speed digital signals Vulnerable to EMI, switch bounce, and transmission line effects 註 Default setting for maximum signal fidelity and speed Use in clean electrical environments with proper PCB design Suitable for high-speed communication interfaces May require external filtering in noisy environments Cases: High-speed SPI/I2C communication Precision timing signals and clocks Clean digital control signals Short PCB traces with proper ground planes Controlled electrical environments Applications where every nanosecond of delay matters 警告 More susceptible to false triggering from electrical noise May require additional external noise mitigation measures Switch inputs may experience bounce without debouncing
Use	Passive Input Filter Enabled. Enables the passive input filter to reduce high-frequency noise and improve signal integrity in electrically challenging environments. Provides noise immunity at the cost of slightly increased input delay. 啟用被動輸入濾波器，適用於電氣環境具挑戰性的應用 RC-style low-pass filtering applied to input signals Attenuates high-frequency noise and voltage spikes Reduces false triggering from electromagnetic interference Improves system reliability in industrial environments Introduces small propagation delay (typically few nanoseconds) Filter time constant is hardware-defined and optimized for typical applications 註 Recommended for noisy electrical environments Particularly effective against switch bounce and contact chatter Useful for long cable connections and PCB traces May reduce need for external noise suppression components Cases: Mechanical switch and button inputs (reduces bounce) Long cable connections and external sensors Industrial control environments with motor drives PCB layouts with limited ground plane coverage RF-rich environments (near transmitters, switching power supplies) Automotive and harsh electrical environments Interrupt inputs that must be noise-immune
Typical	Applications: User interface buttons and switches Sensor inputs over long wires Limit switches and position sensors Emergency stop and safety inputs External interrupt sources in noisy systems 註 Filter Characteristics (typical): Effective against MHz-range noise and spikes Minimal impact on signals < 100kHz Propagation delay: few nanoseconds to low microseconds Does not affect DC levels or slowly changing signals 警告 Introduces slight input delay - verify timing requirements May attenuate very fast legitimate signal transitions Not effective against low-frequency noise or DC offset

Pull

enum struct mcxa153::chip::port::Pull : unsigned char

strong

GPIO Pin Internal Pull Resistor Configuration.

Enumeration for configuring the internal pull resistor on GPIO pins. Pull resistors provide a default logic level when the pin is not actively driven, preventing floating inputs and ensuring deterministic logic states.

GPIO引腳內部上拉/下拉電阻配置列舉。 上拉/下拉電阻在引腳未被主動驅動時提供預設邏輯電平，防止浮空輸入。

• Pull resistors are relatively weak (typically 10kΩ - 100kΩ range)
• Provide bias voltage to prevent floating inputs
• Can be overridden by external drivers with sufficient current capability
• Resistance value controlled by PullResistor enumeration setting
• Active in both input and output modes (though less relevant for outputs)

註

Pull resistors consume power when pin is driven to opposite level

External drivers must sink/source enough current to override pull resistor

Pull resistor values are design-dependent and may vary with voltage/temperature

Essential for proper operation of mechanical switches and open-drain interfaces

參閱

mcxa153::chip::port::PullResistor for resistance value selection

mcxa153::chip::port::OpenDrain for open-drain output configuration

mcxa153::chip::port::Config for complete pin configuration

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Use	Internal Pull Resistor Disabled. Disables both internal pull-up and pull-down resistors. Pin will float when not actively driven, requiring external biasing or guaranteed external drive for proper operation. 關閉內部上拉和下拉電阻，適用於有外部偏壓或驅動的應用 No internal biasing provided to pin Pin impedance is essentially infinite when not driven Minimum power consumption from pull resistor Pin state is undefined when no external drive is present May exhibit noise sensitivity due to floating condition 註 Use when external pull resistors are provided Suitable for output-only pins where input state is irrelevant May cause undefined behavior with floating inputs Recommended for analog inputs to minimize loading Cases: Pins with external pull-up/pull-down resistors Output-only applications (LEDs, motor control) Analog input pins (ADC) to minimize loading effects Pins connected to active drivers (push-pull outputs) Power-sensitive applications requiring minimal current draw Pins used for high-speed digital signals with proper termination 警告 Pin will float if not externally driven - may cause undefined logic levels Floating inputs can cause increased power consumption due to intermediate voltages May be susceptible to noise pickup and false triggering
Use	Internal Pull-Down Resistor Enabled. Enables internal pull-down resistor, biasing the pin toward ground (logic low). When no external drive is present, pin will default to logic low state. External drivers must source current to achieve logic high. 啟用內部下拉電阻，將引腳偏向接地（邏輯低電平） Pin defaults to logic low (0) when not externally driven External driver must source current to VDD for logic high Current flows through resistor when pin is driven high Provides defined logic state preventing floating condition Resistance value determined by PullResistor configuration 註 External driver must overcome pull-down current for logic high Power consumption occurs when pin is driven to logic high Useful for active-high input signals with weak drive capability Cases: Active-high button inputs (button connects pin to VDD) Enable/select signals that default to disabled state Interrupt inputs that should be normally low Bus signals where low is the idle/default state Reset inputs that should default to asserted (low) state Inputs from open-collector/open-drain outputs requiring pull-down
Circuit	Configuration: VDD ----[Button]---- Pin ----[Pull-down]---- GND | To MCU Button open: Pin = 0 (pulled down) Button pressed: Pin = 1 (connected to VDD) 註 Pull-down strength must be sufficient to guarantee logic low without external drive External driver must source more current than pull-down sink current
Use	Internal Pull-Up Resistor Enabled. Enables internal pull-up resistor, biasing the pin toward VDD (logic high). When no external drive is present, pin will default to logic high state. External drivers must sink current to achieve logic low. 啟用內部上拉電阻，將引腳偏向VDD（邏輯高電平） Pin defaults to logic high (1) when not externally driven External driver must sink current to ground for logic low Current flows through resistor when pin is driven low Most common configuration for digital input applications Resistance value determined by PullResistor configuration 註 External driver must overcome pull-up current for logic low Power consumption occurs when pin is driven to logic low Standard configuration for most switch inputs and bus interfaces Cases: Active-low button inputs (button connects pin to ground) I2C bus lines (SDA and SCL require pull-up for open-drain operation) Reset buttons and interrupt inputs (typically active-low) Enable/select signals that default to enabled state Bus interfaces where high is the idle/default state Inputs from open-drain/open-collector outputs UART and SPI inputs for proper idle states
Circuit	Configurations: Button Input: Pin ----[Pull-up]---- VDD | +----[Button]---- GND | To MCU Button open: Pin = 1 (pulled up) Button pressed: Pin = 0 (connected to GND) I2C Bus: VDD ----[Pull-up]---- SDA/SCL ---- To multiple devices Bus idle: Pin = 1 (pulled up) Bus active: Pin = 0 (driven by active device) 註 Pull-up strength must be appropriate for the specific application For I2C, pull-up value affects rise time and bus speed capability External driver must sink more current than pull-up source current

PullResistor

enum struct mcxa153::chip::port::PullResistor : bool

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GPIO Pin Internal Pull Resistor Strength Configuration.

Enumeration for selecting the resistance value of internal pull-up/pull-down resistors. This setting controls the strength of the bias current and affects power consumption, signal rise/fall times, and the ability to override the pull resistor with external drivers.

GPIO引腳內部上拉/下拉電阻強度配置列舉。 此設定控制偏壓電流強度，影響功耗、信號上升/下降時間和外部驅動器覆蓋能力。

• Controls the actual resistance value of enabled pull resistors
• Only effective when Pull is configured to UP or DOWN (not DISABLE)
• Lower resistance provides stronger bias but higher power consumption
• Higher resistance provides weaker bias but lower power consumption
• Affects signal timing characteristics and noise immunity

註

Exact resistance values are design-dependent and may vary with supply voltage/temperature

Setting only applies when pull resistors are enabled via Pull enumeration

External driver current requirements depend on selected resistance value

Consider power consumption implications for battery-powered applications

參閱

mcxa153::chip::port::Pull for enabling/disabling pull resistors

mcxa153::chip::port::Config for complete pin configuration

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Use	Low Pull Resistor Strength (High Resistance Value) Selects higher resistance value for internal pull resistors, providing weaker bias current. Results in lower power consumption but requires external drivers with less current capability to override the pull resistor. Suitable for power-sensitive applications. 低上拉/下拉電阻強度（高電阻值），適用於功耗敏感應用 Higher resistance value (typically in tens of kΩ range) Weaker bias current reduces power consumption Slower signal rise/fall times due to higher R×C time constants External drivers need less current to override pull resistor Better for high-impedance applications and battery-powered devices May provide less noise immunity due to weaker bias 註 Exact resistance values are device-specific (consult datasheet) Power consumption is proportional to I²R, so higher R = lower power May result in slower signal transitions affecting timing-critical applications Cases: Battery-powered applications prioritizing low power consumption High-impedance sensor inputs requiring minimal loading Applications with strong external drivers (push-pull outputs) Slow-speed digital interfaces where timing is not critical Inputs from devices with limited current drive capability Wake-up pins that should minimize standby power
Power	Analysis: If pull-up driven low: P = V²/R, higher R = lower power For 3.3V with 100kΩ resistor driven to 0V: P = 0.11mW Significant power savings in applications with frequent opposite-level driving 註 Considerations: Slower response times may affect interrupt recognition May be insufficient for noisy environments requiring strong bias Check external driver current capability against pull resistor current
Use	High Pull Resistor Strength (Low Resistance Value) Selects lower resistance value for internal pull resistors, providing stronger bias current. Results in higher power consumption but offers better noise immunity and faster signal transitions. Requires external drivers with higher current capability to override. 高上拉/下拉電阻強度（低電阻值），適用於需要強偏壓和快速響應的應用 Lower resistance value (typically in low tens of kΩ range) Stronger bias current provides better noise immunity Faster signal rise/fall times due to lower R×C time constants External drivers need more current to reliably override pull resistor Better signal integrity in electrically noisy environments Higher power consumption when driven to opposite level 註 Higher current consumption requires careful power budget analysis External drivers must have sufficient current sink/source capability Better choice for timing-critical and noise-sensitive applications Cases: Electrically noisy environments requiring strong bias High-speed digital interfaces with tight timing requirements I2C bus applications requiring specific pull-up strength for speed Button/switch inputs in noisy industrial environments Interrupt inputs that must be immune to false triggering Applications where external drivers have adequate current capability Reset and critical control signals requiring robust operation
I2C	Bus Considerations: I2C rise time: t_r ≈ R_pull × C_bus Lower pull resistance enables higher bus speeds Must balance speed requirements with power consumption Standard I2C: 400pF × 10kΩ = 4μs rise time (suitable for standard mode) Fast I2C: May require lower pull resistance for adequate performance
Power	Impact: If pull-up driven low: P = V²/R, lower R = higher power For 3.3V with 10kΩ resistor driven to 0V: P = 1.1mW 10× higher power than LOW setting - consider duty cycle 註 Design Considerations: Verify external driver current specifications against pull current Consider thermal effects in high duty cycle applications May be necessary for reliable operation in harsh electrical environments Essential for maintaining signal integrity in high-speed applications 警告 Higher power consumption - analyze power budget carefully External drivers must meet increased current requirements May cause heating in high-frequency switching applications

Rate

enum struct mcxa153::chip::port::Rate : bool

strong

GPIO Pin Output Slew Rate Configuration.

Enumeration for controlling the slew rate (rise/fall time) of GPIO output signals. Slew rate determines how quickly the output voltage transitions between logic levels, affecting signal integrity, electromagnetic interference (EMI), and power consumption.

GPIO引腳輸出轉換速率配置列舉。 轉換速率決定輸出電壓在邏輯電平間轉換的快慢，影響信號完整性、EMI和功耗。

• Controls the rate of voltage change (dV/dt) during output transitions
• Affects electromagnetic interference (EMI) generation
• Influences signal integrity and timing characteristics
• Impacts power consumption during switching
• Trade-off between speed and EMI/power considerations

註

Slew rate setting only affects output signals (not input behavior)

Faster slew rates improve timing but may increase EMI and power consumption

Slower slew rates reduce EMI but may affect signal timing requirements

Optimal setting depends on application speed requirements and EMI constraints

參閱

mcxa153::chip::port::DriveStrength for output current capability

mcxa153::chip::port::Config for complete pin configuration

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Use	Fast Slew Rate Configuration. Configures the pin for fast slew rate, providing rapid voltage transitions between logic levels. Optimizes signal timing performance but may increase electromagnetic interference and power consumption during switching. 快速轉換速率配置，適用於高速數位應用和時序關鍵系統 Rapid voltage transitions (high dV/dt) during output changes Minimizes propagation delays and setup/hold times Sharp signal edges for better timing precision Higher current peaks during switching transitions Improved signal integrity for high-speed digital communication Better performance driving capacitive loads 註 Default setting for most high-performance digital applications Essential for timing-critical interfaces and high-speed communication May require EMI mitigation measures in sensitive applications Cases: High-speed SPI/I2C communication interfaces Clock signal generation and distribution Fast digital control signals and chip selects High-frequency PWM outputs for motor control Precision timing applications requiring minimal jitter Digital interfaces with tight setup/hold requirements Fast interrupt and trigger signal generation
Timing	Benefits: Reduced propagation delay through output driver Faster rise/fall times improve timing margins Better performance with long PCB traces and cable connections Enhanced signal quality at receiving end for high-speed data
Performance	Characteristics: Rise/fall times: typically few nanoseconds Suitable for MHz-range switching frequencies Maintains signal integrity at higher data rates Reduces timing uncertainty in critical paths 警告 Higher EMI generation - may require filtering/shielding Increased power consumption during switching transitions May cause ringing and overshoot on long transmission lines Can induce crosstalk in adjacent signal traces 註 EMI Mitigation Strategies: Use proper ground planes and signal routing Consider series termination resistors for long traces Implement power supply decoupling and filtering Use differential signaling for critical high-speed signals
Use	Slow Slew Rate Configuration. Configures the pin for slow slew rate, providing gradual voltage transitions between logic levels. Reduces electromagnetic interference and power consumption at the cost of slower signal timing performance. 慢速轉換速率配置，適用於EMI敏感和功耗關鍵的應用 Gradual voltage transitions (lower dV/dt) during output changes Reduced electromagnetic interference (EMI) generation Lower current peaks and reduced power consumption during switching Smoother signal edges reduce voltage overshoot and ringing Better compatibility with long transmission lines and cables Reduced crosstalk to adjacent signal traces 註 Recommended for EMI-sensitive applications and power-conscious designs Essential for regulatory EMI compliance in many applications May not meet timing requirements for high-speed interfaces Cases: EMI-sensitive applications (medical devices, RF systems) Battery-powered devices prioritizing power efficiency Long cable connections prone to signal reflection Industrial environments with strict EMI regulations Audio applications sensitive to digital switching noise Low-speed control signals and status indicators Automotive applications with EMI compliance requirements
EMI	Benefits: Reduced harmonics in frequency spectrum Lower peak electromagnetic emissions Better EMI compliance margin for regulatory approval Reduced interference with sensitive analog circuits Less crosstalk in densely packed PCB layouts
Power	Savings: Lower I²R losses during switching transitions Reduced supply current spikes and ground bounce Less stress on power supply decoupling capacitors Improved power efficiency in high switching frequency applications
Signal	Integrity Benefits: Reduced overshoot and undershoot on signal transitions Better impedance matching with transmission lines Less ringing and oscillation on long traces Improved signal quality with capacitive loads 警告 Slower signal transitions may affect timing-critical applications May not meet setup/hold requirements for high-speed interfaces Reduced noise margins due to slower edge rates May be inadequate for driving heavy capacitive loads quickly 註 Application Considerations: Verify timing requirements can be met with slower transitions May require longer setup/hold times for receiving devices Consider trade-offs between EMI reduction and performance Ideal for applications where EMI compliance is mandatory Typical Characteristics: Rise/fall times: typically tens of nanoseconds Suitable for kHz to low MHz switching frequencies Significant reduction in EMI spectrum content 20-50% reduction in switching power consumption

Shift

enum struct mcxa153::chip::port::Shift : unsigned int

strong

Shift Enumeration for Port Control Register Bit Positions.

This enumeration defines the bit positions for various fields in the Port Control Register (PCR). Each value represents the bit position of a specific configuration option for GPIO pins.

此列舉定義了埠控制暫存器 (PCR) 中各個欄位的位元位置。 每個值代表GPIO引腳特定配置選項的位元位置。

註

Use these values with bitwise operations to configure pin settings

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VERID_FEATURE	VERID_FEATURE - Feature Specification Number. Version ID Feature Specification Number 版本ID功能規格編號 [0b0000000000000000] Basic implementation 基本實作
VERID_MINOR	VERID_MINOR - Minor Version Number. Version ID Minor Version Number 版本ID次要版本號
VERID_MAJOR	VERID_MAJOR - Major Version Number. Version ID Major Version Number 版本ID主要版本號
GPCLR_GPWD	GPCLR_GPWD - Global Pin Write Data. Global Pin Control Low - Global Pin Write Data 全域接腳控制低位 - 全域接腳寫入資料
GPCLR_GPWE0	GPCLR_GPWE0 - Global Pin Write Enable. Global Pin Control Low - Global Pin Write Enable 全域接腳控制低位 - 全域接腳寫入啟用 [0b0] Not updated 未更新 [0b1] Updated 已更新
GPCLR_GPWE1	GPCLR_GPWE1 - Global Pin Write Enable. Global Pin Control Low - Global Pin Write Enable 全域接腳控制低位 - 全域接腳寫入啟用 [0b0] Not updated 未更新 [0b1] Updated 已更新
GPCLR_GPWE2	GPCLR_GPWE2 - Global Pin Write Enable. Global Pin Control Low - Global Pin Write Enable 全域接腳控制低位 - 全域接腳寫入啟用 [0b0] Not updated 未更新 [0b1] Updated 已更新
GPCLR_GPWE3	GPCLR_GPWE3 - Global Pin Write Enable. Global Pin Control Low - Global Pin Write Enable 全域接腳控制低位 - 全域接腳寫入啟用 [0b0] Not updated 未更新 [0b1] Updated 已更新
GPCLR_GPWE4	GPCLR_GPWE4 - Global Pin Write Enable. Global Pin Control Low - Global Pin Write Enable 全域接腳控制低位 - 全域接腳寫入啟用 [0b0] Not updated 未更新 [0b1] Updated 已更新
GPCLR_GPWE5	GPCLR_GPWE5 - Global Pin Write Enable. Global Pin Control Low - Global Pin Write Enable 全域接腳控制低位 - 全域接腳寫入啟用 [0b0] Not updated 未更新 [0b1] Updated 已更新
GPCLR_GPWE6	GPCLR_GPWE6 - Global Pin Write Enable. Global Pin Control Low - Global Pin Write Enable 全域接腳控制低位 - 全域接腳寫入啟用 [0b0] Not updated 未更新 [0b1] Updated 已更新
GPCLR_GPWE7	GPCLR_GPWE7 - Global Pin Write Enable. Global Pin Control Low - Global Pin Write Enable 全域接腳控制低位 - 全域接腳寫入啟用 [0b0] Not updated 未更新 [0b1] Updated 已更新
GPCLR_GPWE8	GPCLR_GPWE8 - Global Pin Write Enable. Global Pin Control Low - Global Pin Write Enable 全域接腳控制低位 - 全域接腳寫入啟用 [0b0] Not updated 未更新 [0b1] Updated 已更新
GPCLR_GPWE9	GPCLR_GPWE9 - Global Pin Write Enable. Global Pin Control Low - Global Pin Write Enable 全域接腳控制低位 - 全域接腳寫入啟用 [0b0] Not updated 未更新 [0b1] Updated 已更新
GPCLR_GPWE10	GPCLR_GPWE10 - Global Pin Write Enable. Global Pin Control Low - Global Pin Write Enable 全域接腳控制低位 - 全域接腳寫入啟用 [0b0] Not updated 未更新 [0b1] Updated 已更新
GPCLR_GPWE11	GPCLR_GPWE11 - Global Pin Write Enable. Global Pin Control Low - Global Pin Write Enable 全域接腳控制低位 - 全域接腳寫入啟用 [0b0] Not updated 未更新 [0b1] Updated 已更新
GPCLR_GPWE12	GPCLR_GPWE12 - Global Pin Write Enable. Global Pin Control Low - Global Pin Write Enable 全域接腳控制低位 - 全域接腳寫入啟用 [0b0] Not updated 未更新 [0b1] Updated 已更新
GPCLR_GPWE13	GPCLR_GPWE13 - Global Pin Write Enable. Global Pin Control Low - Global Pin Write Enable 全域接腳控制低位 - 全域接腳寫入啟用 [0b0] Not updated 未更新 [0b1] Updated 已更新
GPCLR_GPWE14	GPCLR_GPWE14 - Global Pin Write Enable. Global Pin Control Low - Global Pin Write Enable 全域接腳控制低位 - 全域接腳寫入啟用 [0b0] Not updated 未更新 [0b1] Updated 已更新
GPCLR_GPWE15	GPCLR_GPWE15 - Global Pin Write Enable. Global Pin Control Low - Global Pin Write Enable 全域接腳控制低位 - 全域接腳寫入啟用 [0b0] Not updated 未更新 [0b1] Updated 已更新
GPCHR_GPWD	GPCHR_GPWD - Global Pin Write Data. Global Pin Control High - Global Pin Write Data 全域接腳控制高位 - 全域接腳寫入資料
GPCHR_GPWE16	GPCHR_GPWE16 - Global Pin Write Enable. Global Pin Control High - Global Pin Write Enable 全域接腳控制高位 - 全域接腳寫入啟用 [0b0] Not updated 未更新 [0b1] Updated 已更新
GPCHR_GPWE17	GPCHR_GPWE17 - Global Pin Write Enable. Global Pin Control High - Global Pin Write Enable 全域接腳控制高位 - 全域接腳寫入啟用 [0b0] Not updated 未更新 [0b1] Updated 已更新
GPCHR_GPWE18	GPCHR_GPWE18 - Global Pin Write Enable. Global Pin Control High - Global Pin Write Enable 全域接腳控制高位 - 全域接腳寫入啟用 [0b0] Not updated 未更新 [0b1] Updated 已更新
GPCHR_GPWE19	GPCHR_GPWE19 - Global Pin Write Enable. Global Pin Control High - Global Pin Write Enable 全域接腳控制高位 - 全域接腳寫入啟用 [0b0] Not updated 未更新 [0b1] Updated 已更新
GPCHR_GPWE20	GPCHR_GPWE20 - Global Pin Write Enable. Global Pin Control High - Global Pin Write Enable 全域接腳控制高位 - 全域接腳寫入啟用 [0b0] Not updated 未更新 [0b1] Updated 已更新
GPCHR_GPWE21	GPCHR_GPWE21 - Global Pin Write Enable. Global Pin Control High - Global Pin Write Enable 全域接腳控制高位 - 全域接腳寫入啟用 [0b0] Not updated 未更新 [0b1] Updated 已更新
GPCHR_GPWE22	GPCHR_GPWE22 - Global Pin Write Enable. Global Pin Control High - Global Pin Write Enable 全域接腳控制高位 - 全域接腳寫入啟用 [0b0] Not updated 未更新 [0b1] Updated 已更新
GPCHR_GPWE23	GPCHR_GPWE23 - Global Pin Write Enable. Global Pin Control High - Global Pin Write Enable 全域接腳控制高位 - 全域接腳寫入啟用 [0b0] Not updated 未更新 [0b1] Updated 已更新
GPCHR_GPWE24	GPCHR_GPWE24 - Global Pin Write Enable. Global Pin Control High - Global Pin Write Enable 全域接腳控制高位 - 全域接腳寫入啟用 [0b0] Not updated 未更新 [0b1] Updated 已更新
GPCHR_GPWE25	GPCHR_GPWE25 - Global Pin Write Enable. Global Pin Control High - Global Pin Write Enable 全域接腳控制高位 - 全域接腳寫入啟用 [0b0] Not updated 未更新 [0b1] Updated 已更新
GPCHR_GPWE26	GPCHR_GPWE26 - Global Pin Write Enable. Global Pin Control High - Global Pin Write Enable 全域接腳控制高位 - 全域接腳寫入啟用 [0b0] Not updated 未更新 [0b1] Updated 已更新
GPCHR_GPWE27	GPCHR_GPWE27 - Global Pin Write Enable. Global Pin Control High - Global Pin Write Enable 全域接腳控制高位 - 全域接腳寫入啟用 [0b0] Not updated 未更新 [0b1] Updated 已更新
GPCHR_GPWE28	GPCHR_GPWE28 - Global Pin Write Enable. Global Pin Control High - Global Pin Write Enable 全域接腳控制高位 - 全域接腳寫入啟用 [0b0] Not updated 未更新 [0b1] Updated 已更新
GPCHR_GPWE29	GPCHR_GPWE29 - Global Pin Write Enable. Global Pin Control High - Global Pin Write Enable 全域接腳控制高位 - 全域接腳寫入啟用 [0b0] Not updated 未更新 [0b1] Updated 已更新
GPCHR_GPWE30	GPCHR_GPWE30 - Global Pin Write Enable. Global Pin Control High - Global Pin Write Enable 全域接腳控制高位 - 全域接腳寫入啟用 [0b0] Not updated 未更新 [0b1] Updated 已更新
GPCHR_GPWE31	GPCHR_GPWE31 - Global Pin Write Enable. Global Pin Control High - Global Pin Write Enable 全域接腳控制高位 - 全域接腳寫入啟用 [0b0] Not updated 未更新 [0b1] Updated 已更新
CONFIG_RANGE	CONFIG_RANGE - Port Voltage Range. Configuration - Port Voltage Range 配置 - 接腳電壓範圍 [0b0] 1.71 V-3.6 V [0b1] 2.70 V-3.6 V
CALIB0_NCAL	CALIB0_NCAL - Calibration of NMOS Output Driver. Calibration 0 - Calibration of NMOS Output Driver 校準0 - NMOS輸出驅動器校準
CALIB0_PCAL	CALIB0_PCAL - Calibration of PMOS Output Driver. Calibration 0 - Calibration of PMOS Output Driver 校準0 - PMOS輸出驅動器校準
CALIB1_NCAL	CALIB1_NCAL - Calibration of NMOS Output Driver. Calibration 1 - Calibration of NMOS Output Driver 校準1 - NMOS輸出驅動器校準
CALIB1_PCAL	CALIB1_PCAL - Calibration of PMOS Output Driver. Calibration 1 - Calibration of PMOS Output Driver 校準1 - PMOS輸出驅動器校準
PCR_PS	PCR_PS - Pull Select. Pin Control Register Pull Select 接腳控制暫存器拉選 [0b0] Enables internal pulldown resistor 啟用內部下拉電阻 [0b1] Enables internal pullup resistor 啟用內部上拉電阻
PCR_PE	PCR_PE - Pull Enable. Pin Control Register Pull Enable 接腳控制暫存器拉啟用 [0b0] Disables 停用 [0b1] Enables 啟用
PCR_PV	PCR_PV - Pull Value. Pin Control Register Pull Value 接腳控制暫存器拉值 [0b0] Low 低 [0b1] High 高
PCR_SRE	PCR_SRE - Slew Rate Enable. Pin Control Register Slew Rate Enable 接腳控制暫存器斜率啟用 [0b0] Fast 快速 [0b1] Slow 緩慢
PCR_PFE	PCR_PFE - Passive Filter Enable. Pin Control Register Passive Filter Enable 接腳控制暫存器被動濾波器啟用 [0b0] Disables 停用 [0b1] Enables 啟用
PCR_ODE	PCR_ODE - Open Drain Enable. Pin Control Register Open Drain Enable 接腳控制暫存器開放排水啟用 [0b0] Disables 停用 [0b1] Enables 啟用
PCR_DSE	PCR_DSE - Drive Strength Enable. Pin Control Register Drive Strength Enable 接腳控制暫存器驅動強度啟用 [0b0] Low 低 [0b1] High 高
PCR_DSE1	PCR_DSE1 - Drive Strength Enable. Pin Control Register Drive Strength Enable 接腳控制暫存器驅動強度啟用 [0b0] Normal 正常 [0b1] Double 雙倍
PCR_MUX	PCR_MUX - Pin Multiplex Control. Pin Control Register Pin Multiplex Control 接腳控制暫存器接腳多工控制 [0b0000] Alternative 0 (GPIO) 替代0 (GPIO) [0b0001] Alternative 1 (chip-specific) 替代1 (芯片特定) [0b0010] Alternative 2 (chip-specific) 替代2 (芯片特定) [0b0011] Alternative 3 (chip-specific) 替代3 (芯片特定) [0b0100] Alternative 4 (chip-specific) 替代4 (芯片特定) [0b0101] Alternative 5 (chip-specific) 替代5 (芯片特定) [0b0110] Alternative 6 (chip-specific) 替代6 (芯片特定) [0b0111] Alternative 7 (chip-specific) 替代7 (芯片特定) [0b1000] Alternative 8 (chip-specific) 替代8 (芯片特定) [0b1001] Alternative 9 (chip-specific) 替代9 (芯片特定) [0b1010] Alternative 10 (chip-specific) 替代10 (芯片特定) [0b1011] Alternative 11 (chip-specific) 替代11 (芯片特定) [0b1100] Alternative 12 (chip-specific) 替代12 (芯片特定) [0b1101] Alternative 13 (chip-specific) 替代13 (芯片特定)
PCR_IBE	PCR_IBE - Input Buffer Enable. Pin Control Register Input Buffer Enable 接腳控制暫存器輸入緩衝啟用 [0b0] Disables 停用 [0b1] Enables 啟用
PCR_INV	PCR_INV - Invert Input. Pin Control Register Invert Input 接腳控制暫存器反向輸入 [0b0] Does not invert 不反向 [0b1] Inverts 反向
PCR_LK	PCR_LK - Lock Register. Pin Control Register Lock bit 接腳控制暫存器鎖定位元 [0b0] Does not lock 不鎖定 [0b1] Locks 鎖定

VoltageRange

enum struct mcxa153::chip::port::VoltageRange : bool

strong

GPIO Port Operating Voltage Range Configuration.

Enumeration for configuring the operating voltage range of GPIO ports. This setting optimizes the port's electrical characteristics and performance for different supply voltage conditions, ensuring reliable operation and optimal power consumption across the specified voltage range.

GPIO埠操作電壓範圍配置列舉。 此設定針對不同供電電壓條件優化埠的電氣特性和性能。

• Configures internal voltage references and thresholds
• Optimizes input/output buffer characteristics for voltage range
• Affects power consumption and signal timing characteristics
• Ensures reliable logic level detection across voltage range
• May influence analog function performance and accuracy

註

Voltage range setting should match actual supply voltage conditions

Incorrect range selection may result in unreliable operation

Setting affects all pins within the port simultaneously

May impact analog functions requiring precise voltage references

警告

Operating outside the selected voltage range may cause malfunction

參閱

MCXA153 Electrical Specifications for detailed voltage requirements

mcxa153::chip::port::Config for complete pin configuration

自

v1.0.0

列舉值
Use	Wide Voltage Range (1.71V - 3.6V) Configures the port for operation across a wide voltage range from 1.71V to 3.6V. Optimizes electrical characteristics for applications requiring operation at lower supply voltages, including battery-powered systems and low-power designs. 寬電壓範圍(1.71V - 3.6V)，適用於低功耗和電池供電應用 Minimum Supply Voltage: 1.71V Maximum Supply Voltage: 3.6V Optimized for low-voltage operation and battery applications Wider operating range provides greater flexibility May have slightly relaxed timing specifications at lower voltages Input/output thresholds scaled for wide voltage range 註 Preferred setting for battery-powered and low-power applications Provides maximum voltage range flexibility May have slightly higher power consumption due to wider range optimization Cases: Battery-powered IoT devices and sensors Portable electronics with variable supply voltage Systems using coin cell or single-cell Li-ion batteries Low-power applications requiring extended battery life Mixed-voltage systems interfacing with low-voltage devices Applications requiring operation during power supply fluctuations
Battery	Application: // Configure for battery operation (1.8V - 3.3V typical) port_config.voltageRange = VoltageRange::RANGE_1V71_3V6; // This allows operation from fresh battery (3.3V) down to low battery (1.8V)
Electrical	Characteristics: VIL (Input Low): Typically 30% of VDD VIH (Input High): Typically 70% of VDD VOL (Output Low): Typically < 0.4V at IOL = 4mA VOH (Output High): Typically > VDD-0.4V at IOH = 4mA 註 Power Considerations: Slightly higher power consumption due to wide-range optimization Good for applications where voltage varies significantly Recommended when supply voltage may drop below 2.7V 警告 Ensure actual supply voltage stays within 1.71V - 3.6V range May have relaxed timing at minimum voltage - verify timing requirements
Use	Standard Voltage Range (2.70V - 3.6V) Configures the port for operation within the standard voltage range from 2.70V to 3.6V. Optimizes electrical characteristics for conventional 3.3V systems and applications with stable, regulated power supplies providing better performance characteristics. 標準電壓範圍(2.70V - 3.6V)，適用於穩定的3.3V系統和應用 Minimum Supply Voltage: 2.70V Maximum Supply Voltage: 3.6V Optimized for standard 3.3V operation Tighter voltage range enables better performance optimization Improved timing characteristics and noise margins Lower power consumption due to narrower range optimization 註 Recommended for stable 3.3V systems with regulated supplies Provides optimized performance for standard voltage applications Better timing characteristics compared to wide range setting Cases: Standard 3.3V microcontroller systems Applications with well-regulated power supplies High-performance digital interfaces requiring tight timing Systems where supply voltage is guaranteed above 2.7V Industrial applications with stable power distribution Communications systems with regulated 3.3V rails
Standard	System: // Configure for stable 3.3V system operation port_config.voltageRange = VoltageRange::RANGE_2V70_3V6; // Optimizes for best performance with regulated 3.3V supply
Improved	Electrical Characteristics: Better noise margins due to optimized thresholds Faster switching speeds at higher voltages Lower power consumption due to narrower optimization range More precise timing characteristics Enhanced signal integrity for high-speed applications
Typical	Applications: Desktop and embedded computer systems Industrial control systems with regulated supplies Communications equipment with standard 3.3V rails High-speed digital interfaces (SPI, I2C at maximum speeds) Precision analog applications requiring stable references 註 Performance Benefits: Optimized for 3.3V nominal operation Better timing margins and signal integrity Lower power consumption compared to wide range Enhanced noise immunity at standard voltages 警告 Supply voltage must not drop below 2.70V Not suitable for battery applications that may operate below 2.7V Verify power supply regulation and brown-out protection 註 Design Considerations: Ensure adequate power supply regulation Implement brown-out detection if supply may fluctuate Consider power supply tolerances and load regulation Verify minimum voltage under maximum load conditions

函式說明文件

operator+() [1/13]

bool mcxa153::chip::port::operator+ ( DriveStrength e )

constexpr

Operator Overload - Convert DriveStrength enum to bool.

Converts DriveStrength enumeration value to boolean for easy conditional testing. Useful for checking drive strength configuration in conditional statements.

將DriveStrength列舉值轉換為布林值，便於條件判斷

參數

e	DriveStrength enumeration value 驅動強度列舉值

傳回值

constexpr bool Boolean representation (false=LOW, true=HIGH)

operator+() [2/13]

bool mcxa153::chip::port::operator+ ( DriveStrengthDouble e )

constexpr

Operator Overload - Convert DriveStrengthDouble enum to bool.

Converts DriveStrengthDouble enumeration value to boolean for easy conditional testing. Useful for checking if double drive strength mode is enabled in conditional statements.

將DriveStrengthDouble列舉值轉換為布林值，便於條件判斷

參數

e	DriveStrengthDouble enumeration value 雙倍驅動強度列舉值

傳回值

constexpr bool Boolean representation (false=NORMAL, true=DOUBLE)

operator+() [3/13]

bool mcxa153::chip::port::operator+ ( InputBuffer e )

constexpr

Operator Overload - Convert InputBuffer enum to bool.

Converts InputBuffer enumeration value to boolean for easy conditional testing. Useful for checking if digital input buffer is enabled in conditional statements.

將InputBuffer列舉值轉換為布林值，便於條件判斷

參數

e	InputBuffer enumeration value 輸入緩衝器列舉值

傳回值

constexpr bool Boolean representation (false=DISABLE, true=ENABLE)

operator+() [4/13]

bool mcxa153::chip::port::operator+ ( Inverted e )

constexpr

Operator Overload - Convert Inverted enum to bool.

Converts Inverted enumeration value to boolean for easy conditional testing. Useful for checking if digital input inversion is enabled in conditional statements.

將Inverted列舉值轉換為布林值，便於條件判斷

參數

e	Inverted enumeration value 輸入反相列舉值

傳回值

constexpr bool Boolean representation (false=NORMAL, true=INVERT)

operator+() [5/13]

bool mcxa153::chip::port::operator+ ( Lock e )

constexpr

Operator Overload - Convert Lock enum to bool.

Converts Lock enumeration value to boolean for easy conditional testing. Useful for checking if pin control register is locked in conditional statements.

將Lock列舉值轉換為布林值，便於條件判斷

參數

e	Lock enumeration value 鎖定狀態列舉值

傳回值

constexpr bool Boolean representation (false=UNLOCK, true=LOCK)

operator+() [6/13]

unsigned char mcxa153::chip::port::operator+ ( Mux e )

constexpr

Operator Overload - Convert Mux enum to unsigned char.

Converts Mux enumeration value to unsigned char for direct register assignment. Useful for setting multiplexer values in pin configuration registers.

將Mux列舉值轉換為無符號字元，便於直接暫存器賦值

參數

e	Mux enumeration value 多工器列舉值

傳回值

constexpr unsigned char Numeric multiplexer value (0-15)

operator+() [7/13]

bool mcxa153::chip::port::operator+ ( OpenDrain e )

constexpr

Operator Overload - Convert OpenDrain enum to bool.

Converts OpenDrain enumeration value to boolean for easy conditional testing. Useful for checking if open drain output mode is enabled in conditional statements.

將OpenDrain列舉值轉換為布林值，便於條件判斷

參數

e	OpenDrain enumeration value 開漏輸出列舉值

傳回值

constexpr bool Boolean representation (false=DISABLE, true=ENABLE)

operator+() [8/13]

bool mcxa153::chip::port::operator+ ( PassiveFilter e )

constexpr

Operator Overload - Convert PassiveFilter enum to bool.

Converts PassiveFilter enumeration value to boolean for easy conditional testing. Useful for checking if passive input filter is enabled in conditional statements.

將PassiveFilter列舉值轉換為布林值，便於條件判斷

參數

e	PassiveFilter enumeration value 被動濾波器列舉值

傳回值

constexpr bool Boolean representation (false=DISABLE, true=ENABLE)

operator+() [9/13]

unsigned char mcxa153::chip::port::operator+ ( Pull e )

constexpr

Operator Overload - Convert Pull enum to unsigned char.

Converts Pull enumeration value to unsigned char for direct register assignment. Useful for setting pull resistor configuration in pin control registers.

將Pull列舉值轉換為無符號字元，便於直接暫存器賦值

參數

e	Pull enumeration value 上拉/下拉電阻列舉值

傳回值

constexpr unsigned char Numeric pull resistor configuration value

operator+() [10/13]

bool mcxa153::chip::port::operator+ ( PullResistor e )

constexpr

Operator Overload - Convert PullResistor enum to bool.

Converts PullResistor enumeration value to boolean for easy conditional testing. Useful for checking pull resistor strength configuration in conditional statements.

將PullResistor列舉值轉換為布林值，便於條件判斷

參數

e	PullResistor enumeration value 上拉/下拉電阻強度列舉值

傳回值

constexpr bool Boolean representation (false=LOW, true=HIGH)

operator+() [11/13]

bool mcxa153::chip::port::operator+ ( Rate e )

constexpr

Operator Overload - Convert Rate enum to bool.

Converts Rate enumeration value to boolean for easy conditional testing. Useful for checking slew rate configuration in conditional statements.

將Rate列舉值轉換為布林值，便於條件判斷

參數

e	Rate enumeration value 轉換速率列舉值

傳回值

constexpr bool Boolean representation (false=FAST, true=SLOW)

operator+() [12/13]

unsigned int mcxa153::chip::port::operator+ ( Shift e )

constexpr

Shift Operator Overloading - Convert Enum To Unsigned Integer.

Converts the shift enum value to an unsigned integer. 將位移列舉值轉換為無符號整數。

參數

e	Shift enum to convert 要轉換的位移列舉

傳回值

constexpr unsigned int Converted unsigned integer value 轉換後的無符號整數值

operator+() [13/13]

bool mcxa153::chip::port::operator+ ( VoltageRange e )

constexpr

Operator Overload - Convert VoltageRange enum to bool.

Converts VoltageRange enumeration value to boolean for easy conditional testing. Useful for checking voltage range configuration in conditional statements.

將VoltageRange列舉值轉換為布林值，便於條件判斷

參數

e	VoltageRange enumeration value 電壓範圍列舉值

傳回值

constexpr bool Boolean representation (false=1.71V-3.6V, true=2.70V-3.6V)