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mcxa153::chip::port::Register 結構 參考文件

PORT (Pin Multiplexing and Control) Peripheral Register Structure. 更多...

#include <Register.h>

公開屬性

__I uint32 verid
 Version ID Register.
 
uint8 reserved_0 [12]
 Reserved Space (0x4-0xF)
 
__O uint32 gpclr
 Global Pin Control Low Register.
 
__O uint32 gpchr
 Global Pin Control High Register.
 
uint8 reserved_1 [8]
 Reserved Space (0x18-0x1F)
 
__IO uint32 config
 Configuration Register.
 
uint8 reserved_2 [60]
 Reserved Space (0x24-0x5F)
 
__IO uint32 calib0
 Calibration 0 Register.
 
__IO uint32 calib1
 Calibration 1 Register.
 
uint8 reserved_3 [24]
 Reserved Space (0x68-0x7F)
 
__IO uint32 pcr [32]
 

詳細描述

PORT (Pin Multiplexing and Control) Peripheral Register Structure.

Memory-mapped register structure for accessing PORT peripheral registers. The PORT peripheral controls pin multiplexing, electrical characteristics, and configuration for all GPIO pins in the system.

PORT周邊暫存器結構體，用於控制引腳多工、電氣特性和所有GPIO引腳配置。

  • Controls pin multiplexing (MUX) selection for peripheral functions
  • Configures electrical characteristics (pull resistors, drive strength, slew rate)
  • Manages pin control and global pin operations
  • Supports pin calibration for analog functions (on selected ports)
  • Provides version identification for software compatibility
註
Register availability varies by PORT instance (PORT0-PORT3)
Some registers (calib0/calib1) only available on PORT1 and PORT3
PCR array indices correspond to physical pin numbers
All register accesses should be aligned to 32-bit boundaries
自
v1.0.0

資料成員說明文件

◆ calib0

__IO uint32 mcxa153::chip::port::Register::calib0

Calibration 0 Register.

Calibration register for analog pin functions and electrical characteristics. Used to fine-tune pin electrical parameters for optimal analog performance.

校準0暫存器，用於類比引腳功能和電氣特性校準

  • Offset: 0x60
  • Access: Read/Write (__IO)
  • Width: 32-bit
  • Reset: Device-specific value
  • Availability: PORT1 and PORT3 only
註
Only available on PORT1 and PORT3 instances
Missing on PORT0 and PORT2 instances
Used for analog function calibration and optimization
Specific calibration parameters are implementation-dependent
警告
Verify PORT instance before accessing this register
參閱
Device-specific documentation for calibration procedures

◆ calib1

__IO uint32 mcxa153::chip::port::Register::calib1

Calibration 1 Register.

Additional calibration register for analog pin functions and electrical characteristics. Provides extended calibration capabilities for complex analog functions.

校準1暫存器，提供額外的類比功能校準能力

  • Offset: 0x64
  • Access: Read/Write (__IO)
  • Width: 32-bit
  • Reset: Device-specific value
  • Availability: PORT1 and PORT3 only
註
Only available on PORT1 and PORT3 instances
Missing on PORT0 and PORT2 instances
Complements calib0 for comprehensive calibration control
Specific calibration parameters are implementation-dependent
警告
Verify PORT instance before accessing this register
參閱
Device-specific documentation for calibration procedures

◆ config

__IO uint32 mcxa153::chip::port::Register::config

Configuration Register.

General configuration register for PORT peripheral settings. Controls global PORT behavior and features.

PORT周邊配置暫存器

  • Offset: 0x20
  • Access: Read/Write (__IO)
  • Width: 32-bit
  • Reset: Device-specific value
註
Specific bit fields are implementation-dependent
May control global PORT features and operating modes
參閱
MCXA153 reference manual for detailed bit field definitions

◆ gpchr

__O uint32 mcxa153::chip::port::Register::gpchr

Global Pin Control High Register.

Write-only register for simultaneously controlling multiple pins (16-31) with a single register write operation. Provides atomic updates for coordinated pin state changes.

全域引腳控制高位暫存器，用於同時控制多個引腳

  • Offset: 0x14
  • Access: Write-Only (__O)
  • Width: 32-bit
  • Reset: 0x00000000

Bit Fields:

  • [15:0] GPWD: Global Pin Write Data for pins 16-31
  • [31:16] GPWE: Global Pin Write Enable for pins 16-31
註
Writing 1 to GPWE[n] updates pin (16+n) with corresponding GPWD[n] value
Writing 0 to GPWE[n] leaves pin (16+n) unchanged
Complements GPCLR for complete 32-pin coverage
Only affects pins configured as GPIO outputs

◆ gpclr

__O uint32 mcxa153::chip::port::Register::gpclr

Global Pin Control Low Register.

Write-only register for simultaneously controlling multiple pins (0-15) with a single register write operation. Provides atomic updates for coordinated pin state changes.

全域引腳控制低位暫存器，用於同時控制多個引腳

  • Offset: 0x10
  • Access: Write-Only (__O)
  • Width: 32-bit
  • Reset: 0x00000000

Bit Fields:

  • [15:0] GPWD: Global Pin Write Data for pins 0-15
  • [31:16] GPWE: Global Pin Write Enable for pins 0-15
註
Writing 1 to GPWE[n] updates pin n with corresponding GPWD[n] value
Writing 0 to GPWE[n] leaves pin n unchanged
Enables atomic updates of multiple pins simultaneously
Only affects pins configured as GPIO outputs

◆ reserved_0

uint8 mcxa153::chip::port::Register::reserved_0[12]

Reserved Space (0x4-0xF)

Reserved memory space in the register map. These bytes should not be accessed.

保留記憶體空間

  • Offset: 0x4-0xF (12 bytes)
  • Access: Should not be accessed
警告
Do not read from or write to this reserved space

◆ reserved_1

uint8 mcxa153::chip::port::Register::reserved_1[8]

Reserved Space (0x18-0x1F)

Reserved memory space in the register map. These bytes should not be accessed.

保留記憶體空間

  • Offset: 0x18-0x1F (8 bytes)
  • Access: Should not be accessed
警告
Do not read from or write to this reserved space

◆ reserved_2

uint8 mcxa153::chip::port::Register::reserved_2[60]

Reserved Space (0x24-0x5F)

Reserved memory space in the register map. These bytes should not be accessed.

保留記憶體空間

  • Offset: 0x24-0x5F (60 bytes)
  • Access: Should not be accessed
警告
Do not read from or write to this reserved space

◆ reserved_3

uint8 mcxa153::chip::port::Register::reserved_3[24]

Reserved Space (0x68-0x7F)

Reserved memory space in the register map. These bytes should not be accessed.

保留記憶體空間

  • Offset: 0x68-0x7F (24 bytes)
  • Access: Should not be accessed
警告
Do not read from or write to this reserved space

◆ verid

__I uint32 mcxa153::chip::port::Register::verid

Version ID Register.

Read-only register containing version and feature information for the PORT peripheral. Used for software compatibility checking and feature detection.

PORT周邊版本識別暫存器

  • Offset: 0x0
  • Access: Read-Only (__I)
  • Width: 32-bit
  • Reset: Device-specific value

Bit Fields (typical):

  • [15:0] FEATURE: Feature specification number
  • [23:16] MINOR: Minor version number
  • [31:24] MAJOR: Major version number
註
Value is design-dependent and varies by device implementation
Use for software compatibility verification and feature detection
參閱
MCXA153 reference manual for specific bit field definitions
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