PORT Pin Configuration Structure. 更多...

#include <Config.h>

公開屬性
Pull	pullSelect: 2
	Pull Resistor Configuration.

PullResistor	pullValueSelect: 1
	Pull Resistor Value Selection.

Rate	slewRate: 1
	Slew Rate Control.

PassiveFilter	passiveFilterEnable: 1
	Passive Filter Enable.

OpenDrain	openDrainEnable: 1
	Open Drain Output Enable.

DriveStrength	driveStrength: 1
	Drive Strength Control.

DriveStrengthDouble	driveStrengthDouble: 1
	Double Drive Strength Enable.

Mux	mux: 4
	Pin Multiplexer Configuration.

InputBuffer	inputBuffer: 1
	Input Buffer Configuration.

Inverted	invertInput: 1
	Input Inversion Control.

uint16	reserved1: 1
	Reserved Bit Field.

Lock	lockRegister: 1
	Pin Control Register Lock.

詳細描述

PORT Pin Configuration Structure.

Bit-field structure for configuring individual GPIO pin properties and characteristics. This structure maps directly to the PORT Pin Control Register (PCR) layout, providing a convenient way to configure all pin attributes in a single operation.

GPIO引腳配置結構體，用於配置個別GPIO引腳的屬性和特性。此結構直接映射到PORT引腳控制暫存器(PCR)佈局。

Total Size: 16-bit (matches PCR register width)
Bit-packed structure for efficient memory usage
Each field corresponds to specific PCR register bits
Supports atomic pin configuration updates

註: This structure should be used with PORT peripheral registers; All bit fields are packed in little-endian order; Reserved bits should not be modified

自: v1.0.0

資料成員說明文件

◆ driveStrength

DriveStrength mcxa153::chip::port::Config::driveStrength

Drive Strength Control.

Controls the output driver strength for normal operation. Affects current drive capability and signal edge rates.

輸出驅動強度控制

Bit Field: [6]
Width: 1 bit
Values: See DriveStrength enumeration (High/Low)

註: Higher drive strength increases power consumption; Lower drive strength may not drive heavy loads adequately

參閱: mcxa153::chip::port::DriveStrength for strength options

◆ driveStrengthDouble

DriveStrengthDouble mcxa153::chip::port::Config::driveStrengthDouble

Double Drive Strength Enable.

Enables double drive strength mode for maximum current capability. Provides enhanced drive strength for heavy loads or long traces.

雙倍驅動強度模式啟用

Bit Field: [7]
Width: 1 bit
Values: See DriveStrengthDouble enumeration

註: Significantly increases power consumption; Use only when maximum drive capability is required

參閱: mcxa153::chip::port::DriveStrengthDouble for enable/disable options

◆ inputBuffer

InputBuffer mcxa153::chip::port::Config::inputBuffer

Input Buffer Configuration.

Enables/disables the input buffer for digital input functionality. When disabled, pin cannot be read as digital input.

輸入緩衝器配置

Bit Field: [12]
Width: 1 bit
Values: See InputBuffer enumeration

註: Disable for analog-only pins to reduce power consumption; Must be enabled for digital input operations

參閱: mcxa153::chip::port::InputBuffer for configuration options

◆ invertInput

Inverted mcxa153::chip::port::Config::invertInput

Input Inversion Control.

Enables/disables input signal inversion before processing. Inverts the logic level of input signals at the pin level.

輸入信號反相控制

Bit Field: [13]
Width: 1 bit
Values: See Inverted enumeration

註: Inversion occurs before input reaches peripheral; Useful for active-low signal interfacing

參閱: mcxa153::chip::port::Inverted for inversion options

◆ lockRegister

Lock mcxa153::chip::port::Config::lockRegister

Pin Control Register Lock.

Locks/unlocks the pin configuration to prevent accidental changes. When locked, other configuration bits cannot be modified.

引腳控制暫存器鎖定

Bit Field: [15]
Width: 1 bit
Values: See Lock enumeration
Scope: Locks bits [14:0] of this register

註: Once locked, configuration is protected until reset; Useful for critical pin configurations

參閱: mcxa153::chip::port::Lock for lock/unlock options

◆ mux

Mux mcxa153::chip::port::Config::mux

Pin Multiplexer Configuration.

Selects the pin function from available peripheral alternatives. Determines which peripheral (GPIO, UART, SPI, etc.) controls the pin.

引腳多工器配置

Bit Field: [11:8]
Width: 4 bits
Values: See Mux enumeration for available functions

註: MUX setting determines pin's primary function; Each pin may support different peripheral functions

參閱: mcxa153::chip::port::Mux for available multiplexer options

◆ openDrainEnable

OpenDrain mcxa153::chip::port::Config::openDrainEnable

Open Drain Output Enable.

Configures the pin output stage as open drain (open collector). In open drain mode, pin can only pull low or float (high-Z).

開漏輸出模式啟用

Bit Field: [5]
Width: 1 bit
Values: See OpenDrain enumeration

註: Requires external pull-up resistor for logic high; Useful for wired-OR configurations and I2C interfaces

參閱: mcxa153::chip::port::OpenDrain for configuration options

◆ passiveFilterEnable

PassiveFilter mcxa153::chip::port::Config::passiveFilterEnable

Passive Filter Enable.

Enables/disables the passive input filter to reduce noise sensitivity. Helps filter out high-frequency noise on input signals.

被動輸入濾波器啟用控制

Bit Field: [4]
Width: 1 bit
Values: See PassiveFilter enumeration

註: Filtering may introduce slight input delay; Useful for noisy environments or long traces

參閱: mcxa153::chip::port::PassiveFilter for enable/disable options

◆ pullSelect

Pull mcxa153::chip::port::Config::pullSelect

Pull Resistor Configuration.

Configures the internal pull resistor setting for the pin. Determines whether pull-up, pull-down, or no pull resistor is enabled.

內部上拉/下拉電阻配置

Bit Field: [1:0]
Width: 2 bits
Values: See Pull enumeration for valid options

參閱: mcxa153::chip::port::Pull for available pull resistor options

◆ pullValueSelect

PullResistor mcxa153::chip::port::Config::pullValueSelect

Pull Resistor Value Selection.

Selects the resistance value when pull resistor is enabled. Provides different resistance strengths for pull-up/pull-down.

上拉/下拉電阻阻值選擇

Bit Field: [2]
Width: 1 bit
Values: See PullResistor enumeration

註: Only effective when pullSelect is not disabled

參閱: mcxa153::chip::port::PullResistor for resistance values

◆ reserved1

uint16 mcxa153::chip::port::Config::reserved1

Reserved Bit Field.

Reserved bit that should not be modified. Keep at reset value for proper operation.

保留位元欄位

Bit Field: [14]
Width: 1 bit
Value: Should remain 0

警告: Do not modify this field

註: Reserved for future functionality

◆ slewRate

Rate mcxa153::chip::port::Config::slewRate

Slew Rate Control.

Controls the output signal rise/fall time characteristics. Affects electromagnetic interference (EMI) and signal integrity.

輸出信號轉換速率控制

Bit Field: [3]
Width: 1 bit
Values: See Rate enumeration (Fast/Slow)

註: Fast slew rate may increase EMI but improves signal timing; Slow slew rate reduces EMI but may affect signal quality

參閱: mcxa153::chip::port::Rate for available slew rates

此結構(structure) 文件是由下列檔案中產生:

Config.h

公開屬性