PORT Peripheral Version Information Structure.
Structure for parsing and accessing PORT peripheral version information from the VERID register. Provides a convenient way to extract version components and check software compatibility with hardware implementation.
PORT周邊版本資訊結構體,用於解析VERID暫存器的版本資訊。
- Maps directly to VERID register bit fields
- Enables version-based feature detection and compatibility checking
- Supports software adaptation to different hardware revisions
- Used for runtime hardware capability discovery
- Little-endian byte ordering matches register layout
- 註
- Structure layout matches VERID register bit field organization
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Version numbers follow semantic versioning principles
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Feature number indicates available peripheral capabilities
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Use for runtime hardware/software compatibility verification
- 參閱
- mcxa153::chip::port::Register::verid for source register
- 自
- v1.0.0