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公開方法(Public Methods) | 靜態公開方法(Static Public Methods) | 全部成員列表
chip::syscon::SYSCON 類別 參考文件final
類別chip::syscon::SYSCON的繼承圖:
mframe::lang::Object mframe::lang::Interface

公開方法(Public Methods)

virtual ~SYSCON (void) override
 Destroy the object.
 
- 公開方法(Public Methods) 繼承自 mframe::lang::Object
 Object (void)
 Construct a new Object object.
 
virtual ~Object (void) override
 Destroy the Object object.
 
void * operator new (size_t n)
 
void * operator new (size_t n, void *p)
 
mframe::lang::Object & getObject (void) override
 取得類Object
 
void delay (int milliseconds) const
 函數 delay 等待內核滴答中指定的時間段。 對於1的值，系統等待直到下一個計時器滴答發生。 實際時間延遲最多可能比指定時間少一個計時器滴答聲，即在下一個系統滴答聲發生之前立即調用 osDelay(1)，線程會立即重新安排。
 
bool equals (Object *object) const
 函數 delay 等待內核滴答中指定的時間段。 對於1的值，系統等待直到下一個計時器滴答發生。 實際時間延遲最多可能比指定時間少一個計時器滴答聲，即在下一個系統滴答聲發生之前立即調用 osDelay(1)，線程會立即重新安排。
 
bool equals (Object &object) const
 函數 delay 等待內核滴答中指定的時間段。 對於1的值，系統等待直到下一個計時器滴答發生。 實際時間延遲最多可能比指定時間少一個計時器滴答聲，即在下一個系統滴答聲發生之前立即調用 osDelay(1)，線程會立即重新安排。
 
void wait (void) const
 導致當前線程等待，直到另一個線程調用此對象的notify()方法或notifyAll()方法，或指定的時間 已過。
 
bool wait (int timeout) const
 導致當前線程等待，直到另一個線程調用此對象的 notify()方法或 notifyAll()方法，或其他一些線 程中斷當前線程，或一定量的實時時間。
 
bool yield (void) const
 函數yield()將控制權傳遞給處於READY狀態且具有相同優先級的下一個線程。 如果在READY狀態下沒有其他優先級相同的線程，則當前線程繼續執行，不會發生線程切換。
 
int lock (void) const
 核心鎖定，在調用unlock以前將不會進行執行緒切換
 
int unlock (void) const
 核心解鎖。
 
mframe::sys::Thread * currentThread (void) const
 取得當前的執行緒
 
virtual int hashcode (void) const
 返回對象的哈希碼值。支持這種方法是為了散列表，如HashMap提供的那樣。
 
- 公開方法(Public Methods) 繼承自 mframe::lang::Interface
virtual ~Interface (void)=default
 Destroy the struct object.
 

靜態公開方法(Static Public Methods)

static constexpr uint32 REMAP_CPU0_SBUS (uint32 value)
 REMAP - CPU0_SBUS.
 
static constexpr uint32 REMAP_DMA0 (uint32 value)
 REMAP - DMA0.
 
static constexpr uint32 REMAP_USB0 (uint32 value)
 REMAP - USB0.
 
static constexpr uint32 REMAP_LOCK (uint32 value)
 REMAP - LOCK.
 
static constexpr uint32 AHBMATPRIO_CPU0_CBUS (uint32 value)
 AHBMATPRIO - CPU0_CBUS.
 
static constexpr uint32 AHBMATPRIO_CPU0_SBUS (uint32 value)
 AHBMATPRIO - CPU0_SBUS.
 
static constexpr uint32 AHBMATPRIO_DMA0 (uint32 value)
 AHBMATPRIO - DMA0.
 
static constexpr uint32 AHBMATPRIO_USB_FS_ENET (uint32 value)
 AHBMATPRIO - USB_FS_ENET.
 
static constexpr uint32 CPU0NSTCKCAL_TENMS (uint32 value)
 CPU0NSTCKCAL - TENMS.
 
static constexpr uint32 CPU0NSTCKCAL_SKEW (uint32 value)
 CPU0NSTCKCAL - SKEW.
 
static constexpr uint32 CPU0NSTCKCAL_NOREF (uint32 value)
 CPU0NSTCKCAL - NOREF.
 
static constexpr uint32 NMISRC_IRQCPU0 (uint32 value)
 NMISRC - IRQCPU0.
 
static constexpr uint32 NMISRC_NMIENCPU0 (uint32 value)
 NMISRC - NMIENCPU0.
 
static constexpr uint32 SLOWCLKDIV_RESET (uint32 value)
 SLOWCLKDIV - RESET.
 
static constexpr uint32 SLOWCLKDIV_HALT (uint32 value)
 SLOWCLKDIV - HALT.
 
static constexpr uint32 SLOWCLKDIV_UNSTAB (uint32 value)
 SLOWCLKDIV - UNSTAB.
 
static constexpr uint32 AHBCLKDIV_DIV (uint32 value)
 AHBCLKDIV - DIV.
 
static constexpr uint32 AHBCLKDIV_UNSTAB (uint32 value)
 AHBCLKDIV - UNSTAB.
 
static constexpr uint32 CLKUNLOCK_UNLOCK (uint32 value)
 CLKUNLOCK - UNLOCK.
 
static constexpr uint32 NVM_CTRL_DIS_FLASH_SPEC (uint32 value)
 NVM_CTRL - DIS_FLASH_SPEC.
 
static constexpr uint32 NVM_CTRL_DIS_DATA_SPEC (uint32 value)
 NVM_CTRL - DIS_DATA_SPEC.
 
static constexpr uint32 NVM_CTRL_FLASH_STALL_EN (uint32 value)
 NVM_CTRL - FLASH_STALL_EN.
 
static constexpr uint32 NVM_CTRL_DIS_MBECC_ERR_INST (uint32 value)
 NVM_CTRL - DIS_MBECC_ERR_INST.
 
static constexpr uint32 NVM_CTRL_DIS_MBECC_ERR_DATA (uint32 value)
 NVM_CTRL - DIS_MBECC_ERR_DATA.
 
static constexpr uint32 CPUSTAT_CPU0SLEEPING (uint32 value)
 CPUSTAT - CPU0SLEEPING.
 
static constexpr uint32 CPUSTAT_CPU0LOCKUP (uint32 value)
 CPUSTAT - CPU0LOCKUP.
 
static constexpr uint32 LPCAC_CTRL_DIS_LPCAC (uint32 value)
 LPCAC_CTRL - DIS_LPCAC.
 
static constexpr uint32 LPCAC_CTRL_CLR_LPCAC (uint32 value)
 LPCAC_CTRL - CLR_LPCAC.
 
static constexpr uint32 LPCAC_CTRL_FRC_NO_ALLOC (uint32 value)
 LPCAC_CTRL - FRC_NO_ALLOC.
 
static constexpr uint32 LPCAC_CTRL_DIS_LPCAC_WTBF (uint32 value)
 LPCAC_CTRL - DIS_LPCAC_WTBF.
 
static constexpr uint32 LPCAC_CTRL_LIM_LPCAC_WTBF (uint32 value)
 LPCAC_CTRL - LIM_LPCAC_WTBF.
 
static constexpr uint32 LPCAC_CTRL_LPCAC_XOM (uint32 value)
 LPCAC_CTRL - LPCAC_XOM.
 
static constexpr uint32 LPCAC_CTRL_LPCAC_MEM_REQ (uint32 value)
 LPCAC_CTRL - LPCAC_MEM_REQ.
 
static constexpr uint32 PWM0SUBCTL_CLK0_EN (uint32 value)
 PWM0SUBCTL - CLK0_EN.
 
static constexpr uint32 PWM0SUBCTL_CLK1_EN (uint32 value)
 PWM0SUBCTL - CLK1_EN.
 
static constexpr uint32 PWM0SUBCTL_CLK2_EN (uint32 value)
 PWM0SUBCTL - CLK2_EN.
 
static constexpr uint32 PWM0SUBCTL_CLK3_EN (uint32 value)
 PWM0SUBCTL - CLK3_EN.
 
static constexpr uint32 PWM1SUBCTL_CLK0_EN (uint32 value)
 PWM1SUBCTL - CLK0_EN.
 
static constexpr uint32 PWM1SUBCTL_CLK1_EN (uint32 value)
 PWM1SUBCTL - CLK1_EN.
 
static constexpr uint32 PWM1SUBCTL_CLK2_EN (uint32 value)
 PWM1SUBCTL - CLK2_EN.
 
static constexpr uint32 PWM1SUBCTL_CLK3_EN (uint32 value)
 PWM1SUBCTL - CLK3_EN.
 
static constexpr uint32 CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN (uint32 value)
 CTIMERGLOBALSTARTEN - CTIMER0_CLK_EN.
 
static constexpr uint32 CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN (uint32 value)
 CTIMERGLOBALSTARTEN - CTIMER1_CLK_EN.
 
static constexpr uint32 CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN (uint32 value)
 CTIMERGLOBALSTARTEN - CTIMER2_CLK_EN.
 
static constexpr uint32 CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN (uint32 value)
 CTIMERGLOBALSTARTEN - CTIMER3_CLK_EN.
 
static constexpr uint32 CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN (uint32 value)
 CTIMERGLOBALSTARTEN - CTIMER4_CLK_EN.
 
static constexpr uint32 RAM_CTRL_RAMA_ECC_ENABLE (uint32 value)
 RAM_CTRL - RAMA_ECC_ENABLE.
 
static constexpr uint32 RAM_CTRL_RAMA_CG_OVERRIDE (uint32 value)
 RAM_CTRL - RAMA_CG_OVERRIDE.
 
static constexpr uint32 RAM_CTRL_RAMX_CG_OVERRIDE (uint32 value)
 RAM_CTRL - RAMX_CG_OVERRIDE.
 
static constexpr uint32 RAM_CTRL_RAMB_CG_OVERRIDE (uint32 value)
 RAM_CTRL - RAMB_CG_OVERRIDE.
 
static constexpr uint32 GRAY_CODE_LSB_code_gray_31_0 (uint32 value)
 GRAY_CODE_LSB - code_gray_31_0.
 
static constexpr uint32 GRAY_CODE_MSB_code_gray_41_32 (uint32 value)
 GRAY_CODE_MSB - code_gray_41_32.
 
static constexpr uint32 BINARY_CODE_LSB_code_bin_31_0 (uint32 value)
 BINARY_CODE_LSB - code_bin_31_0.
 
static constexpr uint32 BINARY_CODE_MSB_code_bin_41_32 (uint32 value)
 BINARY_CODE_MSB - code_bin_41_32.
 
static constexpr uint32 ROP_STATE_ROP_STATE (uint32 value)
 ROP_STATE - ROP_STATE.
 
static constexpr uint32 OVP_PAD_STATE_OVP_PAD_STATE (uint32 value)
 OVP_PAD_STATE - OVP_PAD_STATE.
 
static constexpr uint32 PROBE_STATE_PROBE_STATE (uint32 value)
 PROBE_STATE - PROBE_STATE.
 
static constexpr uint32 FT_STATE_A_FT_STATE_A (uint32 value)
 FT_STATE_A - FT_STATE_A.
 
static constexpr uint32 FT_STATE_B_FT_STATE_B (uint32 value)
 FT_STATE_B - FT_STATE_B.
 
static constexpr uint32 SRAM_XEN_RAMX0_XEN (uint32 value)
 SRAM_XEN - RAMX0_XEN.
 
static constexpr uint32 SRAM_XEN_RAMX1_XEN (uint32 value)
 SRAM_XEN - RAMX1_XEN.
 
static constexpr uint32 SRAM_XEN_RAMA0_XEN (uint32 value)
 SRAM_XEN - RAMA0_XEN.
 
static constexpr uint32 SRAM_XEN_RAMA1_XEN (uint32 value)
 SRAM_XEN - RAMA1_XEN.
 
static constexpr uint32 SRAM_XEN_RAMB_XEN (uint32 value)
 SRAM_XEN - RAMB_XEN.
 
static constexpr uint32 SRAM_XEN_LOCK (uint32 value)
 SRAM_XEN - LOCK.
 
static constexpr uint32 SRAM_XEN_DP_RAMX0_XEN (uint32 value)
 SRAM_XEN_DP - RAMX0_XEN.
 
static constexpr uint32 SRAM_XEN_DP_RAMX1_XEN (uint32 value)
 SRAM_XEN_DP - RAMX1_XEN.
 
static constexpr uint32 SRAM_XEN_DP_RAMA0_XEN (uint32 value)
 SRAM_XEN_DP - RAMA0_XEN.
 
static constexpr uint32 SRAM_XEN_DP_RAMA1_XEN (uint32 value)
 SRAM_XEN_DP - RAMA1_XEN.
 
static constexpr uint32 SRAM_XEN_DP_RAMB_XEN (uint32 value)
 SRAM_XEN_DP - RAMB_XEN.
 
static constexpr uint32 ELS_OTP_LC_STATE_OTP_LC_STATE (uint32 value)
 ELS_OTP_LC_STATE - OTP_LC_STATE.
 
static constexpr uint32 ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP (uint32 value)
 ELS_OTP_LC_STATE_DP - OTP_LC_STATE_DP.
 
static constexpr uint32 DEBUG_LOCK_EN_LOCK_ALL (uint32 value)
 DEBUG_LOCK_EN - LOCK_ALL.
 
static constexpr uint32 DEBUG_FEATURES_CPU0_DBGEN (uint32 value)
 DEBUG_FEATURES - CPU0_DBGEN.
 
static constexpr uint32 DEBUG_FEATURES_CPU0_NIDEN (uint32 value)
 DEBUG_FEATURES - CPU0_NIDEN.
 
static constexpr uint32 DEBUG_FEATURES_DP_CPU0_DBGEN (uint32 value)
 DEBUG_FEATURES_DP - CPU0_DBGEN.
 
static constexpr uint32 DEBUG_FEATURES_DP_CPU0_NIDEN (uint32 value)
 DEBUG_FEATURES_DP - CPU0_NIDEN.
 
static constexpr uint32 SWD_ACCESS_CPU0_SEC_CODE (uint32 value)
 SWD_ACCESS_CPU0 - SEC_CODE.
 
static constexpr uint32 DEBUG_AUTH_BEACON_BEACON (uint32 value)
 DEBUG_AUTH_BEACON - BEACON.
 
static constexpr uint32 JTAG_ID_JTAG_ID (uint32 value)
 JTAG_ID - JTAG_ID.
 
static constexpr uint32 DEVICE_TYPE_DEVICE_TYPE (uint32 value)
 DEVICE_TYPE - DEVICE_TYPE.
 
static constexpr uint32 DEVICE_ID0_RAM_SIZE (uint32 value)
 DEVICE_ID0 - RAM_SIZE.
 
static constexpr uint32 DEVICE_ID0_FLASH_SIZE (uint32 value)
 DEVICE_ID0 - FLASH_SIZE.
 
static constexpr uint32 DEVICE_ID0_SECURITY (uint32 value)
 DEVICE_ID0 - SECURITY.
 
static constexpr uint32 DIEID_MINOR_REVISION (uint32 value)
 DIEID - MINOR_REVISION.
 
static constexpr uint32 DIEID_MAJOR_REVISION (uint32 value)
 DIEID - MAJOR_REVISION.
 
static constexpr uint32 DIEID_MCO_NUM_IN_DIE_ID (uint32 value)
 DIEID - MCO_NUM_IN_DIE_ID.
 

函式成員說明文件

◆ AHBCLKDIV_DIV()

static constexpr uint32 chip::syscon::SYSCON::AHBCLKDIV_DIV ( uint32 value)
inlinestaticconstexpr

AHBCLKDIV - DIV.

System Clock Divider - Clock divider value

◆ AHBCLKDIV_UNSTAB()

static constexpr uint32 chip::syscon::SYSCON::AHBCLKDIV_UNSTAB ( uint32 value)
inlinestaticconstexpr

AHBCLKDIV - UNSTAB.

System Clock Divider - Divider status flag

  • [0b1]Clock frequency is not stable
  • [0b0]Divider clock is stable

◆ AHBMATPRIO_CPU0_CBUS()

static constexpr uint32 chip::syscon::SYSCON::AHBMATPRIO_CPU0_CBUS ( uint32 value)
inlinestaticconstexpr

AHBMATPRIO - CPU0_CBUS.

AHB Matrix Priority Control - CPU0 C-AHB bus master priority level

  • [0b00]level 0
  • [0b01]level 1
  • [0b10]level 2
  • [0b11]level 3

◆ AHBMATPRIO_CPU0_SBUS()

static constexpr uint32 chip::syscon::SYSCON::AHBMATPRIO_CPU0_SBUS ( uint32 value)
inlinestaticconstexpr

AHBMATPRIO - CPU0_SBUS.

AHB Matrix Priority Control - CPU0 S-AHB bus master priority level

  • [0b00]level 0
  • [0b01]level 1
  • [0b10]level 2
  • [0b11]level 3

◆ AHBMATPRIO_DMA0()

static constexpr uint32 chip::syscon::SYSCON::AHBMATPRIO_DMA0 ( uint32 value)
inlinestaticconstexpr

AHBMATPRIO - DMA0.

AHB Matrix Priority Control - DMA0 controller bus master priority level

  • [0b00]level 0
  • [0b01]level 1
  • [0b10]level 2
  • [0b11]level 3

◆ AHBMATPRIO_USB_FS_ENET()

static constexpr uint32 chip::syscon::SYSCON::AHBMATPRIO_USB_FS_ENET ( uint32 value)
inlinestaticconstexpr

AHBMATPRIO - USB_FS_ENET.

AHB Matrix Priority Control - USB-FS bus master priority level

  • [0b00]level 0
  • [0b01]level 1
  • [0b10]level 2
  • [0b11]level 3

◆ BINARY_CODE_LSB_code_bin_31_0()

static constexpr uint32 chip::syscon::SYSCON::BINARY_CODE_LSB_code_bin_31_0 ( uint32 value)
inlinestaticconstexpr

BINARY_CODE_LSB - code_bin_31_0.

Gray to Binary Converter Binary Code [31:0] - Binary code [31:0]

◆ BINARY_CODE_MSB_code_bin_41_32()

static constexpr uint32 chip::syscon::SYSCON::BINARY_CODE_MSB_code_bin_41_32 ( uint32 value)
inlinestaticconstexpr

BINARY_CODE_MSB - code_bin_41_32.

Gray to Binary Converter Binary Code [41:32] - Binary code [41:32]

◆ CLKUNLOCK_UNLOCK()

static constexpr uint32 chip::syscon::SYSCON::CLKUNLOCK_UNLOCK ( uint32 value)
inlinestaticconstexpr

CLKUNLOCK - UNLOCK.

Clock Configuration Unlock - Controls clock configuration registers access (for example, MRCC_xxx_CLKDIV, MRCC_xxx_CLKSEL, MRCC_GLB_xxx)

  • [0b1]Freezes all clock configuration registers update.
  • [0b0]Updates are allowed to all clock configuration registers

◆ CPU0NSTCKCAL_NOREF()

static constexpr uint32 chip::syscon::SYSCON::CPU0NSTCKCAL_NOREF ( uint32 value)
inlinestaticconstexpr

CPU0NSTCKCAL - NOREF.

Non-Secure CPU0 System Tick Calibration - Indicates whether the device provides a reference clock to the processor.

  • [0b0]Reference clock is provided
  • [0b1]No reference clock is provided

◆ CPU0NSTCKCAL_SKEW()

static constexpr uint32 chip::syscon::SYSCON::CPU0NSTCKCAL_SKEW ( uint32 value)
inlinestaticconstexpr

CPU0NSTCKCAL - SKEW.

Non-Secure CPU0 System Tick Calibration - Indicates whether the TENMS value is exact.

  • [0b0]TENMS value is exact
  • [0b1]TENMS value is not exact or not given

◆ CPU0NSTCKCAL_TENMS()

static constexpr uint32 chip::syscon::SYSCON::CPU0NSTCKCAL_TENMS ( uint32 value)
inlinestaticconstexpr

CPU0NSTCKCAL - TENMS.

Non-Secure CPU0 System Tick Calibration - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the value reads as zero, the calibration value is not known.

◆ CPUSTAT_CPU0LOCKUP()

static constexpr uint32 chip::syscon::SYSCON::CPUSTAT_CPU0LOCKUP ( uint32 value)
inlinestaticconstexpr

CPUSTAT - CPU0LOCKUP.

CPU Status - CPU0 lockup state

  • [0b1]CPU is in lockup
  • [0b0]CPU is not in lockup

◆ CPUSTAT_CPU0SLEEPING()

static constexpr uint32 chip::syscon::SYSCON::CPUSTAT_CPU0SLEEPING ( uint32 value)
inlinestaticconstexpr

CPUSTAT - CPU0SLEEPING.

CPU Status - CPU0 sleeping state

  • [0b1]CPU is sleeping
  • [0b0]CPU is not sleeping

◆ CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN()

static constexpr uint32 chip::syscon::SYSCON::CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN ( uint32 value)
inlinestaticconstexpr

CTIMERGLOBALSTARTEN - CTIMER0_CLK_EN.

CTIMER Global Start Enable - Enables the CTIMER0 function clock

  • [0b1]Enable
  • [0b0]Disable

◆ CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN()

static constexpr uint32 chip::syscon::SYSCON::CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN ( uint32 value)
inlinestaticconstexpr

CTIMERGLOBALSTARTEN - CTIMER1_CLK_EN.

CTIMER Global Start Enable - Enables the CTIMER1 function clock

  • [0b1]Enable
  • [0b0]Disable

◆ CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN()

static constexpr uint32 chip::syscon::SYSCON::CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN ( uint32 value)
inlinestaticconstexpr

CTIMERGLOBALSTARTEN - CTIMER2_CLK_EN.

CTIMER Global Start Enable - Enables the CTIMER2 function clock

  • [0b1]Enable
  • [0b0]Disable

◆ CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN()

static constexpr uint32 chip::syscon::SYSCON::CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN ( uint32 value)
inlinestaticconstexpr

CTIMERGLOBALSTARTEN - CTIMER3_CLK_EN.

CTIMER Global Start Enable - Enables the CTIMER3 function clock

  • [0b1]Enable
  • [0b0]Disable

◆ CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN()

static constexpr uint32 chip::syscon::SYSCON::CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN ( uint32 value)
inlinestaticconstexpr

CTIMERGLOBALSTARTEN - CTIMER4_CLK_EN.

CTIMER Global Start Enable - Enables the CTIMER4 function clock

  • [0b1]Enable
  • [0b0]Disable

◆ DEBUG_AUTH_BEACON_BEACON()

static constexpr uint32 chip::syscon::SYSCON::DEBUG_AUTH_BEACON_BEACON ( uint32 value)
inlinestaticconstexpr

DEBUG_AUTH_BEACON - BEACON.

Debug Authentication BEACON - Sets by the debug authentication code in ROM to pass the debug beacons (Credential Beacon and Authentication Beacon) to the application code.

◆ DEBUG_FEATURES_CPU0_DBGEN()

static constexpr uint32 chip::syscon::SYSCON::DEBUG_FEATURES_CPU0_DBGEN ( uint32 value)
inlinestaticconstexpr

DEBUG_FEATURES - CPU0_DBGEN.

Cortex Debug Features Control - CPU0 invasive debug control

  • [0b01]Disables debug
  • [0b10]Enables debug

◆ DEBUG_FEATURES_CPU0_NIDEN()

static constexpr uint32 chip::syscon::SYSCON::DEBUG_FEATURES_CPU0_NIDEN ( uint32 value)
inlinestaticconstexpr

DEBUG_FEATURES - CPU0_NIDEN.

Cortex Debug Features Control - CPU0 non-invasive debug control

  • [0b01]Disables debug
  • [0b10]Enables debug

◆ DEBUG_FEATURES_DP_CPU0_DBGEN()

static constexpr uint32 chip::syscon::SYSCON::DEBUG_FEATURES_DP_CPU0_DBGEN ( uint32 value)
inlinestaticconstexpr

DEBUG_FEATURES_DP - CPU0_DBGEN.

Cortex Debug Features Control (Duplicate) - CPU0 invasive debug control

  • [0b01]Disables debug
  • [0b10]Enables debug

◆ DEBUG_FEATURES_DP_CPU0_NIDEN()

static constexpr uint32 chip::syscon::SYSCON::DEBUG_FEATURES_DP_CPU0_NIDEN ( uint32 value)
inlinestaticconstexpr

DEBUG_FEATURES_DP - CPU0_NIDEN.

Cortex Debug Features Control (Duplicate) - CPU0 non-invasive debug control

  • [0b01]Disables debug
  • [0b10]Enables debug

◆ DEBUG_LOCK_EN_LOCK_ALL()

static constexpr uint32 chip::syscon::SYSCON::DEBUG_LOCK_EN_LOCK_ALL ( uint32 value)
inlinestaticconstexpr

DEBUG_LOCK_EN - LOCK_ALL.

Control Write Access to Security - Controls write access to the security registers

  • [0b1010]Enables write access to all registers
  • [0b0000]Any other value than b1010: disables write access to all registers

◆ DEVICE_ID0_FLASH_SIZE()

static constexpr uint32 chip::syscon::SYSCON::DEVICE_ID0_FLASH_SIZE ( uint32 value)
inlinestaticconstexpr

DEVICE_ID0 - FLASH_SIZE.

Device ID - Chip FLASH Size

  • [0b0000]32KB.
  • [0b0001]64KB.
  • [0b0010]128KB.
  • [0b0011]256KB.
  • [0b0100]512KB.
  • [0b0101]768KB.
  • [0b0110]1MB.
  • [0b0111]1.5MB.
  • [0b1000]2MB.

◆ DEVICE_ID0_RAM_SIZE()

static constexpr uint32 chip::syscon::SYSCON::DEVICE_ID0_RAM_SIZE ( uint32 value)
inlinestaticconstexpr

DEVICE_ID0 - RAM_SIZE.

Device ID - Chip RAM Size

  • [0b0000]8KB.
  • [0b0001]16KB.
  • [0b0010]32KB.
  • [0b0011]64KB.
  • [0b0100]96KB.
  • [0b0101]128KB.
  • [0b0110]160KB.
  • [0b0111]192KB.
  • [0b1000]256KB.
  • [0b1001]288KB.
  • [0b1010]352KB.
  • [0b1011]512KB.

◆ DEVICE_ID0_SECURITY()

static constexpr uint32 chip::syscon::SYSCON::DEVICE_ID0_SECURITY ( uint32 value)
inlinestaticconstexpr

DEVICE_ID0 - SECURITY.

Device ID

  • [0b1010]Non secure version.
  • [0b0101]Secure version.

◆ DEVICE_TYPE_DEVICE_TYPE()

static constexpr uint32 chip::syscon::SYSCON::DEVICE_TYPE_DEVICE_TYPE ( uint32 value)
inlinestaticconstexpr

DEVICE_TYPE - DEVICE_TYPE.

Device Type - Indicates DEVICE TYPE.

◆ DIEID_MAJOR_REVISION()

static constexpr uint32 chip::syscon::SYSCON::DIEID_MAJOR_REVISION ( uint32 value)
inlinestaticconstexpr

DIEID - MAJOR_REVISION.

Chip Revision ID and Number - Chip major revision

◆ DIEID_MCO_NUM_IN_DIE_ID()

static constexpr uint32 chip::syscon::SYSCON::DIEID_MCO_NUM_IN_DIE_ID ( uint32 value)
inlinestaticconstexpr

DIEID - MCO_NUM_IN_DIE_ID.

Chip Revision ID and Number - Chip number

◆ DIEID_MINOR_REVISION()

static constexpr uint32 chip::syscon::SYSCON::DIEID_MINOR_REVISION ( uint32 value)
inlinestaticconstexpr

DIEID - MINOR_REVISION.

Chip Revision ID and Number - Chip minor revision

◆ ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP()

static constexpr uint32 chip::syscon::SYSCON::ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP ( uint32 value)
inlinestaticconstexpr

ELS_OTP_LC_STATE_DP - OTP_LC_STATE_DP.

Life Cycle State Register (Duplicate) - OTP life cycle state

◆ ELS_OTP_LC_STATE_OTP_LC_STATE()

static constexpr uint32 chip::syscon::SYSCON::ELS_OTP_LC_STATE_OTP_LC_STATE ( uint32 value)
inlinestaticconstexpr

ELS_OTP_LC_STATE - OTP_LC_STATE.

Life Cycle State Register - OTP life cycle state

◆ FT_STATE_A_FT_STATE_A()

static constexpr uint32 chip::syscon::SYSCON::FT_STATE_A_FT_STATE_A ( uint32 value)
inlinestaticconstexpr

FT_STATE_A - FT_STATE_A.

FT_STATE_A - FT_STATE_A

◆ FT_STATE_B_FT_STATE_B()

static constexpr uint32 chip::syscon::SYSCON::FT_STATE_B_FT_STATE_B ( uint32 value)
inlinestaticconstexpr

FT_STATE_B - FT_STATE_B.

FT_STATE_B - FT_STATE_B

◆ GRAY_CODE_LSB_code_gray_31_0()

static constexpr uint32 chip::syscon::SYSCON::GRAY_CODE_LSB_code_gray_31_0 ( uint32 value)
inlinestaticconstexpr

GRAY_CODE_LSB - code_gray_31_0.

Gray to Binary Converter Gray Code [31:0] - Gray code [31:0]

◆ GRAY_CODE_MSB_code_gray_41_32()

static constexpr uint32 chip::syscon::SYSCON::GRAY_CODE_MSB_code_gray_41_32 ( uint32 value)
inlinestaticconstexpr

GRAY_CODE_MSB - code_gray_41_32.

Gray to Binary Converter Gray Code [41:32] - Gray code [41:32]

◆ JTAG_ID_JTAG_ID()

static constexpr uint32 chip::syscon::SYSCON::JTAG_ID_JTAG_ID ( uint32 value)
inlinestaticconstexpr

JTAG_ID - JTAG_ID.

JTAG Chip ID - Indicates the device ID

◆ LPCAC_CTRL_CLR_LPCAC()

static constexpr uint32 chip::syscon::SYSCON::LPCAC_CTRL_CLR_LPCAC ( uint32 value)
inlinestaticconstexpr

LPCAC_CTRL - CLR_LPCAC.

LPCAC Control - Clears the cache function.

  • [0b0]Unclears the cache
  • [0b1]Clears the cache

◆ LPCAC_CTRL_DIS_LPCAC()

static constexpr uint32 chip::syscon::SYSCON::LPCAC_CTRL_DIS_LPCAC ( uint32 value)
inlinestaticconstexpr

LPCAC_CTRL - DIS_LPCAC.

LPCAC Control - Disables/enables the cache function.

  • [0b0]Enabled
  • [0b1]Disabled

◆ LPCAC_CTRL_DIS_LPCAC_WTBF()

static constexpr uint32 chip::syscon::SYSCON::LPCAC_CTRL_DIS_LPCAC_WTBF ( uint32 value)
inlinestaticconstexpr

LPCAC_CTRL - DIS_LPCAC_WTBF.

LPCAC Control - Disable LPCAC Write Through Buffer.

  • [0b1]Disables write through buffer
  • [0b0]Enables write through buffer

◆ LPCAC_CTRL_FRC_NO_ALLOC()

static constexpr uint32 chip::syscon::SYSCON::LPCAC_CTRL_FRC_NO_ALLOC ( uint32 value)
inlinestaticconstexpr

LPCAC_CTRL - FRC_NO_ALLOC.

LPCAC Control - Forces no allocation.

  • [0b0]Forces allocation
  • [0b1]Forces no allocation

◆ LPCAC_CTRL_LIM_LPCAC_WTBF()

static constexpr uint32 chip::syscon::SYSCON::LPCAC_CTRL_LIM_LPCAC_WTBF ( uint32 value)
inlinestaticconstexpr

LPCAC_CTRL - LIM_LPCAC_WTBF.

LPCAC Control - Limit LPCAC Write Through Buffer.

  • [0b1]Write buffer enabled when transaction is cacheable and bufferable
  • [0b0]Write buffer enabled when transaction is bufferable.

◆ LPCAC_CTRL_LPCAC_MEM_REQ()

static constexpr uint32 chip::syscon::SYSCON::LPCAC_CTRL_LPCAC_MEM_REQ ( uint32 value)
inlinestaticconstexpr

LPCAC_CTRL - LPCAC_MEM_REQ.

LPCAC Control - Request LPCAC memories.

  • [0b1]Configure shared memories RAMX1 as LPCAC memories, write one lock until a system reset.
  • [0b0]Configure shared memories RAMX1 as general memories.

◆ LPCAC_CTRL_LPCAC_XOM()

static constexpr uint32 chip::syscon::SYSCON::LPCAC_CTRL_LPCAC_XOM ( uint32 value)
inlinestaticconstexpr

LPCAC_CTRL - LPCAC_XOM.

LPCAC Control - LPCAC XOM(eXecute-Only-Memory) attribute control

  • [0b1]Enabled.
  • [0b0]Disabled.

◆ NMISRC_IRQCPU0()

static constexpr uint32 chip::syscon::SYSCON::NMISRC_IRQCPU0 ( uint32 value)
inlinestaticconstexpr

NMISRC - IRQCPU0.

NMI Source Select - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for CPU0, if enabled by NMIENCPU0.

◆ NMISRC_NMIENCPU0()

static constexpr uint32 chip::syscon::SYSCON::NMISRC_NMIENCPU0 ( uint32 value)
inlinestaticconstexpr

NMISRC - NMIENCPU0.

NMI Source Select - Enables the Non-Maskable Interrupt (NMI) source selected by IRQCPU0.

  • [0b1][Enable.
  • [0b0]Disable.

◆ NVM_CTRL_DIS_DATA_SPEC()

static constexpr uint32 chip::syscon::SYSCON::NVM_CTRL_DIS_DATA_SPEC ( uint32 value)
inlinestaticconstexpr

NVM_CTRL - DIS_DATA_SPEC.

NVM Control -Flash data speculation control

  • [0b0]Enables data speculation
  • [0b1]Disables data speculation

◆ NVM_CTRL_DIS_FLASH_SPEC()

static constexpr uint32 chip::syscon::SYSCON::NVM_CTRL_DIS_FLASH_SPEC ( uint32 value)
inlinestaticconstexpr

NVM_CTRL - DIS_FLASH_SPEC.

NVM Control - Flash speculation control

  • [0b0]Enables flash speculation
  • [0b1]Disables flash speculation

◆ NVM_CTRL_DIS_MBECC_ERR_DATA()

static constexpr uint32 chip::syscon::SYSCON::NVM_CTRL_DIS_MBECC_ERR_DATA ( uint32 value)
inlinestaticconstexpr

NVM_CTRL - DIS_MBECC_ERR_DATA.

NVM Control

  • [0b0]Enables bus error on multi-bit ECC error for data
  • [0b1]Disables bus error on multi-bit ECC error for data

◆ NVM_CTRL_DIS_MBECC_ERR_INST()

static constexpr uint32 chip::syscon::SYSCON::NVM_CTRL_DIS_MBECC_ERR_INST ( uint32 value)
inlinestaticconstexpr

NVM_CTRL - DIS_MBECC_ERR_INST.

NVM Control

  • [0b0]Enables bus error on multi-bit ECC error for instruction
  • [0b1]Disables bus error on multi-bit ECC error for instruction

◆ NVM_CTRL_FLASH_STALL_EN()

static constexpr uint32 chip::syscon::SYSCON::NVM_CTRL_FLASH_STALL_EN ( uint32 value)
inlinestaticconstexpr

NVM_CTRL - FLASH_STALL_EN.

NVM Control - FLASH stall on busy control

  • [0b0]No stall on FLASH busy
  • [0b1]Stall on FLASH busy

◆ OVP_PAD_STATE_OVP_PAD_STATE()

static constexpr uint32 chip::syscon::SYSCON::OVP_PAD_STATE_OVP_PAD_STATE ( uint32 value)
inlinestaticconstexpr

OVP_PAD_STATE - OVP_PAD_STATE.

OVP_PAD_STATE - OVP_PAD_STATE

◆ PROBE_STATE_PROBE_STATE()

static constexpr uint32 chip::syscon::SYSCON::PROBE_STATE_PROBE_STATE ( uint32 value)
inlinestaticconstexpr

PROBE_STATE - PROBE_STATE.

PROBE_STATE - PROBE_STATE

◆ PWM0SUBCTL_CLK0_EN()

static constexpr uint32 chip::syscon::SYSCON::PWM0SUBCTL_CLK0_EN ( uint32 value)
inlinestaticconstexpr

PWM0SUBCTL - CLK0_EN.

PWM0 Submodule Control - Enables PWM0 SUB Clock0

  • [0b1]Enable
  • [0b0]Disable

◆ PWM0SUBCTL_CLK1_EN()

static constexpr uint32 chip::syscon::SYSCON::PWM0SUBCTL_CLK1_EN ( uint32 value)
inlinestaticconstexpr

PWM0SUBCTL - CLK1_EN.

PWM0 Submodule Control - Enables PWM0 SUB Clock1

  • [0b1]Enable
  • [0b0]Disable

◆ PWM0SUBCTL_CLK2_EN()

static constexpr uint32 chip::syscon::SYSCON::PWM0SUBCTL_CLK2_EN ( uint32 value)
inlinestaticconstexpr

PWM0SUBCTL - CLK2_EN.

PWM0 Submodule Control - Enables PWM0 SUB Clock2

  • [0b1]Enable
  • [0b0]Disable

◆ PWM0SUBCTL_CLK3_EN()

static constexpr uint32 chip::syscon::SYSCON::PWM0SUBCTL_CLK3_EN ( uint32 value)
inlinestaticconstexpr

PWM0SUBCTL - CLK3_EN.

PWM0 Submodule Control - Enables PWM0 SUB Clock3

  • [0b1]Enable
  • [0b0]Disable

◆ PWM1SUBCTL_CLK0_EN()

static constexpr uint32 chip::syscon::SYSCON::PWM1SUBCTL_CLK0_EN ( uint32 value)
inlinestaticconstexpr

PWM1SUBCTL - CLK0_EN.

PWM1 Submodule Control - Enables PWM1 SUB Clock0

  • [0b1]Enable
  • [0b0]Disable

◆ PWM1SUBCTL_CLK1_EN()

static constexpr uint32 chip::syscon::SYSCON::PWM1SUBCTL_CLK1_EN ( uint32 value)
inlinestaticconstexpr

PWM1SUBCTL - CLK1_EN.

PWM1 Submodule Control - Enables PWM1 SUB Clock1

  • [0b1]Enable
  • [0b0]Disable

◆ PWM1SUBCTL_CLK2_EN()

static constexpr uint32 chip::syscon::SYSCON::PWM1SUBCTL_CLK2_EN ( uint32 value)
inlinestaticconstexpr

PWM1SUBCTL - CLK2_EN.

PWM1 Submodule Control - Enables PWM1 SUB Clock2

  • [0b1]Enable
  • [0b0]Disable

◆ PWM1SUBCTL_CLK3_EN()

static constexpr uint32 chip::syscon::SYSCON::PWM1SUBCTL_CLK3_EN ( uint32 value)
inlinestaticconstexpr

PWM1SUBCTL - CLK3_EN.

PWM1 Submodule Control - Enables PWM1 SUB Clock3

  • [0b1]Enable
  • [0b0]Disable

◆ RAM_CTRL_RAMA_CG_OVERRIDE()

static constexpr uint32 chip::syscon::SYSCON::RAM_CTRL_RAMA_CG_OVERRIDE ( uint32 value)
inlinestaticconstexpr

RAM_CTRL - RAMA_CG_OVERRIDE.

RAM Control - RAMA bank clock gating control, only avaiable when RAMA_ECC_ENABLE = 0.

  • [0b1]Auto clock gating feature is disabled
  • [0b0]Memory bank clock is gated automatically if no access more than 16 clock cycles

◆ RAM_CTRL_RAMA_ECC_ENABLE()

static constexpr uint32 chip::syscon::SYSCON::RAM_CTRL_RAMA_ECC_ENABLE ( uint32 value)
inlinestaticconstexpr

RAM_CTRL - RAMA_ECC_ENABLE.

RAM Control - RAMA0 ECC enable

  • [0b1]ECC is enabled
  • [0b0]ECC is disabled

◆ RAM_CTRL_RAMB_CG_OVERRIDE()

static constexpr uint32 chip::syscon::SYSCON::RAM_CTRL_RAMB_CG_OVERRIDE ( uint32 value)
inlinestaticconstexpr

RAM_CTRL - RAMB_CG_OVERRIDE.

RAM Control - RAMB bank clock gating control

  • [0b1]Auto clock gating feature is disabled
  • [0b0]Memory bank clock is gated automatically if no access more than 16 clock cycles

◆ RAM_CTRL_RAMX_CG_OVERRIDE()

static constexpr uint32 chip::syscon::SYSCON::RAM_CTRL_RAMX_CG_OVERRIDE ( uint32 value)
inlinestaticconstexpr

RAM_CTRL - RAMX_CG_OVERRIDE.

RAM Control - RAMX bank clock gating control

  • [0b1]Auto clock gating feature is disabled
  • [0b0]Memory bank clock is gated automatically if no access more than 16 clock cycles

◆ REMAP_CPU0_SBUS()

static constexpr uint32 chip::syscon::SYSCON::REMAP_CPU0_SBUS ( uint32 value)
inlinestaticconstexpr

REMAP - CPU0_SBUS.

AHB Matrix Remap Control - RAMX0 address remap for CPU System bus

  • [0b00]RAMX0: 0x04000000 - 0x04001fff
  • [0b01]RAMX0: 0x2001e000 - 0x2001ffff(for 128KB RAM chip) / 0x20016000 - 0x20017fff(for 96KB RAM chip) / 0x2000e000 - 0x2000ffff(for 64KB RAM chip)

◆ REMAP_DMA0()

static constexpr uint32 chip::syscon::SYSCON::REMAP_DMA0 ( uint32 value)
inlinestaticconstexpr

REMAP - DMA0.

AHB Matrix Remap Control - RAMX0 address remap for DMA0

  • [0b00]RAMX0: 0x04000000 - 0x04001fff
  • [0b01]RAMX0: same alias space as CPU0_SBUS

◆ REMAP_LOCK()

static constexpr uint32 chip::syscon::SYSCON::REMAP_LOCK ( uint32 value)
inlinestaticconstexpr

REMAP - LOCK.

AHB Matrix Remap Control - This 1-bit field provides a mechanism to limit writes to the this register to protect its contents. Once set, this bit remains asserted until a system reset.

  • [0b0]This register is not locked and can be altered.
  • [0b1]This register is locked and cannot be altered until a system reset.

◆ REMAP_USB0()

static constexpr uint32 chip::syscon::SYSCON::REMAP_USB0 ( uint32 value)
inlinestaticconstexpr

REMAP - USB0.

AHB Matrix Remap Control - RAMX0 address remap for USB0

  • [0b00]RAMX0: 0x04000000 - 0x04001fff
  • [0b01]RAMX0: same alias space as CPU0_SBUS

◆ ROP_STATE_ROP_STATE()

static constexpr uint32 chip::syscon::SYSCON::ROP_STATE_ROP_STATE ( uint32 value)
inlinestaticconstexpr

ROP_STATE - ROP_STATE.

ROP State Register - ROP state

◆ SLOWCLKDIV_HALT()

static constexpr uint32 chip::syscon::SYSCON::SLOWCLKDIV_HALT ( uint32 value)
inlinestaticconstexpr

SLOWCLKDIV - HALT.

SLOW_CLK Clock Divider - Halts the divider counter

  • [0b1]Divider clock is stopped
  • [0b0]Divider clock is running

◆ SLOWCLKDIV_RESET()

static constexpr uint32 chip::syscon::SYSCON::SLOWCLKDIV_RESET ( uint32 value)
inlinestaticconstexpr

SLOWCLKDIV - RESET.

SLOW_CLK Clock Divider - Resets the divider counter

  • [0b1]Divider is reset
  • [0b0]Divider is not reset

◆ SLOWCLKDIV_UNSTAB()

static constexpr uint32 chip::syscon::SYSCON::SLOWCLKDIV_UNSTAB ( uint32 value)
inlinestaticconstexpr

SLOWCLKDIV - UNSTAB.

SLOW_CLK Clock Divider - Divider status flag

  • [0b1]Clock frequency is not stable
  • [0b0]Divider clock is stable

◆ SRAM_XEN_DP_RAMA0_XEN()

static constexpr uint32 chip::syscon::SYSCON::SRAM_XEN_DP_RAMA0_XEN ( uint32 value)
inlinestaticconstexpr

SRAM_XEN_DP - RAMA0_XEN.

RAM XEN Control (Duplicate) - Refer to SRAM_XEN for more details.

◆ SRAM_XEN_DP_RAMA1_XEN()

static constexpr uint32 chip::syscon::SYSCON::SRAM_XEN_DP_RAMA1_XEN ( uint32 value)
inlinestaticconstexpr

SRAM_XEN_DP - RAMA1_XEN.

RAM XEN Control (Duplicate) - Refer to SRAM_XEN for more details.

◆ SRAM_XEN_DP_RAMB_XEN()

static constexpr uint32 chip::syscon::SYSCON::SRAM_XEN_DP_RAMB_XEN ( uint32 value)
inlinestaticconstexpr

SRAM_XEN_DP - RAMB_XEN.

RAM XEN Control (Duplicate) - Refer to SRAM_XEN for more details.

◆ SRAM_XEN_DP_RAMX0_XEN()

static constexpr uint32 chip::syscon::SYSCON::SRAM_XEN_DP_RAMX0_XEN ( uint32 value)
inlinestaticconstexpr

SRAM_XEN_DP - RAMX0_XEN.

RAM XEN Control (Duplicate) - Refer to SRAM_XEN for more details.

◆ SRAM_XEN_DP_RAMX1_XEN()

static constexpr uint32 chip::syscon::SYSCON::SRAM_XEN_DP_RAMX1_XEN ( uint32 value)
inlinestaticconstexpr

SRAM_XEN_DP - RAMX1_XEN.

RAM XEN Control (Duplicate) - Refer to SRAM_XEN for more details.

◆ SRAM_XEN_LOCK()

static constexpr uint32 chip::syscon::SYSCON::SRAM_XEN_LOCK ( uint32 value)
inlinestaticconstexpr

SRAM_XEN - LOCK.

RAM XEN Control - This 1-bit field provides a mechanism to limit writes to the this register (and SRAM_XEN_DP) to protect its contents. Once set, this bit remains asserted until a system reset.

  • [0b0]This register is not locked and can be altered.
  • [0b1]This register is locked and cannot be altered.

◆ SRAM_XEN_RAMA0_XEN()

static constexpr uint32 chip::syscon::SYSCON::SRAM_XEN_RAMA0_XEN ( uint32 value)
inlinestaticconstexpr

SRAM_XEN - RAMA0_XEN.

RAM XEN Control - RAMA0 Execute permission control.

  • [0b1]Execute permission is enabled, R/W/X are enabled.
  • [0b0]Execute permission is disabled, R/W are enabled.

◆ SRAM_XEN_RAMA1_XEN()

static constexpr uint32 chip::syscon::SYSCON::SRAM_XEN_RAMA1_XEN ( uint32 value)
inlinestaticconstexpr

SRAM_XEN - RAMA1_XEN.

RAM XEN Control - RAMAx (excepts RAMA0) Execute permission control.

  • [0b1]Execute permission is enabled, R/W/X are enabled.
  • [0b0]Execute permission is disabled, R/W are enabled.

◆ SRAM_XEN_RAMB_XEN()

static constexpr uint32 chip::syscon::SYSCON::SRAM_XEN_RAMB_XEN ( uint32 value)
inlinestaticconstexpr

SRAM_XEN - RAMB_XEN.

RAM XEN Control - RAMBx Execute permission control.

  • [0b1]Execute permission is enabled, R/W/X are enabled.
  • [0b0]Execute permission is disabled, R/W are enabled.

◆ SRAM_XEN_RAMX0_XEN()

static constexpr uint32 chip::syscon::SYSCON::SRAM_XEN_RAMX0_XEN ( uint32 value)
inlinestaticconstexpr

SRAM_XEN - RAMX0_XEN.

RAM XEN Control - RAMX0 Execute permission control.

  • [0b1]Execute permission is enabled, R/W/X are enabled.
  • [0b0]Execute permission is disabled, R/W are enabled.

◆ SRAM_XEN_RAMX1_XEN()

static constexpr uint32 chip::syscon::SYSCON::SRAM_XEN_RAMX1_XEN ( uint32 value)
inlinestaticconstexpr

SRAM_XEN - RAMX1_XEN.

RAM XEN Control - RAMX1 Execute permission control.

  • [0b1]Execute permission is enabled, R/W/X are enabled.
  • [0b0]Execute permission is disabled, R/W are enabled.

◆ SWD_ACCESS_CPU0_SEC_CODE()

static constexpr uint32 chip::syscon::SYSCON::SWD_ACCESS_CPU0_SEC_CODE ( uint32 value)
inlinestaticconstexpr

SWD_ACCESS_CPU0 - SEC_CODE.

CPU0 Software Debug Access - CPU0 SWD-AP: 0x12345678

  • [0b00010010001101000101011001111000]Value to write to enable CPU0 SWD access. Reading back register is read as 0xA.
  • [0b00000000000000000000000000000000]CPU0 DAP is not allowed. Reading back register is read as 0x5.
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