SYSCON.h

 
#ifndef CHIP_E90AC029_576D_4863_AF17_144EE618D9F8
#define CHIP_E90AC029_576D_4863_AF17_144EE618D9F8
 
/* ***************************************************************************************
 * Include
 */
 
//----------------------------------------------------------------------------------------
#include "mframe.h"
 
//----------------------------------------------------------------------------------------
#include "./Mask.h"
#include "./Register.h"
#include "./Shift.h"
 
/* ***************************************************************************************
 * Namespace
 */
namespace chip::syscon {
  class SYSCON;
  extern Register& SYSCON0;
}  // namespace chip::syscon
 
/* ***************************************************************************************
 * Class/Interface/Struct/Enum
 */
class chip::syscon::SYSCON final : public mframe::lang::Object {
  /* *************************************************************************************
   * Variable
   */
 
  /* *************************************************************************************
   * Abstract Method
   */
 
  /* *************************************************************************************
   * Construct Method
   */
 private:
  SYSCON(void);
 
 public:
  virtual ~SYSCON(void) override;
 
  /* *************************************************************************************
   * Operator Method
   */
 
  /* *************************************************************************************
   * Public Method <Override>
   */
 
  /* *************************************************************************************
   * Public Method
   */
 
  /* *************************************************************************************
   * Protected Method
   */
 
  /* *************************************************************************************
   * Private Method
   */
 
  /* *************************************************************************************
   * Static Variable
   */
 
  /* *************************************************************************************
   * Static Method
   */
 public:
  static inline constexpr uint32 REMAP_CPU0_SBUS(uint32 value) {
    return ((value << +chip::syscon::Shift::REMAP_CPU0_SBUS) &
            +chip::syscon::Mask::REMAP_CPU0_SBUS);
  }
 
  static inline constexpr uint32 REMAP_DMA0(uint32 value) {
    return ((value << +chip::syscon::Shift::REMAP_DMA0) &
            +chip::syscon::Mask::REMAP_DMA0);
  }
 
  static inline constexpr uint32 REMAP_USB0(uint32 value) {
    return ((value << +chip::syscon::Shift::REMAP_USB0) &
            +chip::syscon::Mask::REMAP_USB0);
  }
 
  static inline constexpr uint32 REMAP_LOCK(uint32 value) {
    return ((value << +chip::syscon::Shift::REMAP_LOCK) &
            +chip::syscon::Mask::REMAP_LOCK);
  }
 
  static inline constexpr uint32 AHBMATPRIO_CPU0_CBUS(uint32 value) {
    return ((value << +chip::syscon::Shift::AHBMATPRIO_CPU0_CBUS) &
            +chip::syscon::Mask::AHBMATPRIO_CPU0_CBUS);
  }
 
  static inline constexpr uint32 AHBMATPRIO_CPU0_SBUS(uint32 value) {
    return ((value << +chip::syscon::Shift::AHBMATPRIO_CPU0_SBUS) &
            +chip::syscon::Mask::AHBMATPRIO_CPU0_SBUS);
  }
 
  static inline constexpr uint32 AHBMATPRIO_DMA0(uint32 value) {
    return ((value << +chip::syscon::Shift::AHBMATPRIO_DMA0) &
            +chip::syscon::Mask::AHBMATPRIO_DMA0);
  }
 
  static inline constexpr uint32 AHBMATPRIO_USB_FS_ENET(uint32 value) {
    return ((value << +chip::syscon::Shift::AHBMATPRIO_USB_FS_ENET) &
            +chip::syscon::Mask::AHBMATPRIO_USB_FS_ENET);
  }
 
  static inline constexpr uint32 CPU0NSTCKCAL_TENMS(uint32 value) {
    return ((value << +chip::syscon::Shift::CPU0NSTCKCAL_TENMS) &
            +chip::syscon::Mask::CPU0NSTCKCAL_TENMS);
  }
 
  static inline constexpr uint32 CPU0NSTCKCAL_SKEW(uint32 value) {
    return ((value << +chip::syscon::Shift::CPU0NSTCKCAL_SKEW) &
            +chip::syscon::Mask::CPU0NSTCKCAL_SKEW);
  }
 
  static inline constexpr uint32 CPU0NSTCKCAL_NOREF(uint32 value) {
    return ((value << +chip::syscon::Shift::CPU0NSTCKCAL_NOREF) &
            +chip::syscon::Mask::CPU0NSTCKCAL_NOREF);
  }
 
  static inline constexpr uint32 NMISRC_IRQCPU0(uint32 value) {
    return ((value << +chip::syscon::Shift::NMISRC_IRQCPU0) &
            +chip::syscon::Mask::NMISRC_IRQCPU0);
  }
 
  static inline constexpr uint32 NMISRC_NMIENCPU0(uint32 value) {
    return ((value << +chip::syscon::Shift::NMISRC_NMIENCPU0) &
            +chip::syscon::Mask::NMISRC_NMIENCPU0);
  }
 
  static inline constexpr uint32 SLOWCLKDIV_RESET(uint32 value) {
    return ((value << +chip::syscon::Shift::SLOWCLKDIV_RESET) &
            +chip::syscon::Mask::SLOWCLKDIV_RESET);
  }
 
  static inline constexpr uint32 SLOWCLKDIV_HALT(uint32 value) {
    return ((value << +chip::syscon::Shift::SLOWCLKDIV_HALT) &
            +chip::syscon::Mask::SLOWCLKDIV_HALT);
  }
 
  static inline constexpr uint32 SLOWCLKDIV_UNSTAB(uint32 value) {
    return ((value << +chip::syscon::Shift::SLOWCLKDIV_UNSTAB) &
            +chip::syscon::Mask::SLOWCLKDIV_UNSTAB);
  }
 
  static inline constexpr uint32 AHBCLKDIV_DIV(uint32 value) {
    return ((value << +chip::syscon::Shift::AHBCLKDIV_DIV) &
            +chip::syscon::Mask::AHBCLKDIV_DIV);
  }
 
  static inline constexpr uint32 AHBCLKDIV_UNSTAB(uint32 value) {
    return ((value << +chip::syscon::Shift::AHBCLKDIV_UNSTAB) &
            +chip::syscon::Mask::AHBCLKDIV_UNSTAB);
  }
 
  static inline constexpr uint32 CLKUNLOCK_UNLOCK(uint32 value) {
    return ((value << +chip::syscon::Shift::CLKUNLOCK_UNLOCK) &
            +chip::syscon::Mask::CLKUNLOCK_UNLOCK);
  }
 
  static inline constexpr uint32 NVM_CTRL_DIS_FLASH_SPEC(uint32 value) {
    return ((value << +chip::syscon::Shift::NVM_CTRL_DIS_FLASH_SPEC) &
            +chip::syscon::Mask::NVM_CTRL_DIS_FLASH_SPEC);
  }
 
  static inline constexpr uint32 NVM_CTRL_DIS_DATA_SPEC(uint32 value) {
    return ((value << +chip::syscon::Shift::NVM_CTRL_DIS_DATA_SPEC) &
            +chip::syscon::Mask::NVM_CTRL_DIS_DATA_SPEC);
  }
 
  static inline constexpr uint32 NVM_CTRL_FLASH_STALL_EN(uint32 value) {
    return ((value << +chip::syscon::Shift::NVM_CTRL_FLASH_STALL_EN) &
            +chip::syscon::Mask::NVM_CTRL_FLASH_STALL_EN);
  }
 
  static inline constexpr uint32 NVM_CTRL_DIS_MBECC_ERR_INST(uint32 value) {
    return ((value << +chip::syscon::Shift::NVM_CTRL_DIS_MBECC_ERR_INST) &
            +chip::syscon::Mask::NVM_CTRL_DIS_MBECC_ERR_INST);
  }
 
  static inline constexpr uint32 NVM_CTRL_DIS_MBECC_ERR_DATA(uint32 value) {
    return ((value << +chip::syscon::Shift::NVM_CTRL_DIS_MBECC_ERR_DATA) &
            +chip::syscon::Mask::NVM_CTRL_DIS_MBECC_ERR_DATA);
  }
 
  static inline constexpr uint32 CPUSTAT_CPU0SLEEPING(uint32 value) {
    return ((value << +chip::syscon::Shift::CPUSTAT_CPU0SLEEPING) &
            +chip::syscon::Mask::CPUSTAT_CPU0SLEEPING);
  }
 
  static inline constexpr uint32 CPUSTAT_CPU0LOCKUP(uint32 value) {
    return ((value << +chip::syscon::Shift::CPUSTAT_CPU0LOCKUP) &
            +chip::syscon::Mask::CPUSTAT_CPU0LOCKUP);
  }
 
  static inline constexpr uint32 LPCAC_CTRL_DIS_LPCAC(uint32 value) {
    return ((value << +chip::syscon::Shift::LPCAC_CTRL_DIS_LPCAC) &
            +chip::syscon::Mask::LPCAC_CTRL_DIS_LPCAC);
  }
 
  static inline constexpr uint32 LPCAC_CTRL_CLR_LPCAC(uint32 value) {
    return ((value << +chip::syscon::Shift::LPCAC_CTRL_CLR_LPCAC) &
            +chip::syscon::Mask::LPCAC_CTRL_CLR_LPCAC);
  }
 
  static inline constexpr uint32 LPCAC_CTRL_FRC_NO_ALLOC(uint32 value) {
    return ((value << +chip::syscon::Shift::LPCAC_CTRL_FRC_NO_ALLOC) &
            +chip::syscon::Mask::LPCAC_CTRL_FRC_NO_ALLOC);
  }
 
  static inline constexpr uint32 LPCAC_CTRL_DIS_LPCAC_WTBF(uint32 value) {
    return ((value << +chip::syscon::Shift::LPCAC_CTRL_DIS_LPCAC_WTBF) &
            +chip::syscon::Mask::LPCAC_CTRL_DIS_LPCAC_WTBF);
  }
 
  static inline constexpr uint32 LPCAC_CTRL_LIM_LPCAC_WTBF(uint32 value) {
    return ((value << +chip::syscon::Shift::LPCAC_CTRL_LIM_LPCAC_WTBF) &
            +chip::syscon::Mask::LPCAC_CTRL_LIM_LPCAC_WTBF);
  }
 
  static inline constexpr uint32 LPCAC_CTRL_LPCAC_XOM(uint32 value) {
    return ((value << +chip::syscon::Shift::LPCAC_CTRL_LPCAC_XOM) &
            +chip::syscon::Mask::LPCAC_CTRL_LPCAC_XOM);
  }
 
  static inline constexpr uint32 LPCAC_CTRL_LPCAC_MEM_REQ(uint32 value) {
    return ((value << +chip::syscon::Shift::LPCAC_CTRL_LPCAC_MEM_REQ) &
            +chip::syscon::Mask::LPCAC_CTRL_LPCAC_MEM_REQ);
  }
 
  static inline constexpr uint32 PWM0SUBCTL_CLK0_EN(uint32 value) {
    return ((value << +chip::syscon::Shift::PWM0SUBCTL_CLK0_EN) &
            +chip::syscon::Mask::PWM0SUBCTL_CLK0_EN);
  }
 
  static inline constexpr uint32 PWM0SUBCTL_CLK1_EN(uint32 value) {
    return ((value << +chip::syscon::Shift::PWM0SUBCTL_CLK1_EN) &
            +chip::syscon::Mask::PWM0SUBCTL_CLK1_EN);
  }
 
  static inline constexpr uint32 PWM0SUBCTL_CLK2_EN(uint32 value) {
    return ((value << +chip::syscon::Shift::PWM0SUBCTL_CLK2_EN) &
            +chip::syscon::Mask::PWM0SUBCTL_CLK2_EN);
  }
 
  static inline constexpr uint32 PWM0SUBCTL_CLK3_EN(uint32 value) {
    return ((value << +chip::syscon::Shift::PWM0SUBCTL_CLK3_EN) &
            +chip::syscon::Mask::PWM0SUBCTL_CLK3_EN);
  }
 
  static inline constexpr uint32 PWM1SUBCTL_CLK0_EN(uint32 value) {
    return ((value << +chip::syscon::Shift::PWM1SUBCTL_CLK0_EN) &
            +chip::syscon::Mask::PWM1SUBCTL_CLK0_EN);
  }
 
  static inline constexpr uint32 PWM1SUBCTL_CLK1_EN(uint32 value) {
    return ((value << +chip::syscon::Shift::PWM1SUBCTL_CLK1_EN) &
            +chip::syscon::Mask::PWM1SUBCTL_CLK1_EN);
  }
 
  static inline constexpr uint32 PWM1SUBCTL_CLK2_EN(uint32 value) {
    return ((value << +chip::syscon::Shift::PWM1SUBCTL_CLK2_EN) &
            +chip::syscon::Mask::PWM1SUBCTL_CLK2_EN);
  }
 
  static inline constexpr uint32 PWM1SUBCTL_CLK3_EN(uint32 value) {
    return ((value << +chip::syscon::Shift::PWM1SUBCTL_CLK3_EN) &
            +chip::syscon::Mask::PWM1SUBCTL_CLK3_EN);
  }
 
  static inline constexpr uint32 CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN(uint32 value) {
    return ((value << +chip::syscon::Shift::CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN) &
            +chip::syscon::Mask::CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN);
  }
 
  static inline constexpr uint32 CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN(uint32 value) {
    return ((value << +chip::syscon::Shift::CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN) &
            +chip::syscon::Mask::CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN);
  }
 
  static inline constexpr uint32 CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN(uint32 value) {
    return ((value << +chip::syscon::Shift::CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN) &
            +chip::syscon::Mask::CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN);
  }
 
  static inline constexpr uint32 CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN(uint32 value) {
    return ((value << +chip::syscon::Shift::CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN) &
            +chip::syscon::Mask::CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN);
  }
 
  static inline constexpr uint32 CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN(uint32 value) {
    return ((value << +chip::syscon::Shift::CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN) &
            +chip::syscon::Mask::CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN);
  }
 
  static inline constexpr uint32 RAM_CTRL_RAMA_ECC_ENABLE(uint32 value) {
    return ((value << +chip::syscon::Shift::RAM_CTRL_RAMA_ECC_ENABLE) &
            +chip::syscon::Mask::RAM_CTRL_RAMA_ECC_ENABLE);
  }
 
  static inline constexpr uint32 RAM_CTRL_RAMA_CG_OVERRIDE(uint32 value) {
    return ((value << +chip::syscon::Shift::RAM_CTRL_RAMA_CG_OVERRIDE) &
            +chip::syscon::Mask::RAM_CTRL_RAMA_CG_OVERRIDE);
  }
 
  static inline constexpr uint32 RAM_CTRL_RAMX_CG_OVERRIDE(uint32 value) {
    return ((value << +chip::syscon::Shift::RAM_CTRL_RAMX_CG_OVERRIDE) &
            +chip::syscon::Mask::RAM_CTRL_RAMX_CG_OVERRIDE);
  }
 
  static inline constexpr uint32 RAM_CTRL_RAMB_CG_OVERRIDE(uint32 value) {
    return ((value << +chip::syscon::Shift::RAM_CTRL_RAMB_CG_OVERRIDE) &
            +chip::syscon::Mask::RAM_CTRL_RAMB_CG_OVERRIDE);
  }
 
  static inline constexpr uint32 GRAY_CODE_LSB_code_gray_31_0(uint32 value) {
    return ((value << +chip::syscon::Shift::GRAY_CODE_LSB_code_gray_31_0) &
            +chip::syscon::Mask::GRAY_CODE_LSB_code_gray_31_0);
  }
 
  static inline constexpr uint32 GRAY_CODE_MSB_code_gray_41_32(uint32 value) {
    return ((value << +chip::syscon::Shift::GRAY_CODE_MSB_code_gray_41_32) &
            +chip::syscon::Mask::GRAY_CODE_MSB_code_gray_41_32);
  }
 
  static inline constexpr uint32 BINARY_CODE_LSB_code_bin_31_0(uint32 value) {
    return ((value << +chip::syscon::Shift::BINARY_CODE_LSB_code_bin_31_0) &
            +chip::syscon::Mask::BINARY_CODE_LSB_code_bin_31_0);
  }
 
  static inline constexpr uint32 BINARY_CODE_MSB_code_bin_41_32(uint32 value) {
    return ((value << +chip::syscon::Shift::BINARY_CODE_MSB_code_bin_41_32) &
            +chip::syscon::Mask::BINARY_CODE_MSB_code_bin_41_32);
  }
 
  static inline constexpr uint32 ROP_STATE_ROP_STATE(uint32 value) {
    return ((value << +chip::syscon::Shift::ROP_STATE_ROP_STATE) &
            +chip::syscon::Mask::ROP_STATE_ROP_STATE);
  }
 
  static inline constexpr uint32 OVP_PAD_STATE_OVP_PAD_STATE(uint32 value) {
    return ((value << +chip::syscon::Shift::OVP_PAD_STATE_OVP_PAD_STATE) &
            +chip::syscon::Mask::OVP_PAD_STATE_OVP_PAD_STATE);
  }
 
  static inline constexpr uint32 PROBE_STATE_PROBE_STATE(uint32 value) {
    return ((value << +chip::syscon::Shift::PROBE_STATE_PROBE_STATE) &
            +chip::syscon::Mask::PROBE_STATE_PROBE_STATE);
  }
 
  static inline constexpr uint32 FT_STATE_A_FT_STATE_A(uint32 value) {
    return ((value << +chip::syscon::Shift::FT_STATE_A_FT_STATE_A) &
            +chip::syscon::Mask::FT_STATE_A_FT_STATE_A);
  }
 
  static inline constexpr uint32 FT_STATE_B_FT_STATE_B(uint32 value) {
    return ((value << +chip::syscon::Shift::FT_STATE_B_FT_STATE_B) &
            +chip::syscon::Mask::FT_STATE_B_FT_STATE_B);
  }
 
  static inline constexpr uint32 SRAM_XEN_RAMX0_XEN(uint32 value) {
    return ((value << +chip::syscon::Shift::SRAM_XEN_RAMX0_XEN) &
            +chip::syscon::Mask::SRAM_XEN_RAMX0_XEN);
  }
 
  static inline constexpr uint32 SRAM_XEN_RAMX1_XEN(uint32 value) {
    return ((value << +chip::syscon::Shift::SRAM_XEN_RAMX1_XEN) &
            +chip::syscon::Mask::SRAM_XEN_RAMX1_XEN);
  }
 
  static inline constexpr uint32 SRAM_XEN_RAMA0_XEN(uint32 value) {
    return ((value << +chip::syscon::Shift::SRAM_XEN_RAMA0_XEN) &
            +chip::syscon::Mask::SRAM_XEN_RAMA0_XEN);
  }
 
  static inline constexpr uint32 SRAM_XEN_RAMA1_XEN(uint32 value) {
    return ((value << +chip::syscon::Shift::SRAM_XEN_RAMA1_XEN) &
            +chip::syscon::Mask::SRAM_XEN_RAMA1_XEN);
  }
 
  static inline constexpr uint32 SRAM_XEN_RAMB_XEN(uint32 value) {
    return ((value << +chip::syscon::Shift::SRAM_XEN_RAMB_XEN) &
            +chip::syscon::Mask::SRAM_XEN_RAMB_XEN);
  }
 
  static inline constexpr uint32 SRAM_XEN_LOCK(uint32 value) {
    return ((value << +chip::syscon::Shift::SRAM_XEN_LOCK) &
            +chip::syscon::Mask::SRAM_XEN_LOCK);
  }
 
  static inline constexpr uint32 SRAM_XEN_DP_RAMX0_XEN(uint32 value) {
    return ((value << +chip::syscon::Shift::SRAM_XEN_DP_RAMX0_XEN) &
            +chip::syscon::Mask::SRAM_XEN_DP_RAMX0_XEN);
  }
 
  static inline constexpr uint32 SRAM_XEN_DP_RAMX1_XEN(uint32 value) {
    return ((value << +chip::syscon::Shift::SRAM_XEN_DP_RAMX1_XEN) &
            +chip::syscon::Mask::SRAM_XEN_DP_RAMX1_XEN);
  }
 
  static inline constexpr uint32 SRAM_XEN_DP_RAMA0_XEN(uint32 value) {
    return ((value << +chip::syscon::Shift::SRAM_XEN_DP_RAMA0_XEN) &
            +chip::syscon::Mask::SRAM_XEN_DP_RAMA0_XEN);
  }
 
  static inline constexpr uint32 SRAM_XEN_DP_RAMA1_XEN(uint32 value) {
    return ((value << +chip::syscon::Shift::SRAM_XEN_DP_RAMA1_XEN) &
            +chip::syscon::Mask::SRAM_XEN_DP_RAMA1_XEN);
  }
 
  static inline constexpr uint32 SRAM_XEN_DP_RAMB_XEN(uint32 value) {
    return ((value << +chip::syscon::Shift::SRAM_XEN_DP_RAMB_XEN) &
            +chip::syscon::Mask::SRAM_XEN_DP_RAMB_XEN);
  }
 
  static inline constexpr uint32 ELS_OTP_LC_STATE_OTP_LC_STATE(uint32 value) {
    return ((value << +chip::syscon::Shift::ELS_OTP_LC_STATE_OTP_LC_STATE) &
            +chip::syscon::Mask::ELS_OTP_LC_STATE_OTP_LC_STATE);
  }
 
  static inline constexpr uint32 ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP(uint32 value) {
    return ((value << +chip::syscon::Shift::ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP) &
            +chip::syscon::Mask::ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP);
  }
 
  static inline constexpr uint32 DEBUG_LOCK_EN_LOCK_ALL(uint32 value) {
    return ((value << +chip::syscon::Shift::DEBUG_LOCK_EN_LOCK_ALL) &
            +chip::syscon::Mask::DEBUG_LOCK_EN_LOCK_ALL);
  }
 
  static inline constexpr uint32 DEBUG_FEATURES_CPU0_DBGEN(uint32 value) {
    return ((value << +chip::syscon::Shift::DEBUG_FEATURES_CPU0_DBGEN) &
            +chip::syscon::Mask::DEBUG_FEATURES_CPU0_DBGEN);
  }
 
  static inline constexpr uint32 DEBUG_FEATURES_CPU0_NIDEN(uint32 value) {
    return ((value << +chip::syscon::Shift::DEBUG_FEATURES_CPU0_NIDEN) &
            +chip::syscon::Mask::DEBUG_FEATURES_CPU0_NIDEN);
  }
 
  static inline constexpr uint32 DEBUG_FEATURES_DP_CPU0_DBGEN(uint32 value) {
    return ((value << +chip::syscon::Shift::DEBUG_FEATURES_DP_CPU0_DBGEN) &
            +chip::syscon::Mask::DEBUG_FEATURES_DP_CPU0_DBGEN);
  }
 
  static inline constexpr uint32 DEBUG_FEATURES_DP_CPU0_NIDEN(uint32 value) {
    return ((value << +chip::syscon::Shift::DEBUG_FEATURES_DP_CPU0_NIDEN) &
            +chip::syscon::Mask::DEBUG_FEATURES_DP_CPU0_NIDEN);
  }
 
  static inline constexpr uint32 SWD_ACCESS_CPU0_SEC_CODE(uint32 value) {
    return ((value << +chip::syscon::Shift::SWD_ACCESS_CPU0_SEC_CODE) &
            +chip::syscon::Mask::SWD_ACCESS_CPU0_SEC_CODE);
  }
 
  static inline constexpr uint32 DEBUG_AUTH_BEACON_BEACON(uint32 value) {
    return ((value << +chip::syscon::Shift::DEBUG_AUTH_BEACON_BEACON) &
            +chip::syscon::Mask::DEBUG_AUTH_BEACON_BEACON);
  }
 
  static inline constexpr uint32 JTAG_ID_JTAG_ID(uint32 value) {
    return ((value << +chip::syscon::Shift::JTAG_ID_JTAG_ID) &
            +chip::syscon::Mask::JTAG_ID_JTAG_ID);
  }
 
  static inline constexpr uint32 DEVICE_TYPE_DEVICE_TYPE(uint32 value) {
    return ((value << +chip::syscon::Shift::DEVICE_TYPE_DEVICE_TYPE) &
            +chip::syscon::Mask::DEVICE_TYPE_DEVICE_TYPE);
  }
 
  static inline constexpr uint32 DEVICE_ID0_RAM_SIZE(uint32 value) {
    return ((value << +chip::syscon::Shift::DEVICE_ID0_RAM_SIZE) &
            +chip::syscon::Mask::DEVICE_ID0_RAM_SIZE);
  }
 
  static inline constexpr uint32 DEVICE_ID0_FLASH_SIZE(uint32 value) {
    return ((value << +chip::syscon::Shift::DEVICE_ID0_FLASH_SIZE) &
            +chip::syscon::Mask::DEVICE_ID0_FLASH_SIZE);
  }
 
  static inline constexpr uint32 DEVICE_ID0_SECURITY(uint32 value) {
    return ((value << +chip::syscon::Shift::DEVICE_ID0_SECURITY) &
            +chip::syscon::Mask::DEVICE_ID0_SECURITY);
  }
 
  static inline constexpr uint32 DIEID_MINOR_REVISION(uint32 value) {
    return ((value << +chip::syscon::Shift::DIEID_MINOR_REVISION) &
            +chip::syscon::Mask::DIEID_MINOR_REVISION);
  }
 
  static inline constexpr uint32 DIEID_MAJOR_REVISION(uint32 value) {
    return ((value << +chip::syscon::Shift::DIEID_MAJOR_REVISION) &
            +chip::syscon::Mask::DIEID_MAJOR_REVISION);
  }
 
  static inline constexpr uint32 DIEID_MCO_NUM_IN_DIE_ID(uint32 value) {
    return ((value << +chip::syscon::Shift::DIEID_MCO_NUM_IN_DIE_ID) &
            +chip::syscon::Mask::DIEID_MCO_NUM_IN_DIE_ID);
  }
};
 
/* ***************************************************************************************
 * End of file
 */
 
#endif /* CHIP_E90AC029_576D_4863_AF17_144EE618D9F8 */