mFrame
載入中...
搜尋中...
無符合項目
公開屬性 | 全部成員列表
chip::syscon::Register 結構 參考文件

公開屬性

uint8 reserved0 [512]
 
union { 
 
   __IO uint32   remap 
 REMAP[0x200] <RW> 更多...
 
   struct { 
 
      __IO uint32   cpu0_sbus: 2 
 RAMX0[0-1] <RW> 更多...
 
      __IO uint32   dma0: 2 
 RAMX0[2-3] <RW> 更多...
 
      __IO uint32   usb0: 2 
 RAMX0[4-5] <RW> 更多...
 
      __I uint32   reserved0: 25 
 Reserved[6-30]. 更多...
 
      __IO uint32   lock: 1 
 LOCK[31] <RW> 更多...
 
   }   remap_bit 
 REMAP[0x200] <RW> 更多...
 
};  
 
uint8 reserved1 [12]
 
__IO uint32 ahbmatprio
 
uint8 reserved2 [40]
 
__IO uint32 cpu0nstckcal
 
uint8 reserved3 [8]
 
__IO uint32 nmisrc
 
uint8 reserved4 [300]
 
__IO uint32 slowclkdiv
 
uint8 reserved5 [4]
 
__IO uint32 ahbclkdiv
 
uint8 reserved6 [120]
 
union { 
 
   __IO uint32   clkunlock 
 CLKUNLOCK[0x3FC] <RW> 更多...
 
   struct { 
 
      __IO uint32   unlock: 1 
 UNLOCK[0] <RW> 更多...
 
      __I uint32   reserved: 31 
 —[1-31] <RESV> 更多...
 
   }   clkunlock_bit 
 CLKUNLOCK[0x3FC] <RW> 更多...
 
};  
 
__IO uint32 nvm_ctrl
 
uint32 romcr
 
uint8 reserved7 [1028]
 
__I uint32 cpustat
 
uint8 reserved8 [20]
 
union { 
 
   __IO uint32   lpcac_ctrl 
 LPCAC Control, offset: 0x824.
 
   struct { 
 
      __IO uint32   dis_lpcac: 1 
 DIS_LPCAC[0] <RW> 更多...
 
      __IO uint32   clr_lpcac: 1 
 CLR_LPCAC[1] <RW> 更多...
 
      __IO uint32   frc_no_alloc: 1 
 FRC_NO_ALLOC[2] <RW> 更多...
 
      __I uint32   reserved0: 1 
 Reserved[3] <RESD>
 
      __IO uint32   dis_lpcac_wtbf: 1 
 DIS_LPCAC_WTBF[4] <RW> 更多...
 
      __IO uint32   lim_lpcac_wtbf: 1 
 LIM_LPCAC_WTBF[5] <RW> 更多...
 
      __I uint32   reserved1: 1 
 Reserved[6] <RESV>
 
      __IO uint32   lpcac_xom: 1 
 LPCAC_XOM[7] <RW> 更多...
 
      __IO uint32   lpcac_mem_req: 1 
 LPCAC_MEM_REQ[8] <RW> 更多...
 
      __I uint32   reserved2: 23 
 reserved[9-31] <RESV>
 
   }   lpcac_ctrl_bit 
 
};  
 
uint8 reserved9 [272]
 
__IO uint32 pwm0subctl
 
uint8 reserved10 [4]
 
__IO uint32 ctimerglobalstarten
 
__IO uint32 ram_ctrl
 
uint8 reserved_11 [536]
 
__IO uint32 gray_code_lsb
 
__IO uint32 gray_code_msb
 
__I uint32 binary_code_lsb
 
__I uint32 binary_code_msb
 
uint8 reserved_12 [720]
 
__I uint32 ovp_pad_state
 
__I uint32 probe_state
 
__I uint32 ft_state_a
 
__I uint32 rop_state
 
uint8 reserved_13 [8]
 
__IO uint32 sram_xen
 
__IO uint32 sram_xen_dp
 
uint8 reserved_14 [32]
 
__I uint32 els_otp_lc_state
 
__I uint32 els_otp_lc_state_DP
 
uint8 reserved_15 [280]
 
__IO uint32 debug_lock_en
 
__IO uint32 debug_features
 
__IO uint32 debug_features_dp
 
uint8 reserved_16 [8]
 
__IO uint32 swd_access_cpu0
 
uint8 reserved_17 [8]
 
__IO uint32 debug_auth_beacon
 
uint8 reserved_18 [44]
 
__I uint32 jtag_id
 
__I uint32 device_type
 
__I uint32 device_id0
 
__I uint32 dieid
 

資料成員說明文件

◆ ahbclkdiv

__IO uint32 chip::syscon::Register::ahbclkdiv

System Clock Divider, offset: 0x380

◆ ahbmatprio

__IO uint32 chip::syscon::Register::ahbmatprio

AHB Matrix Priority Control, offset: 0x210

◆ binary_code_lsb

__I uint32 chip::syscon::Register::binary_code_lsb

Gray to Binary Converter Binary Code [31:0], offset: 0xB68

◆ binary_code_msb

__I uint32 chip::syscon::Register::binary_code_msb

Gray to Binary Converter Binary Code [41:32], offset: 0xB6C

◆ clkunlock

__IO uint32 chip::syscon::Register::clkunlock

CLKUNLOCK[0x3FC] <RW>

This register controls access to the clock select and divider configuration registers.

◆ [struct]

struct { ... } chip::syscon::Register::clkunlock_bit

CLKUNLOCK[0x3FC] <RW>

This register controls access to the clock select and divider configuration registers.

◆ clr_lpcac

__IO uint32 chip::syscon::Register::clr_lpcac

CLR_LPCAC[1] <RW>

Clears the cache function.

  • [0b]Unclears the cache
  • [1b]Clears the cache

◆ cpu0_sbus

__IO uint32 chip::syscon::Register::cpu0_sbus

RAMX0[0-1] <RW>

address remap for CPU System bus

  • [00b]RAMX0: 0x04000000 - 0x04001ff
  • [01b]RAMX0: 0x20006000 - 0x20007fff

◆ cpu0nstckcal

__IO uint32 chip::syscon::Register::cpu0nstckcal

Non-Secure CPU0 System Tick Calibration, offset: 0x23C

◆ cpustat

__I uint32 chip::syscon::Register::cpustat

CPU Status, offset: 0x80C

◆ ctimerglobalstarten

__IO uint32 chip::syscon::Register::ctimerglobalstarten

CTIMER Global Start Enable, offset: 0x940

◆ debug_auth_beacon

__IO uint32 chip::syscon::Register::debug_auth_beacon

Debug Authentication BEACON, offset: 0xFC0

◆ debug_features

__IO uint32 chip::syscon::Register::debug_features

Cortex Debug Features Control, offset: 0xFA4

◆ debug_features_dp

__IO uint32 chip::syscon::Register::debug_features_dp

Cortex Debug Features Control (Duplicate), offset: 0xFA8

◆ debug_lock_en

__IO uint32 chip::syscon::Register::debug_lock_en

Control Write Access to Security, offset: 0xFA0

◆ device_id0

__I uint32 chip::syscon::Register::device_id0

Device ID, offset: 0xFF8

◆ device_type

__I uint32 chip::syscon::Register::device_type

Device Type, offset: 0xFF4

◆ dieid

__I uint32 chip::syscon::Register::dieid

Chip Revision ID and Number, offset: 0xFFC

◆ dis_lpcac

__IO uint32 chip::syscon::Register::dis_lpcac

DIS_LPCAC[0] <RW>

Disables/enables the cache function.

  • [0b]Enabled
  • [1b]Disabled

◆ dis_lpcac_wtbf

__IO uint32 chip::syscon::Register::dis_lpcac_wtbf

DIS_LPCAC_WTBF[4] <RW>

Disable LPCAC Write Through Buffer.

  • [0b]Enables write through buffer
  • [1b]Disables write through buffer

◆ dma0

__IO uint32 chip::syscon::Register::dma0

RAMX0[2-3] <RW>

address remap for DMA0

  • [00b]RAMX0: 0x04000000 - 0x04001fff
  • [01b]RAMX0: same alias space as CPU0_SBUS

◆ els_otp_lc_state

__I uint32 chip::syscon::Register::els_otp_lc_state

Life Cycle State Register, offset: 0xE80

◆ els_otp_lc_state_DP

__I uint32 chip::syscon::Register::els_otp_lc_state_DP

Life Cycle State Register (Duplicate), offset: 0xE84

◆ frc_no_alloc

__IO uint32 chip::syscon::Register::frc_no_alloc

FRC_NO_ALLOC[2] <RW>

Forces no allocation.

  • [0b]Forces allocation
  • [1b]Forces no allocation

◆ ft_state_a

__I uint32 chip::syscon::Register::ft_state_a

FT_STATE_A, offset: 0xE48

◆ gray_code_lsb

__IO uint32 chip::syscon::Register::gray_code_lsb

Gray to Binary Converter Gray Code [31:0], offset: 0xB60

◆ gray_code_msb

__IO uint32 chip::syscon::Register::gray_code_msb

Gray to Binary Converter Gray Code [41:32], offset: 0xB64

◆ jtag_id

__I uint32 chip::syscon::Register::jtag_id

JTAG Chip ID, offset: 0xFF0

◆ lim_lpcac_wtbf

__IO uint32 chip::syscon::Register::lim_lpcac_wtbf

LIM_LPCAC_WTBF[5] <RW>

Limit LPCAC Write Through Buffer.

  • [0b]Write buffer enabled when transaction is bufferable.
  • [1b]Write buffer enabled when transaction is cacheable and bufferable

◆ lock

__IO uint32 chip::syscon::Register::lock

LOCK[31] <RW>

This 1-bit field provides a mechanism to limit writes to the this register to protect its contents. Once set,this bit remains asserted until a system reset.

  • [0b]This register is not locked and can be altered.
  • [1b]This register is locked and cannot be altered until a system reset.

◆ lpcac_mem_req

__IO uint32 chip::syscon::Register::lpcac_mem_req

LPCAC_MEM_REQ[8] <RW>

Request LPCAC memories.

  • [0b]Configure shared memories RAMX1 as general memories.
  • [1b]Configure shared memories RAMX1 as LPCAC memories, write one lock until a systemreset.

◆ lpcac_xom

__IO uint32 chip::syscon::Register::lpcac_xom

LPCAC_XOM[7] <RW>

LPCAC XOM(eXecute-Only-Memory) attribute control

Controls if the instruction fetch attribute is used as part of the address input to the LPCAC. When XOM regions in the internal flash are not configured at the MBC, then this option should be disabled so that instructions and data can be stored within the same cache line. This provides the best cache efficiency for non-XOM applications. When XOM areas in the internal flash are configured at the MBC, then this bit must be set so that instructions and data are cached using separate lines within the LPCAC.

  • [0b]Disabled.
  • [1b]Enabled.

◆ nmisrc

__IO uint32 chip::syscon::Register::nmisrc

NMI Source Select, offset: 0x248

◆ nvm_ctrl

__IO uint32 chip::syscon::Register::nvm_ctrl

NVM Control, offset: 0x400

◆ ovp_pad_state

__I uint32 chip::syscon::Register::ovp_pad_state

OVP_PAD_STATE, offset: 0xE40

◆ probe_state

__I uint32 chip::syscon::Register::probe_state

PROBE_STATE, offset: 0xE44

◆ pwm0subctl

__IO uint32 chip::syscon::Register::pwm0subctl

PWM0 Submodule Control, offset: 0x938

◆ ram_ctrl

__IO uint32 chip::syscon::Register::ram_ctrl

RAM Control, offset: 0x944

◆ remap

__IO uint32 chip::syscon::Register::remap

REMAP[0x200] <RW>

AHB Matrix Remap Control

The Multilayer AHB Matrix remap for all masters, when they attempt to access the matrix slave port.

◆ [struct]

struct { ... } chip::syscon::Register::remap_bit

REMAP[0x200] <RW>

AHB Matrix Remap Control

The Multilayer AHB Matrix remap for all masters, when they attempt to access the matrix slave port.

◆ reserved

__I uint32 chip::syscon::Register::reserved

—[1-31] <RESV>

Reserved

◆ reserved0

__I uint32 chip::syscon::Register::reserved0

Reserved[6-30].

Reserved[3] <RESD>

Reserved Read value is undefined, only zero should be written.

◆ romcr

uint32 chip::syscon::Register::romcr

ROM Wait State, offset: 0x404

◆ rop_state

__I uint32 chip::syscon::Register::rop_state

ROP State Register, offset: 0xE4C

◆ slowclkdiv

__IO uint32 chip::syscon::Register::slowclkdiv

SLOW_CLK Clock Divider, offset: 0x378

◆ sram_xen

__IO uint32 chip::syscon::Register::sram_xen

RAM XEN Control, offset: 0xE58

◆ sram_xen_dp

__IO uint32 chip::syscon::Register::sram_xen_dp

RAM XEN Control (Duplicate), offset: 0xE5C

◆ swd_access_cpu0

__IO uint32 chip::syscon::Register::swd_access_cpu0

CPU0 Software Debug Access, offset: 0xFB4

◆ unlock

__IO uint32 chip::syscon::Register::unlock

UNLOCK[0] <RW>

Controls clock configuration registers access (for example, MRCC_xxx_CLKDIV, MRCC_xxx_CLKSEL, MRCC_GLB_xxx)

-[0b]Updates are allowed to all clock configuration registers

-[1b]Freezes all clock configuration registers update

◆ usb0

__IO uint32 chip::syscon::Register::usb0

RAMX0[4-5] <RW>

address remap for USB0

  • [00b]RAMX0: 0x04000000 - 0x04001fff
  • [01b]RAMX0: same alias space as CPU0_SBUS
此結構(structure) 文件是由下列檔案中產生: