類別chip::scg::SCG的繼承圖:

公開方法(Public Methods)
virtual	~SCG (void) override
	Destroy the object.

公開方法(Public Methods) 繼承自 mframe::lang::Object
	Object (void)
	Construct a new Object object.

virtual	~Object (void) override
	Destroy the Object object.

void *	operator new (size_t n)

void *	operator new (size_t n, void *p)

mframe::lang::Object &	getObject (void) override
	取得類Object

void	delay (int milliseconds) const
	函數 delay 等待內核滴答中指定的時間段。對於1的值，系統等待直到下一個計時器滴答發生。實際時間延遲最多可能比指定時間少一個計時器滴答聲，即在下一個系統滴答聲發生之前立即調用 osDelay(1)，線程會立即重新安排。

bool	equals (Object *object) const
	函數 delay 等待內核滴答中指定的時間段。對於1的值，系統等待直到下一個計時器滴答發生。實際時間延遲最多可能比指定時間少一個計時器滴答聲，即在下一個系統滴答聲發生之前立即調用 osDelay(1)，線程會立即重新安排。

bool	equals (Object &object) const
	函數 delay 等待內核滴答中指定的時間段。對於1的值，系統等待直到下一個計時器滴答發生。實際時間延遲最多可能比指定時間少一個計時器滴答聲，即在下一個系統滴答聲發生之前立即調用 osDelay(1)，線程會立即重新安排。

void	wait (void) const
	導致當前線程等待，直到另一個線程調用此對象的notify()方法或notifyAll()方法，或指定的時間已過。

bool	wait (int timeout) const
	導致當前線程等待，直到另一個線程調用此對象的 notify()方法或 notifyAll()方法，或其他一些線程中斷當前線程，或一定量的實時時間。

bool	yield (void) const
	函數yield()將控制權傳遞給處於READY狀態且具有相同優先級的下一個線程。如果在READY狀態下沒有其他優先級相同的線程，則當前線程繼續執行，不會發生線程切換。

int	lock (void) const
	核心鎖定，在調用unlock以前將不會進行執行緒切換

int	unlock (void) const
	核心解鎖。

mframe::sys::Thread *	currentThread (void) const
	取得當前的執行緒

virtual int	hashcode (void) const
	返回對象的哈希碼值。支持這種方法是為了散列表，如HashMap提供的那樣。

公開方法(Public Methods) 繼承自 mframe::lang::Interface
virtual	~Interface (void)=default
	Destroy the struct object.

靜態公開方法(Static Public Methods)
static constexpr uint32	VERID_VERSION (uint32 value)
	VERID - VERSION.

static constexpr uint32	PARAM_SOSCCLKPRES (uint32 value)
	PARAM - SOSCCLKPRES.

static constexpr uint32	PARAM_SIRCCLKPRES (uint32 value)
	PARAM - SIRCCLKPRES.

static constexpr uint32	PARAM_FIRCCLKPRES (uint32 value)
	PARAM - FIRCCLKPRES.

static constexpr uint32	PARAM_ROSCCLKPRES (uint32 value)
	PARAM - ROSCCLKPRES.

static constexpr uint32	TRIM_LOCK_TRIM_UNLOCK (uint32 value)
	PARAM - TRIM_UNLOCK.

static constexpr uint32	TRIM_LOCK_IFR_DISABLE (uint32 value)
	TRIM_LOCK - IFR_DISABLE.

static constexpr uint32	TRIM_LOCK_TRIM_LOCK_KEY (uint32 value)
	TRIM_LOCK - TRIM_LOCK_KEY.

static constexpr uint32	CSR_SCS (uint32 value)
	SCS.

static constexpr uint32	RCCR_SCS (uint32 value)
	CSR - SCS.

static constexpr uint32	SOSCCSR_SOSCEN (uint32 value)
	RCCR - SOSCEN.

static constexpr uint32	SOSCCSR_SOSCSTEN (uint32 value)
	SOSCCSR - SOSCSTEN.

static constexpr uint32	SOSCCSR_SOSCCM (uint32 value)
	SOSCCSR - SOSCCM.

static constexpr uint32	SOSCCSR_SOSCCMRE (uint32 value)
	SOSCCSR - SOSCCMRE.

static constexpr uint32	SOSCCSR_LK (uint32 value)
	SOSCCSR - LK.

static constexpr uint32	SOSCCSR_SOSCVLD (uint32 value)
	SOSCVLD.

static constexpr uint32	SOSCCSR_SOSCSEL (uint32 value)
	SOSCCSR - SOSCSEL.

static constexpr uint32	SOSCCSR_SOSCERR (uint32 value)
	SOSCCSR - SOSCERR.

static constexpr uint32	SOSCCSR_SOSCVLD_IE (uint32 value)
	SOSCCSR - SOSCVLD_IE.

static constexpr uint32	SOSCCFG_EREFS (uint32 value)
	SOSCCFG - EREFS.

static constexpr uint32	SOSCCFG_RANGE (uint32 value)
	SOSCCFG - RANGE.

static constexpr uint32	SIRCCSR_SIRCSTEN (uint32 value)
	SIRCCSR - SIRCSTEN.

static constexpr uint32	SIRCCSR_SIRC_CLK_PERIPH_EN (uint32 value)
	SIRCCSR - SIRC_CLK_PERIPH_EN.

static constexpr uint32	SIRCCSR_SIRCTREN (uint32 value)
	SIRCCSR - SIRCTREN.

static constexpr uint32	SIRCCSR_SIRCTRUP (uint32 value)
	SIRCTRUP.

static constexpr uint32	SIRCCSR_TRIM_LOCK (uint32 value)
	SIRCCSR - TRIM_LOCK.

static constexpr uint32	SIRCCSR_COARSE_TRIM_BYPASS (uint32 value)
	SIRCCSR - COARSE_TRIM_BYPASS.

static constexpr uint32	SIRCCSR_LK (uint32 value)
	SIRCCSR - LK.

static constexpr uint32	SIRCCSR_SIRCVLD (uint32 value)
	SIRCCSR - SIRCVLD.

static constexpr uint32	SIRCCSR_SIRCSEL (uint32 value)
	SIRCCSR - SIRCSEL.

static constexpr uint32	SIRCCSR_SIRCERR (uint32 value)
	SIRCCSR - SIRCERR.

static constexpr uint32	SIRCCSR_SIRCERR_IE (uint32 value)
	SIRCCSR - SIRCERR_IE.

static constexpr uint32	SIRCTCFG_TRIMSRC (uint32 value)
	SIRCTCFG - TRIMSRC.

static constexpr uint32	SIRCTCFG_TRIMDIV (uint32 value)
	SIRCTCFG - TRIMDIV.

static constexpr uint32	SIRCTRIM_CCOTRIM (uint32 value)
	SIRCTRIM - CCOTRIM.

static constexpr uint32	SIRCTRIM_CLTRIM (uint32 value)
	SIRCTRIM - CLTRIM.

static constexpr uint32	SIRCTRIM_TCTRIM (uint32 value)
	SIRCTRIM - TCTRIM.

static constexpr uint32	SIRCTRIM_FVCHTRIM (uint32 value)
	SIRCTRIM - FVCHTRIM.

static constexpr uint32	SIRCSTAT_CCOTRIM (uint32 value)
	SIRCSTAT - CCOTRIM.

static constexpr uint32	SIRCSTAT_CLTRIM (uint32 value)
	SIRCSTAT - CLTRIM.

static constexpr uint32	FIRCCSR_FIRCEN (uint32 value)
	FIRCEN.

static constexpr uint32	FIRCCSR_FIRCSTEN (uint32 value)
	FIRCCSR - FIRCSTEN.

static constexpr uint32	FIRCCSR_FIRC_SCLK_PERIPH_EN (uint32 value)
	FIRCCSR - FIRC_SCLK_PERIPH_EN.

static constexpr uint32	FIRCCSR_FIRC_FCLK_PERIPH_EN (uint32 value)
	FIRCCSR - FIRC_FCLK_PERIPH_EN.

static constexpr uint32	FIRCCSR_FIRCTREN (uint32 value)
	FIRCCSR - FIRCTREN.

static constexpr uint32	FIRCCSR_FIRCTRUP (uint32 value)
	FIRCCSR - FIRCTRUP.

static constexpr uint32	FIRCCSR_TRIM_LOCK (uint32 value)
	FIRCCSR - TRIM_LOCK.

static constexpr uint32	FIRCCSR_COARSE_TRIM_BYPASS (uint32 value)
	FIRCCSR - COARSE_TRIM_BYPASS.

static constexpr uint32	FIRCCSR_LK (uint32 value)
	FIRCCSR - LK.

static constexpr uint32	FIRCCSR_FIRCVLD (uint32 value)
	FIRCCSR - FIRCVLD.

static constexpr uint32	FIRCCSR_FIRCSEL (uint32 value)
	FIRCCSR - FIRCSEL.

static constexpr uint32	FIRCCSR_FIRCERR (uint32 value)
	FIRCCSR - FIRCERR.

static constexpr uint32	FIRCCSR_FIRCERR_IE (uint32 value)
	FIRCCSR - FIRCERR_IE.

static constexpr uint32	FIRCCSR_FIRCACC_IE (uint32 value)
	FIRCCSR - FIRCACC_IE.

static constexpr uint32	FIRCCSR_FIRCACC (uint32 value)
	FIRCCSR - FIRCACC.

static constexpr uint32	FIRCCFG_FREQ_SEL (uint32 value)
	FIRCCFG - FREQ_SEL.

static constexpr uint32	FIRCTCFG_TRIMSRC (uint32 value)
	FIRCCFG - TRIMSRC.

static constexpr uint32	FIRCTCFG_TRIMDIV (uint32 value)
	FIRCCFG - TRIMDIV.

static constexpr uint32	FIRCTRIM_TRIMFINE (uint32 value)
	FIRCTRIM - TRIMFINE.

static constexpr uint32	FIRCTRIM_TRIMCOAR (uint32 value)
	FIRCTRIM - TRIMCOAR.

static constexpr uint32	FIRCTRIM_TRIMTEMP2 (uint32 value)
	FIRCTRIM - TRIMTEMP2.

static constexpr uint32	FIRCTRIM_TRIMSTART (uint32 value)
	FIRCTRIM - TRIMSTART.

static constexpr uint32	FIRCSTAT_TRIMFINE (uint32 value)
	FIRCSTAT - TRIMFINE.

static constexpr uint32	FIRCSTAT_TRIMCOAR (uint32 value)
	FIRCSTAT - TRIMCOAR.

static constexpr uint32	FIRCATC1_IDEALC (uint32 value)
	FIRCATC1 - IDEALC.

static constexpr uint32	FIRCATC2_COARMINC (uint32 value)
	FIRCATC2 - COARMINC.

static constexpr uint32	FIRCATC2_COARMAXC (uint32 value)
	FIRCATC2 - COARMAXC.

static constexpr uint32	FIRCATC3_FINEMINC (uint32 value)
	FIRCATC3 - FINEMINC.

static constexpr uint32	FIRCATC3_FINEMAXC (uint32 value)
	FIRCATC3 - FINEMAXC.

static constexpr uint32	ROSCCSR_LK (uint32 value)
	ROSCCSR - LK.

static constexpr uint32	ROSCCSR_ROSCVLD (uint32 value)
	ROSCCSR - ROSCVLD.

static constexpr uint32	ROSCCSR_ROSCSEL (uint32 value)
	ROSCCSR - ROSCSEL.

static constexpr uint32	ROSCCSR_ROSCERR (uint32 value)
	ROSCCSR - ROSCERR.

函式成員說明文件

◆ CSR_SCS()

static constexpr uint32 chip::scg::SCG::CSR_SCS ( uint32 value )

inlinestaticconstexpr

SCS.

System Clock Source

[0b000]Reserved
[0b001]SOSC
[0b010]SIRC
[0b011]FIRC
[0b100]ROSC
[0b101-0b111]Reserved

◆ FIRCATC1_IDEALC()

static constexpr uint32 chip::scg::SCG::FIRCATC1_IDEALC ( uint32 value )

inlinestaticconstexpr

FIRCATC1 - IDEALC.

FIRC Auto-trimming Counter 1 - Ideal Counter

◆ FIRCATC2_COARMAXC()

static constexpr uint32 chip::scg::SCG::FIRCATC2_COARMAXC ( uint32 value )

inlinestaticconstexpr

FIRCATC2 - COARMAXC.

FIRC Auto-trimming Counter 1 - Coarse Trim Maximum Counter

◆ FIRCATC2_COARMINC()

static constexpr uint32 chip::scg::SCG::FIRCATC2_COARMINC ( uint32 value )

inlinestaticconstexpr

FIRCATC2 - COARMINC.

FIRC Auto-trimming Counter 1 - Coarse Trim Minimum Counter

◆ FIRCATC3_FINEMAXC()

static constexpr uint32 chip::scg::SCG::FIRCATC3_FINEMAXC ( uint32 value )

inlinestaticconstexpr

FIRCATC3 - FINEMAXC.

FIRC Auto-trimming Counter 2 - Fine Trim Maximum Counter

◆ FIRCATC3_FINEMINC()

static constexpr uint32 chip::scg::SCG::FIRCATC3_FINEMINC ( uint32 value )

inlinestaticconstexpr

FIRCATC3 - FINEMINC.

FIRC Auto-trimming Counter 2 - Fine Trim Minimum Counter

◆ FIRCCFG_FREQ_SEL()

static constexpr uint32 chip::scg::SCG::FIRCCFG_FREQ_SEL ( uint32 value )

inlinestaticconstexpr

FIRCCFG - FREQ_SEL.

FIRC Configuration Register - Frequency select

[0b111]192 MHz FIRC clock selected
[0b101]96 MHz FIRC clock selected
[0b011]64 MHz FIRC clock selected
[0b001]48 MHz FIRC clock selected, divided from 192 MHz

◆ FIRCCSR_COARSE_TRIM_BYPASS()

static constexpr uint32 chip::scg::SCG::FIRCCSR_COARSE_TRIM_BYPASS ( uint32 value )

inlinestaticconstexpr

FIRCCSR - COARSE_TRIM_BYPASS.

FIRC Control Status Register - Coarse Auto Trim Bypass

[0b0]FIRC Coarse Auto Trim NOT Bypassed
[0b1]FIRC Coarse Auto Trim Bypassed

◆ FIRCCSR_FIRC_FCLK_PERIPH_EN()

static constexpr uint32 chip::scg::SCG::FIRCCSR_FIRC_FCLK_PERIPH_EN ( uint32 value )

inlinestaticconstexpr

FIRCCSR - FIRC_FCLK_PERIPH_EN.

FIRC Control Status Register - FRO_HF Clock to peripherals Enable

[0b0]FRO_HF to peripherals is disabled

[0b1]FRO_HF to peripherals is enabled

◆ FIRCCSR_FIRC_SCLK_PERIPH_EN()

static constexpr uint32 chip::scg::SCG::FIRCCSR_FIRC_SCLK_PERIPH_EN ( uint32 value )

inlinestaticconstexpr

FIRCCSR - FIRC_SCLK_PERIPH_EN.

FIRC Control Status Register - FIRC 48 MHz Clock to peripherals Enable

[0b0]FIRC 48 MHz to peripherals is disabled

[0b1]FIRC 48 MHz to peripherals is enabled

◆ FIRCCSR_FIRCACC()

static constexpr uint32 chip::scg::SCG::FIRCCSR_FIRCACC ( uint32 value )

inlinestaticconstexpr

FIRCCSR - FIRCACC.

FIRC Control Status Register - FIRC Frequency Accurate

-[0b0]FIRC is not enabled or clock is not accurate.

-[0b1]FIRC is enabled and output clock is accurate after some preparation time which is obtained by counting FRO_HF clock.

◆ FIRCCSR_FIRCACC_IE()

static constexpr uint32 chip::scg::SCG::FIRCCSR_FIRCACC_IE ( uint32 value )

inlinestaticconstexpr

FIRCCSR - FIRCACC_IE.

FIRC Control Status Register - FIRC Accurate Interrupt Enable

[0b0]FIRCACC interrupt is not enabled
[0b1]FIRCACC interrupt is enabled

◆ FIRCCSR_FIRCEN()

static constexpr uint32 chip::scg::SCG::FIRCCSR_FIRCEN ( uint32 value )

inlinestaticconstexpr

FIRCEN.

SIRC Auto-trimming Status Register - FIRC Enable

[0b0]FIRC is disabled
[0b1]FIRC is enabled

◆ FIRCCSR_FIRCERR()

static constexpr uint32 chip::scg::SCG::FIRCCSR_FIRCERR ( uint32 value )

inlinestaticconstexpr

FIRCCSR - FIRCERR.

FIRC Control Status Register - FIRC Clock Error

[0b0]Error not detected with the FIRC trimming
[0b1]Error detected with the FIRC trimming

◆ FIRCCSR_FIRCERR_IE()

static constexpr uint32 chip::scg::SCG::FIRCCSR_FIRCERR_IE ( uint32 value )

inlinestaticconstexpr

FIRCCSR - FIRCERR_IE.

FIRC Control Status Register - FIRC Clock Error Interrupt Enable

[0b0]FIRCERR interrupt is not enabled
[0b1]FIRCERR interrupt is enabled

◆ FIRCCSR_FIRCSEL()

static constexpr uint32 chip::scg::SCG::FIRCCSR_FIRCSEL ( uint32 value )

inlinestaticconstexpr

FIRCCSR - FIRCSEL.

FIRC Control Status Register - FIRC Selected

[0b0]FIRC is not the system clock source
[0b1]FIRC is the system clock source

◆ FIRCCSR_FIRCSTEN()

static constexpr uint32 chip::scg::SCG::FIRCCSR_FIRCSTEN ( uint32 value )

inlinestaticconstexpr

FIRCCSR - FIRCSTEN.

FIRC Control Status Register - FIRC Stop Enable

[0b0]FIRC is disabled in Deep Sleep mode
[0b1]FIRC is enabled in Deep Sleep mode

◆ FIRCCSR_FIRCTREN()

static constexpr uint32 chip::scg::SCG::FIRCCSR_FIRCTREN ( uint32 value )

inlinestaticconstexpr

FIRCCSR - FIRCTREN.

FIRC Control Status Register - FRO_HF Trim Enable

[0b0]Disables trimming FRO_HF by an external clock source
[0b1]Enables trimming FRO_HF by an external clock source

◆ FIRCCSR_FIRCTRUP()

static constexpr uint32 chip::scg::SCG::FIRCCSR_FIRCTRUP ( uint32 value )

inlinestaticconstexpr

FIRCCSR - FIRCTRUP.

FIRC Control Status Register - FIRC Trim Update

[0b0]Disables FIRC trimming updates
[0b1]Enables FIRC trimming updates

◆ FIRCCSR_FIRCVLD()

static constexpr uint32 chip::scg::SCG::FIRCCSR_FIRCVLD ( uint32 value )

inlinestaticconstexpr

FIRCCSR - FIRCVLD.

FIRC Control Status Register - FIRC Valid status

[0b0]FIRC is not enabled or clock is not valid.
[0b1]FIRC is enabled and output clock is valid. The clock is valid after there is an output clock from the FIRC analog.

◆ FIRCCSR_LK()

static constexpr uint32 chip::scg::SCG::FIRCCSR_LK ( uint32 value )

inlinestaticconstexpr

FIRCCSR - LK.

FIRC Control Status Register - Lock Register

[0b0]Control Status Register can be written
[0b1]Control Status Register cannot be written

◆ FIRCCSR_TRIM_LOCK()

static constexpr uint32 chip::scg::SCG::FIRCCSR_TRIM_LOCK ( uint32 value )

inlinestaticconstexpr

FIRCCSR - TRIM_LOCK.

FIRC Control Status Register - FIRC TRIM LOCK

[0b0]FIRC auto trim not locked to target frequency range
[0b1]FIRC auto trim locked to target frequency range

◆ FIRCSTAT_TRIMCOAR()

static constexpr uint32 chip::scg::SCG::FIRCSTAT_TRIMCOAR ( uint32 value )

inlinestaticconstexpr

FIRCSTAT - TRIMCOAR.

FIRC Auto-trimming Status Register - Trim Coarse

◆ FIRCSTAT_TRIMFINE()

static constexpr uint32 chip::scg::SCG::FIRCSTAT_TRIMFINE ( uint32 value )

inlinestaticconstexpr

FIRCSTAT - TRIMFINE.

FIRC Auto-trimming Status Register - Trim Fine

◆ FIRCTCFG_TRIMDIV()

static constexpr uint32 chip::scg::SCG::FIRCTCFG_TRIMDIV ( uint32 value )

inlinestaticconstexpr

FIRCCFG - TRIMDIV.

FIRC Configuration Register - FIRC Trim Pre-divider

◆ FIRCTCFG_TRIMSRC()

static constexpr uint32 chip::scg::SCG::FIRCTCFG_TRIMSRC ( uint32 value )

inlinestaticconstexpr

FIRCCFG - TRIMSRC.

FIRC Configuration Register - Trim Source

[0b00]USB0 Start of Frame (1 KHz). This option does not use TRIMDIV .
[0b01]Reserved
[0b10]SOSC. This option requires that SOSC be divided using the TRIMDIV field to get a frequency of 1 MHz.
[0b11]Reserved

◆ FIRCTRIM_TRIMCOAR()

static constexpr uint32 chip::scg::SCG::FIRCTRIM_TRIMCOAR ( uint32 value )

inlinestaticconstexpr

FIRCTRIM - TRIMCOAR.

FIRC Trim Register - Trim Coarse

◆ FIRCTRIM_TRIMFINE()

static constexpr uint32 chip::scg::SCG::FIRCTRIM_TRIMFINE ( uint32 value )

inlinestaticconstexpr

FIRCTRIM - TRIMFINE.

FIRC Trim Register - Trim Fine

◆ FIRCTRIM_TRIMSTART()

static constexpr uint32 chip::scg::SCG::FIRCTRIM_TRIMSTART ( uint32 value )

inlinestaticconstexpr

FIRCTRIM - TRIMSTART.

FIRC Trim Register - Trim Start

◆ FIRCTRIM_TRIMTEMP2()

static constexpr uint32 chip::scg::SCG::FIRCTRIM_TRIMTEMP2 ( uint32 value )

inlinestaticconstexpr

FIRCTRIM - TRIMTEMP2.

FIRC Trim Register - Trim Temperature2

◆ PARAM_FIRCCLKPRES()

static constexpr uint32 chip::scg::SCG::PARAM_FIRCCLKPRES ( uint32 value )

inlinestaticconstexpr

PARAM - FIRCCLKPRES.

Parameter Register - FIRC Clock Present

[0b1]FIRC clock source is present
[0b0]FIRC clock source is not present

◆ PARAM_ROSCCLKPRES()

static constexpr uint32 chip::scg::SCG::PARAM_ROSCCLKPRES ( uint32 value )

inlinestaticconstexpr

PARAM - ROSCCLKPRES.

Parameter Register - ROSC Clock Present

[0b1]ROSC clock source is present
[0b0]ROSC clock source is not present

◆ PARAM_SIRCCLKPRES()

static constexpr uint32 chip::scg::SCG::PARAM_SIRCCLKPRES ( uint32 value )

inlinestaticconstexpr

PARAM - SIRCCLKPRES.

Parameter Register - SIRC Clock Present

[0b1]SIRC clock source is present
[0b0]SIRC clock source is not present

◆ PARAM_SOSCCLKPRES()

static constexpr uint32 chip::scg::SCG::PARAM_SOSCCLKPRES ( uint32 value )

inlinestaticconstexpr

PARAM - SOSCCLKPRES.

Parameter Register - SOSC Clock Present

[0b1]SOSC clock source is present
[0b0]SOSC clock source is not present

◆ RCCR_SCS()

static constexpr uint32 chip::scg::SCG::RCCR_SCS ( uint32 value )

inlinestaticconstexpr

CSR - SCS.

Clock Status Register - System Clock Source

[0b000]Reserved
[0b001]SOSC
[0b010]SIRC
[0b011]FIRC
[0b100]ROSC
[0b101-0b111]Reserved

◆ ROSCCSR_LK()

static constexpr uint32 chip::scg::SCG::ROSCCSR_LK ( uint32 value )

inlinestaticconstexpr

ROSCCSR - LK.

ROSC Control Status Register - Lock Register

[0b0]Control Status Register can be written
[0b1]Control Status Register cannot be written

◆ ROSCCSR_ROSCERR()

static constexpr uint32 chip::scg::SCG::ROSCCSR_ROSCERR ( uint32 value )

inlinestaticconstexpr

ROSCCSR - ROSCERR.

ROSC Control Status Register - ROSC Clock Error

[0b0]ROSC Clock has not detected an error
[0b1]ROSC Clock has detected an error

◆ ROSCCSR_ROSCSEL()

static constexpr uint32 chip::scg::SCG::ROSCCSR_ROSCSEL ( uint32 value )

inlinestaticconstexpr

ROSCCSR - ROSCSEL.

ROSC Control Status Register - ROSC Selected

[0b0]ROSC is not the system clock source
[0b1]ROSC is the system clock source

◆ ROSCCSR_ROSCVLD()

static constexpr uint32 chip::scg::SCG::ROSCCSR_ROSCVLD ( uint32 value )

inlinestaticconstexpr

ROSCCSR - ROSCVLD.

ROSC Control Status Register - ROSC Valid

[0b0]ROSC is not enabled or clock is not valid
[0b1]ROSC is enabled and output clock is valid

◆ SIRCCSR_COARSE_TRIM_BYPASS()

static constexpr uint32 chip::scg::SCG::SIRCCSR_COARSE_TRIM_BYPASS ( uint32 value )

inlinestaticconstexpr

SIRCCSR - COARSE_TRIM_BYPASS.

SIRC Control Status Register - Coarse Auto Trim Bypass

[0b0]SIRC Coarse Auto Trim NOT Bypassed
[0b1]SIRC Coarse Auto Trim Bypassed

◆ SIRCCSR_LK()

static constexpr uint32 chip::scg::SCG::SIRCCSR_LK ( uint32 value )

inlinestaticconstexpr

SIRCCSR - LK.

SIRC Control Status Register - Lock Register

[0b0]Control Status Register can be written
[0b1]Control Status Register cannot be written

◆ SIRCCSR_SIRC_CLK_PERIPH_EN()

static constexpr uint32 chip::scg::SCG::SIRCCSR_SIRC_CLK_PERIPH_EN ( uint32 value )

inlinestaticconstexpr

SIRCCSR - SIRC_CLK_PERIPH_EN.

SIRC Control Status Register - SIRC Clock to Peripherals Enable

[0b0]SIRC clock to peripherals is disabled
[0b1]SIRC clock to peripherals is enabled

◆ SIRCCSR_SIRCERR()

static constexpr uint32 chip::scg::SCG::SIRCCSR_SIRCERR ( uint32 value )

inlinestaticconstexpr

SIRCCSR - SIRCERR.

SIRC Control Status Register - SIRC Clock Error

[0b0]Error not detected with the SIRC trimming
[0b1]Error detected with the SIRC trimming

◆ SIRCCSR_SIRCERR_IE()

static constexpr uint32 chip::scg::SCG::SIRCCSR_SIRCERR_IE ( uint32 value )

inlinestaticconstexpr

SIRCCSR - SIRCERR_IE.

SIRC Control Status Register - SIRC Clock Error Interrupt Enable

[0b0]SIRCERR interrupt is not enabled
[0b1]SIRCERR interrupt is enabled

◆ SIRCCSR_SIRCSEL()

static constexpr uint32 chip::scg::SCG::SIRCCSR_SIRCSEL ( uint32 value )

inlinestaticconstexpr

SIRCCSR - SIRCSEL.

SIRC Control Status Register - SIRC Selected

[0b0]SIRC is not the system clock source
[0b1]SIRC is the system clock source

◆ SIRCCSR_SIRCSTEN()

static constexpr uint32 chip::scg::SCG::SIRCCSR_SIRCSTEN ( uint32 value )

inlinestaticconstexpr

SIRCCSR - SIRCSTEN.

SIRC Control Status Register - SIRC Stop Enable

[0b0]SIRC is disabled in Deep Sleep mode
[0b1]SIRC is enabled in Deep Sleep mode

◆ SIRCCSR_SIRCTREN()

static constexpr uint32 chip::scg::SCG::SIRCCSR_SIRCTREN ( uint32 value )

inlinestaticconstexpr

SIRCCSR - SIRCTREN.

SIRC Control Status Register - SIRC 12 MHz Trim Enable (SIRCCFG[RANGE]=1)

[0b0]Disables trimming SIRC to an external clock source
[0b1]Enables trimming SIRC to an external clock source

◆ SIRCCSR_SIRCTRUP()

static constexpr uint32 chip::scg::SCG::SIRCCSR_SIRCTRUP ( uint32 value )

inlinestaticconstexpr

SIRCTRUP.

SIRC Control Status Register - SIRC Trim Update

[0b0]Disables SIRC trimming updates
[0b1]Enables SIRC trimming updates

◆ SIRCCSR_SIRCVLD()

static constexpr uint32 chip::scg::SCG::SIRCCSR_SIRCVLD ( uint32 value )

inlinestaticconstexpr

SIRCCSR - SIRCVLD.

SIRC Control Status Register - SIRC Valid

[0b0]SIRC is not enabled or clock is not valid
[0b1]SIRC is enabled and output clock is valid

◆ SIRCCSR_TRIM_LOCK()

static constexpr uint32 chip::scg::SCG::SIRCCSR_TRIM_LOCK ( uint32 value )

inlinestaticconstexpr

SIRCCSR - TRIM_LOCK.

SIRC Control Status Register - SIRC TRIM LOCK

[0b0]SIRC auto trim not locked to target frequency range
[0b1]SIRC auto trim locked to target frequency range

◆ SIRCSTAT_CCOTRIM()

static constexpr uint32 chip::scg::SCG::SIRCSTAT_CCOTRIM ( uint32 value )

inlinestaticconstexpr

SIRCSTAT - CCOTRIM.

SIRC Trim Register - CCO Trim

◆ SIRCSTAT_CLTRIM()

static constexpr uint32 chip::scg::SCG::SIRCSTAT_CLTRIM ( uint32 value )

inlinestaticconstexpr

SIRCSTAT - CLTRIM.

SIRC Auto-trimming Status Register - CL Trim

◆ SIRCTCFG_TRIMDIV()

static constexpr uint32 chip::scg::SCG::SIRCTCFG_TRIMDIV ( uint32 value )

inlinestaticconstexpr

SIRCTCFG - TRIMDIV.

SIRC Trim Configuration Register - SIRC Trim Pre-divider

◆ SIRCTCFG_TRIMSRC()

static constexpr uint32 chip::scg::SCG::SIRCTCFG_TRIMSRC ( uint32 value )

inlinestaticconstexpr

SIRCTCFG - TRIMSRC.

SIRC Trim Configuration Register - Trim Source

[0b00]Reserved
[0b01]Reserved
[0b10]SOSC. This option requires that SOSC be divided using the TRIMDIV field to get a frequency of 1 MHz.
[0b11]Reserved

◆ SIRCTRIM_CCOTRIM()

static constexpr uint32 chip::scg::SCG::SIRCTRIM_CCOTRIM ( uint32 value )

inlinestaticconstexpr

SIRCTRIM - CCOTRIM.

SIRC Trim Register - CCO Trim

◆ SIRCTRIM_CLTRIM()

static constexpr uint32 chip::scg::SCG::SIRCTRIM_CLTRIM ( uint32 value )

inlinestaticconstexpr

SIRCTRIM - CLTRIM.

SIRC Trim Register - CL Trim

◆ SIRCTRIM_FVCHTRIM()

static constexpr uint32 chip::scg::SCG::SIRCTRIM_FVCHTRIM ( uint32 value )

inlinestaticconstexpr

SIRCTRIM - FVCHTRIM.

SIRC Trim Register

◆ SIRCTRIM_TCTRIM()

static constexpr uint32 chip::scg::SCG::SIRCTRIM_TCTRIM ( uint32 value )

inlinestaticconstexpr

SIRCTRIM - TCTRIM.

SIRC Trim Register - Trim Temp

◆ SOSCCFG_EREFS()

static constexpr uint32 chip::scg::SCG::SOSCCFG_EREFS ( uint32 value )

inlinestaticconstexpr

SOSCCFG - EREFS.

SOSC Configuration Register - External Reference Select

[0b0]External reference clock selected.
[0b1]Internal crystal oscillator of OSC selected.

◆ SOSCCFG_RANGE()

static constexpr uint32 chip::scg::SCG::SOSCCFG_RANGE ( uint32 value )

inlinestaticconstexpr

SOSCCFG - RANGE.

SOSC Configuration Register - SOSC Range Select

[0b00]Frequency range select of 8-16 MHz.
[0b01]Frequency range select of 16-25 MHz.
[0b10]Frequency range select of 25-40 MHz.
[0b11]Frequency range select of 40-50 MHz.

◆ SOSCCSR_LK()

static constexpr uint32 chip::scg::SCG::SOSCCSR_LK ( uint32 value )

inlinestaticconstexpr

SOSCCSR - LK.

SOSC Control Status Register - Lock Register

[0b0]This Control Status Register can be written
[0b1]This Control Status Register cannot be written

◆ SOSCCSR_SOSCCM()

static constexpr uint32 chip::scg::SCG::SOSCCSR_SOSCCM ( uint32 value )

inlinestaticconstexpr

SOSCCSR - SOSCCM.

SOSC Control Status Register - SOSC Clock Monitor Enable

[0b0]SOSC Clock Monitor is disabled
[0b1]SOSC Clock Monitor is enabled

◆ SOSCCSR_SOSCCMRE()

static constexpr uint32 chip::scg::SCG::SOSCCSR_SOSCCMRE ( uint32 value )

inlinestaticconstexpr

SOSCCSR - SOSCCMRE.

SOSC Control Status Register - SOSC Clock Monitor Reset Enable

[0b0]Clock monitor generates an interrupt when an error is detected
[0b1]Clock monitor generates a reset when an error is detected

◆ SOSCCSR_SOSCEN()

static constexpr uint32 chip::scg::SCG::SOSCCSR_SOSCEN ( uint32 value )

inlinestaticconstexpr

RCCR - SOSCEN.

Run Clock Control Register - SOSC Enable

[0b0]SOSC is disabled
[0b1]SOSC is enabled

◆ SOSCCSR_SOSCERR()

static constexpr uint32 chip::scg::SCG::SOSCCSR_SOSCERR ( uint32 value )

inlinestaticconstexpr

SOSCCSR - SOSCERR.

SOSC Control Status Register - SOSC Clock Error

-[0b0]SOSC Clock Monitor is disabled or has not detected an error

-[0b1]SOSC Clock Monitor is enabled and detected an error

◆ SOSCCSR_SOSCSEL()

static constexpr uint32 chip::scg::SCG::SOSCCSR_SOSCSEL ( uint32 value )

inlinestaticconstexpr

SOSCCSR - SOSCSEL.

SOSC Control Status Register - SOSC Selected

[0b0]SOSC is not the system clock source
[0b1]SOSC is the system clock source

◆ SOSCCSR_SOSCSTEN()

static constexpr uint32 chip::scg::SCG::SOSCCSR_SOSCSTEN ( uint32 value )

inlinestaticconstexpr

SOSCCSR - SOSCSTEN.

SOSC Control Status Register - SOSC Stop Enable

[0b0]SOSC is disabled in Deep Sleep mode

[0b1]SOSC is enabled in Deep Sleep mode only if SOSCEN is set

◆ SOSCCSR_SOSCVLD()

static constexpr uint32 chip::scg::SCG::SOSCCSR_SOSCVLD ( uint32 value )

inlinestaticconstexpr

SOSCVLD.

SOSC Control Status Register - SOSC Valid

[0b0]SOSC is not enabled or clock is not valid
[0b1]SOSC is enabled and output clock is valid

◆ SOSCCSR_SOSCVLD_IE()

static constexpr uint32 chip::scg::SCG::SOSCCSR_SOSCVLD_IE ( uint32 value )

inlinestaticconstexpr

SOSCCSR - SOSCVLD_IE.

SOSC Control Status Register - SOSC Valid Interrupt Enable

[0b0]SOSCVLD interrupt is not enabled
[0b1]SOSCVLD interrupt is enabled

◆ TRIM_LOCK_IFR_DISABLE()

static constexpr uint32 chip::scg::SCG::TRIM_LOCK_IFR_DISABLE ( uint32 value )

inlinestaticconstexpr

TRIM_LOCK - IFR_DISABLE.

Trim Lock register - IFR_DISABLE

[0b0]IFR write access to SCG trim registers not disabled. The SCG Trim registers are reprogrammed with the IFR values after any system reset.

[0b1]IFR write access to SCG trim registers during system reset is blocked.

◆ TRIM_LOCK_TRIM_LOCK_KEY()

static constexpr uint32 chip::scg::SCG::TRIM_LOCK_TRIM_LOCK_KEY ( uint32 value )

inlinestaticconstexpr

TRIM_LOCK - TRIM_LOCK_KEY.

Trim Lock register - TRIM_LOCK_KEY

◆ TRIM_LOCK_TRIM_UNLOCK()

static constexpr uint32 chip::scg::SCG::TRIM_LOCK_TRIM_UNLOCK ( uint32 value )

inlinestaticconstexpr

PARAM - TRIM_UNLOCK.

Parameter Register - TRIM_UNLOCK

[0b0]SCG Trim Registers locked and not writable.
[0b1]SCG Trim registers unlocked and writable.

◆ VERID_VERSION()

static constexpr uint32 chip::scg::SCG::VERID_VERSION ( uint32 value )

inlinestaticconstexpr

VERID - VERSION.

Version ID Register - SCG Version Number

此類別(class) 文件是由下列檔案中產生:

SCG.h

公開方法(Public Methods)

靜態公開方法(Static Public Methods)

函式成員說明文件

◆ CSR_SCS()

◆ FIRCATC1_IDEALC()

◆ FIRCATC2_COARMAXC()

◆ FIRCATC2_COARMINC()

◆ FIRCATC3_FINEMAXC()

◆ FIRCATC3_FINEMINC()

◆ FIRCCFG_FREQ_SEL()

◆ FIRCCSR_COARSE_TRIM_BYPASS()

◆ FIRCCSR_FIRC_FCLK_PERIPH_EN()

◆ FIRCCSR_FIRC_SCLK_PERIPH_EN()

◆ FIRCCSR_FIRCACC()

◆ FIRCCSR_FIRCACC_IE()

◆ FIRCCSR_FIRCEN()

◆ FIRCCSR_FIRCERR()

◆ FIRCCSR_FIRCERR_IE()

◆ FIRCCSR_FIRCSEL()

◆ FIRCCSR_FIRCSTEN()

◆ FIRCCSR_FIRCTREN()

◆ FIRCCSR_FIRCTRUP()

◆ FIRCCSR_FIRCVLD()

◆ FIRCCSR_LK()

◆ FIRCCSR_TRIM_LOCK()

◆ FIRCSTAT_TRIMCOAR()

◆ FIRCSTAT_TRIMFINE()

◆ FIRCTCFG_TRIMDIV()

◆ FIRCTCFG_TRIMSRC()

◆ FIRCTRIM_TRIMCOAR()

◆ FIRCTRIM_TRIMFINE()

◆ FIRCTRIM_TRIMSTART()

◆ FIRCTRIM_TRIMTEMP2()

◆ PARAM_FIRCCLKPRES()

◆ PARAM_ROSCCLKPRES()

◆ PARAM_SIRCCLKPRES()

◆ PARAM_SOSCCLKPRES()

◆ RCCR_SCS()

◆ ROSCCSR_LK()

◆ ROSCCSR_ROSCERR()

◆ ROSCCSR_ROSCSEL()

◆ ROSCCSR_ROSCVLD()

◆ SIRCCSR_COARSE_TRIM_BYPASS()

◆ SIRCCSR_LK()

◆ SIRCCSR_SIRC_CLK_PERIPH_EN()

◆ SIRCCSR_SIRCERR()

◆ SIRCCSR_SIRCERR_IE()

◆ SIRCCSR_SIRCSEL()

◆ SIRCCSR_SIRCSTEN()

◆ SIRCCSR_SIRCTREN()

◆ SIRCCSR_SIRCTRUP()

◆ SIRCCSR_SIRCVLD()

◆ SIRCCSR_TRIM_LOCK()

◆ SIRCSTAT_CCOTRIM()

◆ SIRCSTAT_CLTRIM()

◆ SIRCTCFG_TRIMDIV()

◆ SIRCTCFG_TRIMSRC()

◆ SIRCTRIM_CCOTRIM()

◆ SIRCTRIM_CLTRIM()

◆ SIRCTRIM_FVCHTRIM()

◆ SIRCTRIM_TCTRIM()

◆ SOSCCFG_EREFS()

◆ SOSCCFG_RANGE()

◆ SOSCCSR_LK()

◆ SOSCCSR_SOSCCM()

◆ SOSCCSR_SOSCCMRE()

◆ SOSCCSR_SOSCEN()

◆ SOSCCSR_SOSCERR()

◆ SOSCCSR_SOSCSEL()

◆ SOSCCSR_SOSCSTEN()

◆ SOSCCSR_SOSCVLD()

◆ SOSCCSR_SOSCVLD_IE()

◆ TRIM_LOCK_IFR_DISABLE()

◆ TRIM_LOCK_TRIM_LOCK_KEY()

◆ TRIM_LOCK_TRIM_UNLOCK()

◆ VERID_VERSION()