SCG.h

 
#ifndef CHIP_68FC7893_16D3_44E3_955F_6A00759AB5C9
#define CHIP_68FC7893_16D3_44E3_955F_6A00759AB5C9
 
/* ***************************************************************************************
 * Include
 */
 
//----------------------------------------------------------------------------------------
#include "mframe.h"
 
//----------------------------------------------------------------------------------------
#include "./Mask.h"
#include "./Register.h"
#include "./Shift.h"
 
/* ***************************************************************************************
 * Namespace
 */
namespace chip::scg {
  class SCG;
  extern Register& SCG0;
}  // namespace chip::scg
 
/* ***************************************************************************************
 * Class/Interface/Struct/Enum
 */
class chip::scg::SCG final : public mframe::lang::Object {
  /* *************************************************************************************
   * Variable
   */
 
  /* *************************************************************************************
   * Abstract Method
   */
 
  /* *************************************************************************************
   * Construct Method
   */
 private:
  SCG(void);
 
 public:
  virtual ~SCG(void) override;
 
  /* *************************************************************************************
   * Operator Method
   */
 
  /* *************************************************************************************
   * Public Method <Override>
   */
 
  /* *************************************************************************************
   * Public Method
   */
 
  /* *************************************************************************************
   * Protected Method
   */
 
  /* *************************************************************************************
   * Private Method
   */
 
  /* *************************************************************************************
   * Static Variable
   */
 
  /* *************************************************************************************
   * Static Method
   */
 public:
  static inline constexpr uint32 VERID_VERSION(uint32 value) {
    return ((value << +chip::scg::Shift::VERID_VERSION) &
            +chip::scg::Mask::VERID_VERSION);
  }
 
  static inline constexpr uint32 PARAM_SOSCCLKPRES(uint32 value) {
    return ((value << +chip::scg::Shift::PARAM_SOSCCLKPRES) &
            +chip::scg::Mask::PARAM_SOSCCLKPRES);
  }
 
  static inline constexpr uint32 PARAM_SIRCCLKPRES(uint32 value) {
    return ((value << +chip::scg::Shift::PARAM_SIRCCLKPRES) &
            +chip::scg::Mask::PARAM_SIRCCLKPRES);
  }
 
  static inline constexpr uint32 PARAM_FIRCCLKPRES(uint32 value) {
    return ((value << +chip::scg::Shift::PARAM_FIRCCLKPRES) &
            +chip::scg::Mask::PARAM_FIRCCLKPRES);
  }
 
  static inline constexpr uint32 PARAM_ROSCCLKPRES(uint32 value) {
    return ((value << +chip::scg::Shift::PARAM_ROSCCLKPRES) &
            +chip::scg::Mask::PARAM_ROSCCLKPRES);
  }
 
  static inline constexpr uint32 TRIM_LOCK_TRIM_UNLOCK(uint32 value) {
    return ((value << +chip::scg::Shift::TRIM_LOCK_TRIM_UNLOCK) &
            +chip::scg::Mask::TRIM_LOCK_TRIM_UNLOCK);
  }
 
  static inline constexpr uint32 TRIM_LOCK_IFR_DISABLE(uint32 value) {
    return ((value << +chip::scg::Shift::TRIM_LOCK_IFR_DISABLE) &
            +chip::scg::Mask::TRIM_LOCK_IFR_DISABLE);
  }
 
  static inline constexpr uint32 TRIM_LOCK_TRIM_LOCK_KEY(uint32 value) {
    return ((value << +chip::scg::Shift::TRIM_LOCK_TRIM_LOCK_KEY) &
            +chip::scg::Mask::TRIM_LOCK_TRIM_LOCK_KEY);
  }
 
  static inline constexpr uint32 CSR_SCS(uint32 value) {
    return ((value << +chip::scg::Shift::CSR_SCS) &
            +chip::scg::Mask::CSR_SCS);
  }
 
  static inline constexpr uint32 RCCR_SCS(uint32 value) {
    return ((value << +chip::scg::Shift::RCCR_SCS) &
            +chip::scg::Mask::RCCR_SCS);
  }
 
  static inline constexpr uint32 SOSCCSR_SOSCEN(uint32 value) {
    return ((value << +chip::scg::Shift::SOSCCSR_SOSCEN) &
            +chip::scg::Mask::SOSCCSR_SOSCEN);
  }
 
  static inline constexpr uint32 SOSCCSR_SOSCSTEN(uint32 value) {
    return ((value << +chip::scg::Shift::SOSCCSR_SOSCSTEN) &
            +chip::scg::Mask::SOSCCSR_SOSCSTEN);
  }
 
  static inline constexpr uint32 SOSCCSR_SOSCCM(uint32 value) {
    return ((value << +chip::scg::Shift::SOSCCSR_SOSCCM) &
            +chip::scg::Mask::SOSCCSR_SOSCCM);
  }
 
  static inline constexpr uint32 SOSCCSR_SOSCCMRE(uint32 value) {
    return ((value << +chip::scg::Shift::SOSCCSR_SOSCCMRE) &
            +chip::scg::Mask::SOSCCSR_SOSCCMRE);
  }
 
  static inline constexpr uint32 SOSCCSR_LK(uint32 value) {
    return ((value << +chip::scg::Shift::SOSCCSR_LK) &
            +chip::scg::Mask::SOSCCSR_LK);
  }
 
  static inline constexpr uint32 SOSCCSR_SOSCVLD(uint32 value) {
    return ((value << +chip::scg::Shift::SOSCCSR_SOSCVLD) &
            +chip::scg::Mask::SOSCCSR_SOSCVLD);
  }
 
  static inline constexpr uint32 SOSCCSR_SOSCSEL(uint32 value) {
    return ((value << +chip::scg::Shift::SOSCCSR_SOSCSEL) &
            +chip::scg::Mask::SOSCCSR_SOSCSEL);
  }
 
  static inline constexpr uint32 SOSCCSR_SOSCERR(uint32 value) {
    return ((value << +chip::scg::Shift::SOSCCSR_SOSCERR) &
            +chip::scg::Mask::SOSCCSR_SOSCERR);
  }
 
  static inline constexpr uint32 SOSCCSR_SOSCVLD_IE(uint32 value) {
    return ((value << +chip::scg::Shift::SOSCCSR_SOSCVLD_IE) &
            +chip::scg::Mask::SOSCCSR_SOSCVLD_IE);
  }
 
  static inline constexpr uint32 SOSCCFG_EREFS(uint32 value) {
    return ((value << +chip::scg::Shift::SOSCCFG_EREFS) &
            +chip::scg::Mask::SOSCCFG_EREFS);
  }
 
  static inline constexpr uint32 SOSCCFG_RANGE(uint32 value) {
    return ((value << +chip::scg::Shift::SOSCCFG_RANGE) &
            +chip::scg::Mask::SOSCCFG_RANGE);
  }
 
  static inline constexpr uint32 SIRCCSR_SIRCSTEN(uint32 value) {
    return ((value << +chip::scg::Shift::SIRCCSR_SIRCSTEN) &
            +chip::scg::Mask::SIRCCSR_SIRCSTEN);
  }
 
  static inline constexpr uint32 SIRCCSR_SIRC_CLK_PERIPH_EN(uint32 value) {
    return ((value << +chip::scg::Shift::SIRCCSR_SIRC_CLK_PERIPH_EN) &
            +chip::scg::Mask::SIRCCSR_SIRC_CLK_PERIPH_EN);
  }
 
  static inline constexpr uint32 SIRCCSR_SIRCTREN(uint32 value) {
    return ((value << +chip::scg::Shift::SIRCCSR_SIRCTREN) &
            +chip::scg::Mask::SIRCCSR_SIRCTREN);
  }
 
  static inline constexpr uint32 SIRCCSR_SIRCTRUP(uint32 value) {
    return ((value << +chip::scg::Shift::SIRCCSR_SIRCTRUP) &
            +chip::scg::Mask::SIRCCSR_SIRCTRUP);
  }
 
  static inline constexpr uint32 SIRCCSR_TRIM_LOCK(uint32 value) {
    return ((value << +chip::scg::Shift::SIRCCSR_TRIM_LOCK) &
            +chip::scg::Mask::SIRCCSR_TRIM_LOCK);
  }
 
  static inline constexpr uint32 SIRCCSR_COARSE_TRIM_BYPASS(uint32 value) {
    return ((value << +chip::scg::Shift::SIRCCSR_COARSE_TRIM_BYPASS) &
            +chip::scg::Mask::SIRCCSR_COARSE_TRIM_BYPASS);
  }
 
  static inline constexpr uint32 SIRCCSR_LK(uint32 value) {
    return ((value << +chip::scg::Shift::SIRCCSR_LK) &
            +chip::scg::Mask::SIRCCSR_LK);
  }
 
  static inline constexpr uint32 SIRCCSR_SIRCVLD(uint32 value) {
    return ((value << +chip::scg::Shift::SIRCCSR_SIRCVLD) &
            +chip::scg::Mask::SIRCCSR_SIRCVLD);
  }
 
  static inline constexpr uint32 SIRCCSR_SIRCSEL(uint32 value) {
    return ((value << +chip::scg::Shift::SIRCCSR_SIRCSEL) &
            +chip::scg::Mask::SIRCCSR_SIRCSEL);
  }
 
  static inline constexpr uint32 SIRCCSR_SIRCERR(uint32 value) {
    return ((value << +chip::scg::Shift::SIRCCSR_SIRCERR) &
            +chip::scg::Mask::SIRCCSR_SIRCERR);
  }
 
  static inline constexpr uint32 SIRCCSR_SIRCERR_IE(uint32 value) {
    return ((value << +chip::scg::Shift::SIRCCSR_SIRCERR_IE) &
            +chip::scg::Mask::SIRCCSR_SIRCERR_IE);
  }
 
  static inline constexpr uint32 SIRCTCFG_TRIMSRC(uint32 value) {
    return ((value << +chip::scg::Shift::SIRCTCFG_TRIMSRC) &
            +chip::scg::Mask::SIRCTCFG_TRIMSRC);
  }
 
  static inline constexpr uint32 SIRCTCFG_TRIMDIV(uint32 value) {
    return ((value << +chip::scg::Shift::SIRCTCFG_TRIMDIV) &
            +chip::scg::Mask::SIRCTCFG_TRIMDIV);
  }
 
  static inline constexpr uint32 SIRCTRIM_CCOTRIM(uint32 value) {
    return ((value << +chip::scg::Shift::SIRCTRIM_CCOTRIM) &
            +chip::scg::Mask::SIRCTRIM_CCOTRIM);
  }
 
  static inline constexpr uint32 SIRCTRIM_CLTRIM(uint32 value) {
    return ((value << +chip::scg::Shift::SIRCTRIM_CLTRIM) &
            +chip::scg::Mask::SIRCTRIM_CLTRIM);
  }
 
  static inline constexpr uint32 SIRCTRIM_TCTRIM(uint32 value) {
    return ((value << +chip::scg::Shift::SIRCTRIM_TCTRIM) &
            +chip::scg::Mask::SIRCTRIM_TCTRIM);
  }
 
  static inline constexpr uint32 SIRCTRIM_FVCHTRIM(uint32 value) {
    return ((value << +chip::scg::Shift::SIRCTRIM_FVCHTRIM) &
            +chip::scg::Mask::SIRCTRIM_FVCHTRIM);
  }
 
  static inline constexpr uint32 SIRCSTAT_CCOTRIM(uint32 value) {
    return ((value << +chip::scg::Shift::SIRCSTAT_CCOTRIM) &
            +chip::scg::Mask::SIRCSTAT_CCOTRIM);
  }
 
  static inline constexpr uint32 SIRCSTAT_CLTRIM(uint32 value) {
    return ((value << +chip::scg::Shift::SIRCSTAT_CLTRIM) &
            +chip::scg::Mask::SIRCSTAT_CLTRIM);
  }
 
  static inline constexpr uint32 FIRCCSR_FIRCEN(uint32 value) {
    return ((value << +chip::scg::Shift::FIRCCSR_FIRCEN) &
            +chip::scg::Mask::FIRCCSR_FIRCEN);
  }
 
  static inline constexpr uint32 FIRCCSR_FIRCSTEN(uint32 value) {
    return ((value << +chip::scg::Shift::FIRCCSR_FIRCSTEN) &
            +chip::scg::Mask::FIRCCSR_FIRCSTEN);
  }
 
  static inline constexpr uint32 FIRCCSR_FIRC_SCLK_PERIPH_EN(uint32 value) {
    return ((value << +chip::scg::Shift::FIRCCSR_FIRC_SCLK_PERIPH_EN) &
            +chip::scg::Mask::FIRCCSR_FIRC_SCLK_PERIPH_EN);
  }
 
  static inline constexpr uint32 FIRCCSR_FIRC_FCLK_PERIPH_EN(uint32 value) {
    return ((value << +chip::scg::Shift::FIRCCSR_FIRC_FCLK_PERIPH_EN) &
            +chip::scg::Mask::FIRCCSR_FIRC_FCLK_PERIPH_EN);
  }
 
  static inline constexpr uint32 FIRCCSR_FIRCTREN(uint32 value) {
    return ((value << +chip::scg::Shift::FIRCCSR_FIRCTREN) &
            +chip::scg::Mask::FIRCCSR_FIRCTREN);
  }
 
  static inline constexpr uint32 FIRCCSR_FIRCTRUP(uint32 value) {
    return ((value << +chip::scg::Shift::FIRCCSR_FIRCTRUP) &
            +chip::scg::Mask::FIRCCSR_FIRCTRUP);
  }
 
  static inline constexpr uint32 FIRCCSR_TRIM_LOCK(uint32 value) {
    return ((value << +chip::scg::Shift::FIRCCSR_TRIM_LOCK) &
            +chip::scg::Mask::FIRCCSR_TRIM_LOCK);
  }
 
  static inline constexpr uint32 FIRCCSR_COARSE_TRIM_BYPASS(uint32 value) {
    return ((value << +chip::scg::Shift::FIRCCSR_COARSE_TRIM_BYPASS) &
            +chip::scg::Mask::FIRCCSR_COARSE_TRIM_BYPASS);
  }
 
  static inline constexpr uint32 FIRCCSR_LK(uint32 value) {
    return ((value << +chip::scg::Shift::FIRCCSR_LK) &
            +chip::scg::Mask::FIRCCSR_LK);
  }
 
  static inline constexpr uint32 FIRCCSR_FIRCVLD(uint32 value) {
    return ((value << +chip::scg::Shift::FIRCCSR_FIRCVLD) &
            +chip::scg::Mask::FIRCCSR_FIRCVLD);
  }
 
  static inline constexpr uint32 FIRCCSR_FIRCSEL(uint32 value) {
    return ((value << +chip::scg::Shift::FIRCCSR_FIRCSEL) &
            +chip::scg::Mask::FIRCCSR_FIRCSEL);
  }
 
  static inline constexpr uint32 FIRCCSR_FIRCERR(uint32 value) {
    return ((value << +chip::scg::Shift::FIRCCSR_FIRCERR) &
            +chip::scg::Mask::FIRCCSR_FIRCERR);
  }
 
  static inline constexpr uint32 FIRCCSR_FIRCERR_IE(uint32 value) {
    return ((value << +chip::scg::Shift::FIRCCSR_FIRCERR_IE) &
            +chip::scg::Mask::FIRCCSR_FIRCERR_IE);
  }
 
  static inline constexpr uint32 FIRCCSR_FIRCACC_IE(uint32 value) {
    return ((value << +chip::scg::Shift::FIRCCSR_FIRCACC_IE) &
            +chip::scg::Mask::FIRCCSR_FIRCACC_IE);
  }
 
  static inline constexpr uint32 FIRCCSR_FIRCACC(uint32 value) {
    return ((value << +chip::scg::Shift::FIRCCSR_FIRCACC) &
            +chip::scg::Mask::FIRCCSR_FIRCACC);
  }
 
  static inline constexpr uint32 FIRCCFG_FREQ_SEL(uint32 value) {
    return ((value << +chip::scg::Shift::FIRCCFG_FREQ_SEL) &
            +chip::scg::Mask::FIRCCFG_FREQ_SEL);
  }
 
  static inline constexpr uint32 FIRCTCFG_TRIMSRC(uint32 value) {
    return ((value << +chip::scg::Shift::FIRCTCFG_TRIMSRC) &
            +chip::scg::Mask::FIRCTCFG_TRIMSRC);
  }
 
  static inline constexpr uint32 FIRCTCFG_TRIMDIV(uint32 value) {
    return ((value << +chip::scg::Shift::FIRCTCFG_TRIMDIV) &
            +chip::scg::Mask::FIRCTCFG_TRIMDIV);
  }
 
  static inline constexpr uint32 FIRCTRIM_TRIMFINE(uint32 value) {
    return ((value << +chip::scg::Shift::FIRCTRIM_TRIMFINE) &
            +chip::scg::Mask::FIRCTRIM_TRIMFINE);
  }
 
  static inline constexpr uint32 FIRCTRIM_TRIMCOAR(uint32 value) {
    return ((value << +chip::scg::Shift::FIRCTRIM_TRIMCOAR) &
            +chip::scg::Mask::FIRCTRIM_TRIMCOAR);
  }
 
  static inline constexpr uint32 FIRCTRIM_TRIMTEMP2(uint32 value) {
    return ((value << +chip::scg::Shift::FIRCTRIM_TRIMTEMP2) &
            +chip::scg::Mask::FIRCTRIM_TRIMTEMP2);
  }
 
  static inline constexpr uint32 FIRCTRIM_TRIMSTART(uint32 value) {
    return ((value << +chip::scg::Shift::FIRCTRIM_TRIMSTART) &
            +chip::scg::Mask::FIRCTRIM_TRIMSTART);
  }
 
  static inline constexpr uint32 FIRCSTAT_TRIMFINE(uint32 value) {
    return ((value << +chip::scg::Shift::FIRCSTAT_TRIMFINE) &
            +chip::scg::Mask::FIRCSTAT_TRIMFINE);
  }
 
  static inline constexpr uint32 FIRCSTAT_TRIMCOAR(uint32 value) {
    return ((value << +chip::scg::Shift::FIRCSTAT_TRIMCOAR) &
            +chip::scg::Mask::FIRCSTAT_TRIMCOAR);
  }
 
  static inline constexpr uint32 FIRCATC1_IDEALC(uint32 value) {
    return ((value << +chip::scg::Shift::FIRCATC1_IDEALC) &
            +chip::scg::Mask::FIRCATC1_IDEALC);
  }
 
  static inline constexpr uint32 FIRCATC2_COARMINC(uint32 value) {
    return ((value << +chip::scg::Shift::FIRCATC2_COARMINC) &
            +chip::scg::Mask::FIRCATC2_COARMINC);
  }
 
  static inline constexpr uint32 FIRCATC2_COARMAXC(uint32 value) {
    return ((value << +chip::scg::Shift::FIRCATC2_COARMAXC) &
            +chip::scg::Mask::FIRCATC2_COARMAXC);
  }
 
  static inline constexpr uint32 FIRCATC3_FINEMINC(uint32 value) {
    return ((value << +chip::scg::Shift::FIRCATC3_FINEMINC) &
            +chip::scg::Mask::FIRCATC3_FINEMINC);
  }
 
  static inline constexpr uint32 FIRCATC3_FINEMAXC(uint32 value) {
    return ((value << +chip::scg::Shift::FIRCATC3_FINEMAXC) &
            +chip::scg::Mask::FIRCATC3_FINEMAXC);
  }
 
  static inline constexpr uint32 ROSCCSR_LK(uint32 value) {
    return ((value << +chip::scg::Shift::ROSCCSR_LK) &
            +chip::scg::Mask::ROSCCSR_LK);
  }
 
  static inline constexpr uint32 ROSCCSR_ROSCVLD(uint32 value) {
    return ((value << +chip::scg::Shift::ROSCCSR_ROSCVLD) &
            +chip::scg::Mask::ROSCCSR_ROSCVLD);
  }
 
  static inline constexpr uint32 ROSCCSR_ROSCSEL(uint32 value) {
    return ((value << +chip::scg::Shift::ROSCCSR_ROSCSEL) &
            +chip::scg::Mask::ROSCCSR_ROSCSEL);
  }
 
  static inline constexpr uint32 ROSCCSR_ROSCERR(uint32 value) {
    return ((value << +chip::scg::Shift::ROSCCSR_ROSCERR) &
            +chip::scg::Mask::ROSCCSR_ROSCERR);
  }
};
 
/* ***************************************************************************************
 * End of file
 */
 
#endif /* CHIP_68FC7893_16D3_44E3_955F_6A00759AB5C9 */