chip::scg 命名空間(Namespace)參考文件

複合項目
struct	Register
class	SCG

列舉型態
enum struct	Mask : unsigned int {   VERID_VERSION = 0xFFFFFFFFU , PARAM_SOSCCLKPRES = 0x00000002U , PARAM_SIRCCLKPRES = 0x00000004U , PARAM_FIRCCLKPRES = 0x00000008U ,   PARAM_ROSCCLKPRES = 0x00000010U , TRIM_LOCK_TRIM_UNLOCK = 0x00000001U , TRIM_LOCK_IFR_DISABLE = 0x00000002U , TRIM_LOCK_TRIM_LOCK_KEY = 0xFFFF0000U ,   CSR_SCS = 0x07000000U , RCCR_SCS = 0x07000000U , SOSCCSR_SOSCEN = 0x00000001U , SOSCCSR_SOSCSTEN = 0x00000002U ,   SOSCCSR_SOSCCM = 0x00010000U , SOSCCSR_SOSCCMRE = 0x00020000U , SOSCCSR_LK = 0x00800000U , SOSCCSR_SOSCVLD = 0x01000000U ,   SOSCCSR_SOSCSEL = 0x02000000U , SOSCCSR_SOSCERR = 0x04000000U , SOSCCSR_SOSCVLD_IE = 0x40000000U , SOSCCFG_EREFS = 0x00000004U ,   SOSCCFG_RANGE = 0x00000030U , SIRCCSR_SIRCSTEN = 0x00000002U , SIRCCSR_SIRC_CLK_PERIPH_EN = 0x00000020U , SIRCCSR_SIRCTREN = 0x00000100U ,   SIRCCSR_SIRCTRUP = 0x00000200U , SIRCCSR_TRIM_LOCK = 0x00000400U , SIRCCSR_COARSE_TRIM_BYPASS = 0x00000800U , SIRCCSR_LK = 0x0800000U ,   SIRCCSR_SIRCVLD = 0x01000000U , SIRCCSR_SIRCSEL = 0x02000000U , SIRCCSR_SIRCERR = 0x04000000U , SIRCCSR_SIRCERR_IE = 0x08000000U ,   SIRCTCFG_TRIMSRC = 0x00000003U , SIRCTCFG_TRIMDIV = 0x007F0000U , SIRCTRIM_CCOTRIM = 0x0000003FU , SIRCTRIM_CLTRIM = 0x00003F00U ,   SIRCTRIM_TCTRIM = 0x001F0000U , SIRCTRIM_FVCHTRIM = 0x1F000000U , SIRCSTAT_CCOTRIM = 0x00000003FU , SIRCSTAT_CLTRIM = 0x00003F00U ,   FIRCCSR_FIRCEN = 0x00000001U , FIRCCSR_FIRCSTEN = 0x00000002U , FIRCCSR_FIRC_SCLK_PERIPH_EN = 0x00000010U , FIRCCSR_FIRC_FCLK_PERIPH_EN = 0x00000020U ,   FIRCCSR_FIRCTREN = 0x00000100U , FIRCCSR_FIRCTRUP = 0x00000200U , FIRCCSR_TRIM_LOCK = 0x00000400U , FIRCCSR_COARSE_TRIM_BYPASS = 0x00000800U ,   FIRCCSR_LK = 0x00800000U , FIRCCSR_FIRCVLD = 0x01000000U , FIRCCSR_FIRCSEL = 0x02000000U , FIRCCSR_FIRCERR = 0x04000000U ,   FIRCCSR_FIRCERR_IE = 0x08000000U , FIRCCSR_FIRCACC_IE = 0x40000000U , FIRCCSR_FIRCACC = 0x80000000U , FIRCCFG_FREQ_SEL = 0x0000000EU ,   FIRCTCFG_TRIMSRC = 0x00000003U , FIRCTCFG_TRIMDIV = 0x07F00000U , FIRCTRIM_TRIMFINE = 0x000000FFU , FIRCTRIM_TRIMCOAR = 0x00003F00U ,   FIRCTRIM_TRIMTEMP2 = 0x000C0000U , FIRCTRIM_TRIMSTART = 0x3F000000U , FIRCSTAT_TRIMFINE = 0x000000FFU , FIRCSTAT_TRIMCOAR = 0x00003F00U ,   FIRCATC1_IDEALC = 0x0000FFFFU , FIRCATC2_COARMINC = 0x0000FFFFU , FIRCATC2_COARMAXC = 0xFFFF0000U , FIRCATC3_FINEMINC = 0x0000FFFFU ,   FIRCATC3_FINEMAXC = 0xFFFF0000U , ROSCCSR_LK = 0x00800000U , ROSCCSR_ROSCVLD = 0x01000000U , ROSCCSR_ROSCSEL = 0x02000000U ,   ROSCCSR_ROSCERR = 0x04000000U }
enum struct	Shift : unsigned int {   VERID_VERSION = 0U , PARAM_SOSCCLKPRES = 1U , PARAM_SIRCCLKPRES = 2U , PARAM_FIRCCLKPRES = 3U ,   PARAM_ROSCCLKPRES = 4U , TRIM_LOCK_TRIM_UNLOCK = 0U , TRIM_LOCK_IFR_DISABLE = 1U , TRIM_LOCK_TRIM_LOCK_KEY = 16U ,   CSR_SCS = 24U , RCCR_SCS = 24U , SOSCCSR_SOSCEN = 0U , SOSCCSR_SOSCSTEN = 1U ,   SOSCCSR_SOSCCM = 16U , SOSCCSR_SOSCCMRE = 17U , SOSCCSR_LK = 23U , SOSCCSR_SOSCVLD = 24U ,   SOSCCSR_SOSCSEL = 25U , SOSCCSR_SOSCERR = 26U , SOSCCSR_SOSCVLD_IE = 30U , SOSCCFG_EREFS = 2U ,   SOSCCFG_RANGE = 4U , SIRCCSR_SIRCSTEN = 1U , SIRCCSR_SIRC_CLK_PERIPH_EN = 5U , SIRCCSR_SIRCTREN = 8U ,   SIRCCSR_SIRCTRUP = 9U , SIRCCSR_TRIM_LOCK = 10U , SIRCCSR_COARSE_TRIM_BYPASS = 11U , SIRCCSR_LK = 23U ,   SIRCCSR_SIRCVLD = 24U , SIRCCSR_SIRCSEL = 25U , SIRCCSR_SIRCERR = 26U , SIRCCSR_SIRCERR_IE = 27U ,   SIRCTCFG_TRIMSRC = 0U , SIRCTCFG_TRIMDIV = 16U , SIRCTRIM_CCOTRIM = 0U , SIRCTRIM_CLTRIM = 8U ,   SIRCTRIM_TCTRIM = 16U , SIRCTRIM_FVCHTRIM = 24U , SIRCSTAT_CCOTRIM = 0U , SIRCSTAT_CLTRIM = 8U ,   FIRCCSR_FIRCEN = 0U , FIRCCSR_FIRCSTEN = 1U , FIRCCSR_FIRC_SCLK_PERIPH_EN = 4U , FIRCCSR_FIRC_FCLK_PERIPH_EN = 5U ,   FIRCCSR_FIRCTREN = 8U , FIRCCSR_FIRCTRUP = 9U , FIRCCSR_TRIM_LOCK = 10U , FIRCCSR_COARSE_TRIM_BYPASS = 11U ,   FIRCCSR_LK = 23U , FIRCCSR_FIRCVLD = 24U , FIRCCSR_FIRCSEL = 25U , FIRCCSR_FIRCERR = 26U ,   FIRCCSR_FIRCERR_IE = 27U , FIRCCSR_FIRCACC_IE = 30U , FIRCCSR_FIRCACC = 31U , FIRCCFG_FREQ_SEL = 1U ,   FIRCTCFG_TRIMSRC = 0U , FIRCTCFG_TRIMDIV = 16U , FIRCTRIM_TRIMFINE = 0U , FIRCTRIM_TRIMCOAR = 8U ,   FIRCTRIM_TRIMTEMP2 = 18U , FIRCTRIM_TRIMSTART = 24U , FIRCSTAT_TRIMFINE = 0U , FIRCSTAT_TRIMCOAR = 8U ,   FIRCATC1_IDEALC = 0U , FIRCATC2_COARMINC = 0U , FIRCATC2_COARMAXC = 16U , FIRCATC3_FINEMINC = 0U ,   FIRCATC3_FINEMAXC = 16U , ROSCCSR_LK = 23U , ROSCCSR_ROSCVLD = 24U , ROSCCSR_ROSCSEL = 25U ,   ROSCCSR_ROSCERR = 26U }

函式
constexpr unsigned int	operator+ (Mask e)
constexpr unsigned int	operator+ (Shift e)

變數
Register &	SCG0

詳細描述

Copyright (c) 2020 ZxyKira All rights reserved.

SPDX-License-Identifier: MIT

列舉型態說明文件

Mask

enum struct chip::scg::Mask : unsigned int

strong

列舉值
VERID_VERSION	VERID - VERSION. Version ID Register - SCG Version Number
PARAM_SOSCCLKPRES	PARAM - SOSCCLKPRES. Parameter Register - SOSC Clock Present [0b1]SOSC clock source is present [0b0]SOSC clock source is not present
PARAM_SIRCCLKPRES	PARAM - SIRCCLKPRES. Parameter Register - SIRC Clock Present [0b1]SIRC clock source is present [0b0]SIRC clock source is not present
PARAM_FIRCCLKPRES	PARAM - FIRCCLKPRES. Parameter Register - FIRC Clock Present [0b1]FIRC clock source is present [0b0]FIRC clock source is not present
PARAM_ROSCCLKPRES	PARAM - ROSCCLKPRES. Parameter Register - ROSC Clock Present [0b1]ROSC clock source is present [0b0]ROSC clock source is not present
TRIM_LOCK_TRIM_UNLOCK	PARAM - TRIM_UNLOCK. Parameter Register - TRIM_UNLOCK [0b0]SCG Trim Registers locked and not writable. [0b1]SCG Trim registers unlocked and writable.
TRIM_LOCK_IFR_DISABLE	TRIM_LOCK - IFR_DISABLE. Trim Lock register - IFR_DISABLE [0b0]IFR write access to SCG trim registers not disabled. The SCG Trim registers are reprogrammed with the IFR values after any system reset. [0b1]IFR write access to SCG trim registers during system reset is blocked.
TRIM_LOCK_TRIM_LOCK_KEY	TRIM_LOCK - TRIM_LOCK_KEY. Trim Lock register - TRIM_LOCK_KEY
CSR_SCS	SCS. System Clock Source [0b000]Reserved [0b001]SOSC [0b010]SIRC [0b011]FIRC [0b100]ROSC [0b101-0b111]Reserved
RCCR_SCS	CSR - SCS. Clock Status Register - System Clock Source [0b000]Reserved [0b001]SOSC [0b010]SIRC [0b011]FIRC [0b100]ROSC [0b101-0b111]Reserved
SOSCCSR_SOSCEN	RCCR - SOSCEN. Run Clock Control Register - SOSC Enable [0b0]SOSC is disabled [0b1]SOSC is enabled
SOSCCSR_SOSCSTEN	SOSCCSR - SOSCSTEN. SOSC Control Status Register - SOSC Stop Enable [0b0]SOSC is disabled in Deep Sleep mode [0b1]SOSC is enabled in Deep Sleep mode only if SOSCEN is set
SOSCCSR_SOSCCM	SOSCCSR - SOSCCM. SOSC Control Status Register - SOSC Clock Monitor Enable [0b0]SOSC Clock Monitor is disabled [0b1]SOSC Clock Monitor is enabled
SOSCCSR_SOSCCMRE	SOSCCSR - SOSCCMRE. SOSC Control Status Register - SOSC Clock Monitor Reset Enable [0b0]Clock monitor generates an interrupt when an error is detected [0b1]Clock monitor generates a reset when an error is detected
SOSCCSR_LK	SOSCCSR - LK. SOSC Control Status Register - Lock Register [0b0]This Control Status Register can be written [0b1]This Control Status Register cannot be written
SOSCCSR_SOSCVLD	SOSCVLD. SOSC Control Status Register - SOSC Valid [0b0]SOSC is not enabled or clock is not valid [0b1]SOSC is enabled and output clock is valid
SOSCCSR_SOSCSEL	SOSCCSR - SOSCSEL. SOSC Control Status Register - SOSC Selected [0b0]SOSC is not the system clock source [0b1]SOSC is the system clock source
SOSCCSR_SOSCERR	SOSCCSR - SOSCERR. SOSC Control Status Register - SOSC Clock Error -[0b0]SOSC Clock Monitor is disabled or has not detected an error -[0b1]SOSC Clock Monitor is enabled and detected an error
SOSCCSR_SOSCVLD_IE	SOSCCSR - SOSCVLD_IE. SOSC Control Status Register - SOSC Valid Interrupt Enable [0b0]SOSCVLD interrupt is not enabled [0b1]SOSCVLD interrupt is enabled
SOSCCFG_EREFS	SOSCCFG - EREFS. SOSC Configuration Register - External Reference Select [0b0]External reference clock selected. [0b1]Internal crystal oscillator of OSC selected.
SOSCCFG_RANGE	SOSCCFG - RANGE. SOSC Configuration Register - SOSC Range Select [0b00]Frequency range select of 8-16 MHz. [0b01]Frequency range select of 16-25 MHz. [0b10]Frequency range select of 25-40 MHz. [0b11]Frequency range select of 40-50 MHz.
SIRCCSR_SIRCSTEN	SIRCCSR - SIRCSTEN. SIRC Control Status Register - SIRC Stop Enable [0b0]SIRC is disabled in Deep Sleep mode [0b1]SIRC is enabled in Deep Sleep mode
SIRCCSR_SIRC_CLK_PERIPH_EN	SIRCCSR - SIRC_CLK_PERIPH_EN. SIRC Control Status Register - SIRC Clock to Peripherals Enable [0b0]SIRC clock to peripherals is disabled [0b1]SIRC clock to peripherals is enabled
SIRCCSR_SIRCTREN	SIRCCSR - SIRCTREN. SIRC Control Status Register - SIRC 12 MHz Trim Enable (SIRCCFG[RANGE]=1) [0b0]Disables trimming SIRC to an external clock source [0b1]Enables trimming SIRC to an external clock source
SIRCCSR_SIRCTRUP	SIRCTRUP. SIRC Control Status Register - SIRC Trim Update [0b0]Disables SIRC trimming updates [0b1]Enables SIRC trimming updates
SIRCCSR_TRIM_LOCK	SIRCCSR - TRIM_LOCK. SIRC Control Status Register - SIRC TRIM LOCK [0b0]SIRC auto trim not locked to target frequency range [0b1]SIRC auto trim locked to target frequency range
SIRCCSR_COARSE_TRIM_BYPASS	SIRCCSR - COARSE_TRIM_BYPASS. SIRC Control Status Register - Coarse Auto Trim Bypass [0b0]SIRC Coarse Auto Trim NOT Bypassed [0b1]SIRC Coarse Auto Trim Bypassed
SIRCCSR_LK	SIRCCSR - LK. SIRC Control Status Register - Lock Register [0b0]Control Status Register can be written [0b1]Control Status Register cannot be written
SIRCCSR_SIRCVLD	SIRCCSR - SIRCVLD. SIRC Control Status Register - SIRC Valid [0b0]SIRC is not enabled or clock is not valid [0b1]SIRC is enabled and output clock is valid
SIRCCSR_SIRCSEL	SIRCCSR - SIRCSEL. SIRC Control Status Register - SIRC Selected [0b0]SIRC is not the system clock source [0b1]SIRC is the system clock source
SIRCCSR_SIRCERR	SIRCCSR - SIRCERR. SIRC Control Status Register - SIRC Clock Error [0b0]Error not detected with the SIRC trimming [0b1]Error detected with the SIRC trimming
SIRCCSR_SIRCERR_IE	SIRCCSR - SIRCERR_IE. SIRC Control Status Register - SIRC Clock Error Interrupt Enable [0b0]SIRCERR interrupt is not enabled [0b1]SIRCERR interrupt is enabled
SIRCTCFG_TRIMSRC	SIRCTCFG - TRIMSRC. SIRC Trim Configuration Register - Trim Source [0b00]Reserved [0b01]Reserved [0b10]SOSC. This option requires that SOSC be divided using the TRIMDIV field to get a frequency of 1 MHz. [0b11]Reserved
SIRCTCFG_TRIMDIV	SIRCTCFG - TRIMDIV. SIRC Trim Configuration Register - SIRC Trim Pre-divider
SIRCTRIM_CCOTRIM	SIRCTRIM - CCOTRIM. SIRC Trim Register - CCO Trim
SIRCTRIM_CLTRIM	SIRCTRIM - CLTRIM. SIRC Trim Register - CL Trim
SIRCTRIM_TCTRIM	SIRCTRIM - TCTRIM. SIRC Trim Register - Trim Temp
SIRCTRIM_FVCHTRIM	SIRCTRIM - FVCHTRIM. SIRC Trim Register
SIRCSTAT_CCOTRIM	SIRCSTAT - CCOTRIM. SIRC Trim Register - CCO Trim
SIRCSTAT_CLTRIM	SIRCSTAT - CLTRIM. SIRC Auto-trimming Status Register - CL Trim
FIRCCSR_FIRCEN	FIRCEN. SIRC Auto-trimming Status Register - FIRC Enable [0b0]FIRC is disabled [0b1]FIRC is enabled
FIRCCSR_FIRCSTEN	FIRCCSR - FIRCSTEN. FIRC Control Status Register - FIRC Stop Enable [0b0]FIRC is disabled in Deep Sleep mode [0b1]FIRC is enabled in Deep Sleep mode
FIRCCSR_FIRC_SCLK_PERIPH_EN	FIRCCSR - FIRC_SCLK_PERIPH_EN. FIRC Control Status Register - FIRC 48 MHz Clock to peripherals Enable [0b0]FIRC 48 MHz to peripherals is disabled [0b1]FIRC 48 MHz to peripherals is enabled
FIRCCSR_FIRC_FCLK_PERIPH_EN	FIRCCSR - FIRC_FCLK_PERIPH_EN. FIRC Control Status Register - FRO_HF Clock to peripherals Enable [0b0]FRO_HF to peripherals is disabled [0b1]FRO_HF to peripherals is enabled
FIRCCSR_FIRCTREN	FIRCCSR - FIRCTREN. FIRC Control Status Register - FRO_HF Trim Enable [0b0]Disables trimming FRO_HF by an external clock source [0b1]Enables trimming FRO_HF by an external clock source
FIRCCSR_FIRCTRUP	FIRCCSR - FIRCTRUP. FIRC Control Status Register - FIRC Trim Update [0b0]Disables FIRC trimming updates [0b1]Enables FIRC trimming updates
FIRCCSR_TRIM_LOCK	FIRCCSR - TRIM_LOCK. FIRC Control Status Register - FIRC TRIM LOCK [0b0]FIRC auto trim not locked to target frequency range [0b1]FIRC auto trim locked to target frequency range
FIRCCSR_COARSE_TRIM_BYPASS	FIRCCSR - COARSE_TRIM_BYPASS. FIRC Control Status Register - Coarse Auto Trim Bypass [0b0]FIRC Coarse Auto Trim NOT Bypassed [0b1]FIRC Coarse Auto Trim Bypassed
FIRCCSR_LK	FIRCCSR - LK. FIRC Control Status Register - Lock Register [0b0]Control Status Register can be written [0b1]Control Status Register cannot be written
FIRCCSR_FIRCVLD	FIRCCSR - FIRCVLD. FIRC Control Status Register - FIRC Valid status [0b0]FIRC is not enabled or clock is not valid. [0b1]FIRC is enabled and output clock is valid. The clock is valid after there is an output clock from the FIRC analog.
FIRCCSR_FIRCSEL	FIRCCSR - FIRCSEL. FIRC Control Status Register - FIRC Selected [0b0]FIRC is not the system clock source [0b1]FIRC is the system clock source
FIRCCSR_FIRCERR	FIRCCSR - FIRCERR. FIRC Control Status Register - FIRC Clock Error [0b0]Error not detected with the FIRC trimming [0b1]Error detected with the FIRC trimming
FIRCCSR_FIRCERR_IE	FIRCCSR - FIRCERR_IE. FIRC Control Status Register - FIRC Clock Error Interrupt Enable [0b0]FIRCERR interrupt is not enabled [0b1]FIRCERR interrupt is enabled
FIRCCSR_FIRCACC_IE	FIRCCSR - FIRCACC_IE. FIRC Control Status Register - FIRC Accurate Interrupt Enable [0b0]FIRCACC interrupt is not enabled [0b1]FIRCACC interrupt is enabled
FIRCCSR_FIRCACC	FIRCCSR - FIRCACC. FIRC Control Status Register - FIRC Frequency Accurate -[0b0]FIRC is not enabled or clock is not accurate. -[0b1]FIRC is enabled and output clock is accurate after some preparation time which is obtained by counting FRO_HF clock.
FIRCCFG_FREQ_SEL	FIRCCFG - FREQ_SEL. FIRC Configuration Register - Frequency select [0b111]192 MHz FIRC clock selected [0b101]96 MHz FIRC clock selected [0b011]64 MHz FIRC clock selected [0b001]48 MHz FIRC clock selected, divided from 192 MHz
FIRCTCFG_TRIMSRC	FIRCCFG - TRIMSRC. FIRC Configuration Register - Trim Source [0b00]USB0 Start of Frame (1 KHz). This option does not use TRIMDIV . [0b01]Reserved [0b10]SOSC. This option requires that SOSC be divided using the TRIMDIV field to get a frequency of 1 MHz. [0b11]Reserved
FIRCTCFG_TRIMDIV	FIRCCFG - TRIMDIV. FIRC Configuration Register - FIRC Trim Pre-divider
FIRCTRIM_TRIMFINE	FIRCTRIM - TRIMFINE. FIRC Trim Register - Trim Fine
FIRCTRIM_TRIMCOAR	FIRCTRIM - TRIMCOAR. FIRC Trim Register - Trim Coarse
FIRCTRIM_TRIMTEMP2	FIRCTRIM - TRIMTEMP2. FIRC Trim Register - Trim Temperature2
FIRCTRIM_TRIMSTART	FIRCTRIM - TRIMSTART. FIRC Trim Register - Trim Start
FIRCSTAT_TRIMFINE	FIRCSTAT - TRIMFINE. FIRC Auto-trimming Status Register - Trim Fine
FIRCSTAT_TRIMCOAR	FIRCSTAT - TRIMCOAR. FIRC Auto-trimming Status Register - Trim Coarse
FIRCATC1_IDEALC	FIRCATC1 - IDEALC. FIRC Auto-trimming Counter 1 - Ideal Counter
FIRCATC2_COARMINC	FIRCATC2 - COARMINC. FIRC Auto-trimming Counter 1 - Coarse Trim Minimum Counter
FIRCATC2_COARMAXC	FIRCATC2 - COARMAXC. FIRC Auto-trimming Counter 1 - Coarse Trim Maximum Counter
FIRCATC3_FINEMINC	FIRCATC3 - FINEMINC. FIRC Auto-trimming Counter 2 - Fine Trim Minimum Counter
FIRCATC3_FINEMAXC	FIRCATC3 - FINEMAXC. FIRC Auto-trimming Counter 2 - Fine Trim Maximum Counter
ROSCCSR_LK	ROSCCSR - LK. ROSC Control Status Register - Lock Register [0b0]Control Status Register can be written [0b1]Control Status Register cannot be written
ROSCCSR_ROSCVLD	ROSCCSR - ROSCVLD. ROSC Control Status Register - ROSC Valid [0b0]ROSC is not enabled or clock is not valid [0b1]ROSC is enabled and output clock is valid
ROSCCSR_ROSCSEL	ROSCCSR - ROSCSEL. ROSC Control Status Register - ROSC Selected [0b0]ROSC is not the system clock source [0b1]ROSC is the system clock source
ROSCCSR_ROSCERR	ROSCCSR - ROSCERR. ROSC Control Status Register - ROSC Clock Error [0b0]ROSC Clock has not detected an error [0b1]ROSC Clock has detected an error

Shift

enum struct chip::scg::Shift : unsigned int

strong

列舉值
VERID_VERSION	VERID - VERSION. Version ID Register - SCG Version Number
PARAM_SOSCCLKPRES	PARAM - SOSCCLKPRES. Parameter Register - SOSC Clock Present [0b1]SOSC clock source is present [0b0]SOSC clock source is not present
PARAM_SIRCCLKPRES	PARAM - SIRCCLKPRES. Parameter Register - SIRC Clock Present [0b1]SIRC clock source is present [0b0]SIRC clock source is not present
PARAM_FIRCCLKPRES	PARAM - FIRCCLKPRES. Parameter Register - FIRC Clock Present [0b1]FIRC clock source is present [0b0]FIRC clock source is not present
PARAM_ROSCCLKPRES	PARAM - ROSCCLKPRES. Parameter Register - ROSC Clock Present [0b1]ROSC clock source is present [0b0]ROSC clock source is not present
TRIM_LOCK_TRIM_UNLOCK	PARAM - TRIM_UNLOCK. Parameter Register - TRIM_UNLOCK [0b0]SCG Trim Registers locked and not writable. [0b1]SCG Trim registers unlocked and writable.
TRIM_LOCK_IFR_DISABLE	TRIM_LOCK - IFR_DISABLE. Trim Lock register - IFR_DISABLE [0b0]IFR write access to SCG trim registers not disabled. The SCG Trim registers are reprogrammed with the IFR values after any system reset. [0b1]IFR write access to SCG trim registers during system reset is blocked.
TRIM_LOCK_TRIM_LOCK_KEY	TRIM_LOCK - TRIM_LOCK_KEY. Trim Lock register - TRIM_LOCK_KEY
CSR_SCS	SCS. System Clock Source [0b000]Reserved [0b001]SOSC [0b010]SIRC [0b011]FIRC [0b100]ROSC [0b101-0b111]Reserved
RCCR_SCS	CSR - SCS. Clock Status Register - System Clock Source [0b000]Reserved [0b001]SOSC [0b010]SIRC [0b011]FIRC [0b100]ROSC [0b101-0b111]Reserved
SOSCCSR_SOSCEN	RCCR - SOSCEN. Run Clock Control Register - SOSC Enable [0b0]SOSC is disabled [0b1]SOSC is enabled
SOSCCSR_SOSCSTEN	SOSCCSR - SOSCSTEN. SOSC Control Status Register - SOSC Stop Enable [0b0]SOSC is disabled in Deep Sleep mode [0b1]SOSC is enabled in Deep Sleep mode only if SOSCEN is set
SOSCCSR_SOSCCM	SOSCCSR - SOSCCM. SOSC Control Status Register - SOSC Clock Monitor Enable [0b0]SOSC Clock Monitor is disabled [0b1]SOSC Clock Monitor is enabled
SOSCCSR_SOSCCMRE	SOSCCSR - SOSCCMRE. SOSC Control Status Register - SOSC Clock Monitor Reset Enable [0b0]Clock monitor generates an interrupt when an error is detected [0b1]Clock monitor generates a reset when an error is detected
SOSCCSR_LK	SOSCCSR - LK. SOSC Control Status Register - Lock Register [0b0]This Control Status Register can be written [0b1]This Control Status Register cannot be written
SOSCCSR_SOSCVLD	SOSCVLD. SOSC Control Status Register - SOSC Valid [0b0]SOSC is not enabled or clock is not valid [0b1]SOSC is enabled and output clock is valid
SOSCCSR_SOSCSEL	SOSCCSR - SOSCSEL. SOSC Control Status Register - SOSC Selected [0b0]SOSC is not the system clock source [0b1]SOSC is the system clock source
SOSCCSR_SOSCERR	SOSCCSR - SOSCERR. SOSC Control Status Register - SOSC Clock Error -[0b0]SOSC Clock Monitor is disabled or has not detected an error -[0b1]SOSC Clock Monitor is enabled and detected an error
SOSCCSR_SOSCVLD_IE	SOSCCSR - SOSCVLD_IE. SOSC Control Status Register - SOSC Valid Interrupt Enable [0b0]SOSCVLD interrupt is not enabled [0b1]SOSCVLD interrupt is enabled
SOSCCFG_EREFS	SOSCCFG - EREFS. SOSC Configuration Register - External Reference Select [0b0]External reference clock selected. [0b1]Internal crystal oscillator of OSC selected.
SOSCCFG_RANGE	SOSCCFG - RANGE. SOSC Configuration Register - SOSC Range Select [0b00]Frequency range select of 8-16 MHz. [0b01]Frequency range select of 16-25 MHz. [0b10]Frequency range select of 25-40 MHz. [0b11]Frequency range select of 40-50 MHz.
SIRCCSR_SIRCSTEN	SIRCCSR - SIRCSTEN. SIRC Control Status Register - SIRC Stop Enable [0b0]SIRC is disabled in Deep Sleep mode [0b1]SIRC is enabled in Deep Sleep mode
SIRCCSR_SIRC_CLK_PERIPH_EN	SIRCCSR - SIRC_CLK_PERIPH_EN. SIRC Control Status Register - SIRC Clock to Peripherals Enable [0b0]SIRC clock to peripherals is disabled [0b1]SIRC clock to peripherals is enabled
SIRCCSR_SIRCTREN	SIRCCSR - SIRCTREN. SIRC Control Status Register - SIRC 12 MHz Trim Enable (SIRCCFG[RANGE]=1) [0b0]Disables trimming SIRC to an external clock source [0b1]Enables trimming SIRC to an external clock source
SIRCCSR_SIRCTRUP	SIRCTRUP. SIRC Control Status Register - SIRC Trim Update [0b0]Disables SIRC trimming updates [0b1]Enables SIRC trimming updates
SIRCCSR_TRIM_LOCK	SIRCCSR - TRIM_LOCK. SIRC Control Status Register - SIRC TRIM LOCK [0b0]SIRC auto trim not locked to target frequency range [0b1]SIRC auto trim locked to target frequency range
SIRCCSR_COARSE_TRIM_BYPASS	SIRCCSR - COARSE_TRIM_BYPASS. SIRC Control Status Register - Coarse Auto Trim Bypass [0b0]SIRC Coarse Auto Trim NOT Bypassed [0b1]SIRC Coarse Auto Trim Bypassed
SIRCCSR_LK	SIRCCSR - LK. SIRC Control Status Register - Lock Register [0b0]Control Status Register can be written [0b1]Control Status Register cannot be written
SIRCCSR_SIRCVLD	SIRCCSR - SIRCVLD. SIRC Control Status Register - SIRC Valid [0b0]SIRC is not enabled or clock is not valid [0b1]SIRC is enabled and output clock is valid
SIRCCSR_SIRCSEL	SIRCCSR - SIRCSEL. SIRC Control Status Register - SIRC Selected [0b0]SIRC is not the system clock source [0b1]SIRC is the system clock source
SIRCCSR_SIRCERR	SIRCCSR - SIRCERR. SIRC Control Status Register - SIRC Clock Error [0b0]Error not detected with the SIRC trimming [0b1]Error detected with the SIRC trimming
SIRCCSR_SIRCERR_IE	SIRCCSR - SIRCERR_IE. SIRC Control Status Register - SIRC Clock Error Interrupt Enable [0b0]SIRCERR interrupt is not enabled [0b1]SIRCERR interrupt is enabled
SIRCTCFG_TRIMSRC	SIRCTCFG - TRIMSRC. SIRC Trim Configuration Register - Trim Source [0b00]Reserved [0b01]Reserved [0b10]SOSC. This option requires that SOSC be divided using the TRIMDIV field to get a frequency of 1 MHz. [0b11]Reserved
SIRCTCFG_TRIMDIV	SIRCTCFG - TRIMDIV. SIRC Trim Configuration Register - SIRC Trim Pre-divider
SIRCTRIM_CCOTRIM	SIRCTRIM - CCOTRIM. SIRC Trim Register - CCO Trim
SIRCTRIM_CLTRIM	SIRCTRIM - CLTRIM. SIRC Trim Register - CL Trim
SIRCTRIM_TCTRIM	SIRCTRIM - TCTRIM. SIRC Trim Register - Trim Temp
SIRCTRIM_FVCHTRIM	SIRCTRIM - FVCHTRIM. SIRC Trim Register
SIRCSTAT_CCOTRIM	SIRCSTAT - CCOTRIM. SIRC Trim Register - CCO Trim
SIRCSTAT_CLTRIM	SIRCSTAT - CLTRIM. SIRC Auto-trimming Status Register - CL Trim
FIRCCSR_FIRCEN	FIRCEN. SIRC Auto-trimming Status Register - FIRC Enable [0b0]FIRC is disabled [0b1]FIRC is enabled
FIRCCSR_FIRCSTEN	FIRCCSR - FIRCSTEN. FIRC Control Status Register - FIRC Stop Enable [0b0]FIRC is disabled in Deep Sleep mode [0b1]FIRC is enabled in Deep Sleep mode
FIRCCSR_FIRC_SCLK_PERIPH_EN	FIRCCSR - FIRC_SCLK_PERIPH_EN. FIRC Control Status Register - FIRC 48 MHz Clock to peripherals Enable [0b0]FIRC 48 MHz to peripherals is disabled [0b1]FIRC 48 MHz to peripherals is enabled
FIRCCSR_FIRC_FCLK_PERIPH_EN	FIRCCSR - FIRC_FCLK_PERIPH_EN. FIRC Control Status Register - FRO_HF Clock to peripherals Enable [0b0]FRO_HF to peripherals is disabled [0b1]FRO_HF to peripherals is enabled
FIRCCSR_FIRCTREN	FIRCCSR - FIRCTREN. FIRC Control Status Register - FRO_HF Trim Enable [0b0]Disables trimming FRO_HF by an external clock source [0b1]Enables trimming FRO_HF by an external clock source
FIRCCSR_FIRCTRUP	FIRCCSR - FIRCTRUP. FIRC Control Status Register - FIRC Trim Update [0b0]Disables FIRC trimming updates [0b1]Enables FIRC trimming updates
FIRCCSR_TRIM_LOCK	FIRCCSR - TRIM_LOCK. FIRC Control Status Register - FIRC TRIM LOCK [0b0]FIRC auto trim not locked to target frequency range [0b1]FIRC auto trim locked to target frequency range
FIRCCSR_COARSE_TRIM_BYPASS	FIRCCSR - COARSE_TRIM_BYPASS. FIRC Control Status Register - Coarse Auto Trim Bypass [0b0]FIRC Coarse Auto Trim NOT Bypassed [0b1]FIRC Coarse Auto Trim Bypassed
FIRCCSR_LK	FIRCCSR - LK. FIRC Control Status Register - Lock Register [0b0]Control Status Register can be written [0b1]Control Status Register cannot be written
FIRCCSR_FIRCVLD	FIRCCSR - FIRCVLD. FIRC Control Status Register - FIRC Valid status [0b0]FIRC is not enabled or clock is not valid. [0b1]FIRC is enabled and output clock is valid. The clock is valid after there is an output clock from the FIRC analog.
FIRCCSR_FIRCSEL	FIRCCSR - FIRCSEL. FIRC Control Status Register - FIRC Selected [0b0]FIRC is not the system clock source [0b1]FIRC is the system clock source
FIRCCSR_FIRCERR	FIRCCSR - FIRCERR. FIRC Control Status Register - FIRC Clock Error [0b0]Error not detected with the FIRC trimming [0b1]Error detected with the FIRC trimming
FIRCCSR_FIRCERR_IE	FIRCCSR - FIRCERR_IE. FIRC Control Status Register - FIRC Clock Error Interrupt Enable [0b0]FIRCERR interrupt is not enabled [0b1]FIRCERR interrupt is enabled
FIRCCSR_FIRCACC_IE	FIRCCSR - FIRCACC_IE. FIRC Control Status Register - FIRC Accurate Interrupt Enable [0b0]FIRCACC interrupt is not enabled [0b1]FIRCACC interrupt is enabled
FIRCCSR_FIRCACC	FIRCCSR - FIRCACC. FIRC Control Status Register - FIRC Frequency Accurate -[0b0]FIRC is not enabled or clock is not accurate. -[0b1]FIRC is enabled and output clock is accurate after some preparation time which is obtained by counting FRO_HF clock.
FIRCCFG_FREQ_SEL	FIRCCFG - FREQ_SEL. FIRC Configuration Register - Frequency select [0b111]192 MHz FIRC clock selected [0b101]96 MHz FIRC clock selected [0b011]64 MHz FIRC clock selected [0b001]48 MHz FIRC clock selected, divided from 192 MHz
FIRCTCFG_TRIMSRC	FIRCCFG - TRIMSRC. FIRC Configuration Register - Trim Source [0b00]USB0 Start of Frame (1 KHz). This option does not use TRIMDIV . [0b01]Reserved [0b10]SOSC. This option requires that SOSC be divided using the TRIMDIV field to get a frequency of 1 MHz. [0b11]Reserved
FIRCTCFG_TRIMDIV	FIRCCFG - TRIMDIV. FIRC Configuration Register - FIRC Trim Pre-divider
FIRCTRIM_TRIMFINE	FIRCTRIM - TRIMFINE. FIRC Trim Register - Trim Fine
FIRCTRIM_TRIMCOAR	FIRCTRIM - TRIMCOAR. FIRC Trim Register - Trim Coarse
FIRCTRIM_TRIMTEMP2	FIRCTRIM - TRIMTEMP2. FIRC Trim Register - Trim Temperature2
FIRCTRIM_TRIMSTART	FIRCTRIM - TRIMSTART. FIRC Trim Register - Trim Start
FIRCSTAT_TRIMFINE	FIRCSTAT - TRIMFINE. FIRC Auto-trimming Status Register - Trim Fine
FIRCSTAT_TRIMCOAR	FIRCSTAT - TRIMCOAR. FIRC Auto-trimming Status Register - Trim Coarse
FIRCATC1_IDEALC	FIRCATC1 - IDEALC. FIRC Auto-trimming Counter 1 - Ideal Counter
FIRCATC2_COARMINC	FIRCATC2 - COARMINC. FIRC Auto-trimming Counter 1 - Coarse Trim Minimum Counter
FIRCATC2_COARMAXC	FIRCATC2 - COARMAXC. FIRC Auto-trimming Counter 1 - Coarse Trim Maximum Counter
FIRCATC3_FINEMINC	FIRCATC3 - FINEMINC. FIRC Auto-trimming Counter 2 - Fine Trim Minimum Counter
FIRCATC3_FINEMAXC	FIRCATC3 - FINEMAXC. FIRC Auto-trimming Counter 2 - Fine Trim Maximum Counter
ROSCCSR_LK	ROSCCSR - LK. ROSC Control Status Register - Lock Register [0b0]Control Status Register can be written [0b1]Control Status Register cannot be written
ROSCCSR_ROSCVLD	ROSCCSR - ROSCVLD. ROSC Control Status Register - ROSC Valid [0b0]ROSC is not enabled or clock is not valid [0b1]ROSC is enabled and output clock is valid
ROSCCSR_ROSCSEL	ROSCCSR - ROSCSEL. ROSC Control Status Register - ROSC Selected [0b0]ROSC is not the system clock source [0b1]ROSC is the system clock source
ROSCCSR_ROSCERR	ROSCCSR - ROSCERR. ROSC Control Status Register - ROSC Clock Error [0b0]ROSC Clock has not detected an error [0b1]ROSC Clock has detected an error