chip::mrcc::Register 結構 參考文件

公開屬性
__IO uint32	mrcc_glb_rst0
__O uint32	mrcc_glb_rst0_set
__O uint32	mrcc_glb_rst0_clr
uint8	reserved_0 [4]
__IO uint32	mrcc_glb_rst1
__O uint32	mrcc_glb_rst1_set
__O uint32	mrcc_glb_rst1_clr
uint8	reserved_1 [36]
__IO uint32	mrcc_glb_cc0
__O uint32	mrcc_glb_cc0_set
__O uint32	mrcc_glb_cc0_clr
uint8	reserved_2 [4]
__IO uint32	mrcc_glb_cc1
__O uint32	mrcc_glb_cc1_set
__O uint32	mrcc_glb_cc1_clr
uint8	reserved_3 [36]
__IO uint32	mrcc_glb_acc0
__IO uint32	mrcc_glb_acc1
uint8	reserved_4 [24]
__IO uint32	mrcc_i3c0_fclk_clksel
__IO uint32	mrcc_i3c0_fclk_clkdiv
__IO uint32	mrcc_ctimer0_clksel
__IO uint32	mrcc_ctimer0_clkdiv
__IO uint32	mrcc_ctimer1_clksel
__IO uint32	mrcc_ctimer1_clkdiv
__IO uint32	mrcc_ctimer2_clksel
__IO uint32	mrcc_ctimer2_clkdiv
uint8	reserved_5 [4]
__IO uint32	mrcc_wwdt0_clkdiv
__IO uint32	mrcc_lpi2c0_clksel
__IO uint32	mrcc_lpi2c0_clkdiv
__IO uint32	mrcc_lpspi0_clksel
__IO uint32	mrcc_lpspi0_clkdiv
__IO uint32	mrcc_lpspi1_clksel
__IO uint32	mrcc_lpspi1_clkdiv
__IO uint32	mrcc_lpuart0_clksel
__IO uint32	mrcc_lpuart0_clkdiv
__IO uint32	mrcc_lpuart1_clksel
__IO uint32	mrcc_lpuart1_clkdiv
__IO uint32	mrcc_lpuart2_clksel
__IO uint32	mrcc_lpuart2_clkdiv
__IO uint32	mrcc_usb0_clksel
uint8	reserved_6 [4]
__IO uint32	mrcc_lptmr0_clksel
__IO uint32	mrcc_lptmr0_clkdiv
__IO uint32	mrcc_ostimer0_clksel
uint8	reserved_7 [4]
__IO uint32	mrcc_adc0_clksel
__IO uint32	mrcc_adc0_clkdiv
uint8	reserved_8 [4]
__IO uint32	mrcc_cmp0_func_clkdiv
__IO uint32	mrcc_cmp0_rr_clksel
__IO uint32	mrcc_cmp0_rr_clkdiv
uint8	reserved_9 [4]
__IO uint32	mrcc_cmp1_func_clkdiv
__IO uint32	mrcc_cmp1_rr_clksel
__IO uint32	mrcc_cmp1_rr_clkdiv
__IO uint32	mrcc_dbg_trace_clksel
__IO uint32	mrcc_dbg_trace_clkdiv
__IO uint32	mrcc_clkout_clksel
__IO uint32	mrcc_clkout_clkdiv
__IO uint32	mrcc_systick_clksel
__IO uint32	mrcc_systick_clkdiv
uint8	reserved_10 [4]
__IO uint32	mrcc_fro_hf_div_clkdiv

資料成員說明文件

mrcc_adc0_clkdiv

__IO uint32 chip::mrcc::Register::mrcc_adc0_clkdiv

ADC0 clock divider control, offset: 0x114

mrcc_adc0_clksel

__IO uint32 chip::mrcc::Register::mrcc_adc0_clksel

ADC0 clock selection control, offset: 0x110

mrcc_clkout_clkdiv

__IO uint32 chip::mrcc::Register::mrcc_clkout_clkdiv

CLKOUT clock divider control, offset: 0x144

mrcc_clkout_clksel

__IO uint32 chip::mrcc::Register::mrcc_clkout_clksel

CLKOUT clock selection control, offset: 0x140

mrcc_cmp0_func_clkdiv

__IO uint32 chip::mrcc::Register::mrcc_cmp0_func_clkdiv

CMP0_FUNC clock divider control, offset: 0x11C

mrcc_cmp0_rr_clkdiv

__IO uint32 chip::mrcc::Register::mrcc_cmp0_rr_clkdiv

CMP0_RR clock divider control, offset: 0x124

mrcc_cmp0_rr_clksel

__IO uint32 chip::mrcc::Register::mrcc_cmp0_rr_clksel

CMP0_RR clock selection control, offset: 0x120

mrcc_cmp1_func_clkdiv

__IO uint32 chip::mrcc::Register::mrcc_cmp1_func_clkdiv

CMP1_FUNC clock divider control, offset: 0x12C

mrcc_cmp1_rr_clkdiv

__IO uint32 chip::mrcc::Register::mrcc_cmp1_rr_clkdiv

CMP1_RR clock divider control, offset: 0x134

mrcc_cmp1_rr_clksel

__IO uint32 chip::mrcc::Register::mrcc_cmp1_rr_clksel

CMP1_RR clock selection control, offset: 0x130

mrcc_ctimer0_clkdiv

__IO uint32 chip::mrcc::Register::mrcc_ctimer0_clkdiv

CTIMER0 clock divider control, offset: 0xAC

mrcc_ctimer0_clksel

__IO uint32 chip::mrcc::Register::mrcc_ctimer0_clksel

CTIMER0 clock selection control, offset: 0xA8

mrcc_ctimer1_clkdiv

__IO uint32 chip::mrcc::Register::mrcc_ctimer1_clkdiv

CTIMER1 clock divider control, offset: 0xB4

mrcc_ctimer1_clksel

__IO uint32 chip::mrcc::Register::mrcc_ctimer1_clksel

CTIMER1 clock selection control, offset: 0xB0

mrcc_ctimer2_clkdiv

__IO uint32 chip::mrcc::Register::mrcc_ctimer2_clkdiv

CTIMER2 clock divider control, offset: 0xBC

mrcc_ctimer2_clksel

__IO uint32 chip::mrcc::Register::mrcc_ctimer2_clksel

CTIMER2 clock selection control, offset: 0xB8

mrcc_dbg_trace_clkdiv

__IO uint32 chip::mrcc::Register::mrcc_dbg_trace_clkdiv

DBG_TRACE clock divider control, offset: 0x13C

mrcc_dbg_trace_clksel

__IO uint32 chip::mrcc::Register::mrcc_dbg_trace_clksel

DBG_TRACE clock selection control, offset: 0x138

mrcc_fro_hf_div_clkdiv

__IO uint32 chip::mrcc::Register::mrcc_fro_hf_div_clkdiv

FRO_HF_DIV clock divider control, offset: 0x154

mrcc_glb_acc0

__IO uint32 chip::mrcc::Register::mrcc_glb_acc0

Control Automatic Clock Gating 0, offset: 0x80

mrcc_glb_acc1

__IO uint32 chip::mrcc::Register::mrcc_glb_acc1

Control Automatic Clock Gating 1, offset: 0x84

mrcc_glb_cc0

__IO uint32 chip::mrcc::Register::mrcc_glb_cc0

AHB Clock Control 0, offset: 0x40

mrcc_glb_cc0_clr

__O uint32 chip::mrcc::Register::mrcc_glb_cc0_clr

AHB Clock Control Clear 0, offset: 0x48

mrcc_glb_cc0_set

__O uint32 chip::mrcc::Register::mrcc_glb_cc0_set

AHB Clock Control Set 0, offset: 0x44

mrcc_glb_cc1

__IO uint32 chip::mrcc::Register::mrcc_glb_cc1

AHB Clock Control 1, offset: 0x50

mrcc_glb_cc1_clr

__O uint32 chip::mrcc::Register::mrcc_glb_cc1_clr

AHB Clock Control Clear 1, offset: 0x58

mrcc_glb_cc1_set

__O uint32 chip::mrcc::Register::mrcc_glb_cc1_set

AHB Clock Control Set 1, offset: 0x54

mrcc_glb_rst0

__IO uint32 chip::mrcc::Register::mrcc_glb_rst0

Peripheral Reset Control 0, offset: 0x0

mrcc_glb_rst0_clr

__O uint32 chip::mrcc::Register::mrcc_glb_rst0_clr

Peripheral Reset Control Clear 0, offset: 0x8

mrcc_glb_rst0_set

__O uint32 chip::mrcc::Register::mrcc_glb_rst0_set

Peripheral Reset Control Set 0, offset: 0x4

mrcc_glb_rst1

__IO uint32 chip::mrcc::Register::mrcc_glb_rst1

Peripheral Reset Control 1, offset: 0x10

mrcc_glb_rst1_clr

__O uint32 chip::mrcc::Register::mrcc_glb_rst1_clr

Peripheral Reset Control Clear 1, offset: 0x18

mrcc_glb_rst1_set

__O uint32 chip::mrcc::Register::mrcc_glb_rst1_set

Peripheral Reset Control Set 1, offset: 0x14

mrcc_i3c0_fclk_clkdiv

__IO uint32 chip::mrcc::Register::mrcc_i3c0_fclk_clkdiv

I3C0_FCLK clock divider control, offset: 0xA4

mrcc_i3c0_fclk_clksel

__IO uint32 chip::mrcc::Register::mrcc_i3c0_fclk_clksel

I3C0_FCLK clock selection control, offset: 0xA0

mrcc_lpi2c0_clkdiv

__IO uint32 chip::mrcc::Register::mrcc_lpi2c0_clkdiv

LPI2C0 clock divider control, offset: 0xCC

mrcc_lpi2c0_clksel

__IO uint32 chip::mrcc::Register::mrcc_lpi2c0_clksel

LPI2C0 clock selection control, offset: 0xC8

mrcc_lpspi0_clkdiv

__IO uint32 chip::mrcc::Register::mrcc_lpspi0_clkdiv

LPSPI0 clock divider control, offset: 0xD4

mrcc_lpspi0_clksel

__IO uint32 chip::mrcc::Register::mrcc_lpspi0_clksel

LPSPI0 clock selection control, offset: 0xD0

mrcc_lpspi1_clkdiv

__IO uint32 chip::mrcc::Register::mrcc_lpspi1_clkdiv

LPSPI1 clock divider control, offset: 0xDC

mrcc_lpspi1_clksel

__IO uint32 chip::mrcc::Register::mrcc_lpspi1_clksel

LPSPI1 clock selection control, offset: 0xD8

mrcc_lptmr0_clkdiv

__IO uint32 chip::mrcc::Register::mrcc_lptmr0_clkdiv

LPTMR0 clock divider control, offset: 0x104

mrcc_lptmr0_clksel

__IO uint32 chip::mrcc::Register::mrcc_lptmr0_clksel

LPTMR0 clock selection control, offset: 0x100

mrcc_lpuart0_clkdiv

__IO uint32 chip::mrcc::Register::mrcc_lpuart0_clkdiv

LPUART0 clock divider control, offset: 0xE4

mrcc_lpuart0_clksel

__IO uint32 chip::mrcc::Register::mrcc_lpuart0_clksel

LPUART0 clock selection control, offset: 0xE0

mrcc_lpuart1_clkdiv

__IO uint32 chip::mrcc::Register::mrcc_lpuart1_clkdiv

LPUART1 clock divider control, offset: 0xEC

mrcc_lpuart1_clksel

__IO uint32 chip::mrcc::Register::mrcc_lpuart1_clksel

LPUART1 clock selection control, offset: 0xE8

mrcc_lpuart2_clkdiv

__IO uint32 chip::mrcc::Register::mrcc_lpuart2_clkdiv

LPUART2 clock divider control, offset: 0xF4

mrcc_lpuart2_clksel

__IO uint32 chip::mrcc::Register::mrcc_lpuart2_clksel

LPUART2 clock selection control, offset: 0xF0

mrcc_ostimer0_clksel

__IO uint32 chip::mrcc::Register::mrcc_ostimer0_clksel

OSTIMER0 clock selection control, offset: 0x108

mrcc_systick_clkdiv

__IO uint32 chip::mrcc::Register::mrcc_systick_clkdiv

SYSTICK clock divider control, offset: 0x14C

mrcc_systick_clksel

__IO uint32 chip::mrcc::Register::mrcc_systick_clksel

SYSTICK clock selection control, offset: 0x148

mrcc_usb0_clksel

__IO uint32 chip::mrcc::Register::mrcc_usb0_clksel

USB0 clock selection control, offset: 0xF8

mrcc_wwdt0_clkdiv

__IO uint32 chip::mrcc::Register::mrcc_wwdt0_clkdiv

WWDT0 clock divider control, offset: 0xC4

reserved_0

uint8 chip::mrcc::Register::reserved_0[4]

Reserved

reserved_1

uint8 chip::mrcc::Register::reserved_1[36]

Reserved

reserved_10

uint8 chip::mrcc::Register::reserved_10[4]

Reserved

reserved_2

uint8 chip::mrcc::Register::reserved_2[4]

Reserved

reserved_3

uint8 chip::mrcc::Register::reserved_3[36]

Reserved

reserved_4

uint8 chip::mrcc::Register::reserved_4[24]

Reserved

reserved_5

uint8 chip::mrcc::Register::reserved_5[4]

Reserved

reserved_6

uint8 chip::mrcc::Register::reserved_6[4]

Reserved

reserved_7

uint8 chip::mrcc::Register::reserved_7[4]

Reserved

reserved_8

uint8 chip::mrcc::Register::reserved_8[4]

Reserved

reserved_9

uint8 chip::mrcc::Register::reserved_9[4]

Reserved

---

此結構(structure) 文件是由下列檔案中產生:

• mrcc/Register.h