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複合項目 | 列舉型態 | 函式 | 變數
chip::mrcc 命名空間(Namespace)參考文件

複合項目

class  MRCC
 
struct  Register
 

列舉型態

enum struct  Count : unsigned int { MRCC_GLB_CC_SET = 1U , MRCC_GLB_CC_CLR = 1U }
 
enum struct  Mask : unsigned int {
  GLB_RST0_INPUTMUX0 = 0x00000001U , GLB_RST0_I3C0 = 0x00000002U , GLB_RST0_CTIMER0 = 0x00000004U , GLB_RST0_CTIMER1 = 0x00000008U ,
  GLB_RST0_CTIMER2 = 0x00000010U , GLB_RST0_CTIMER3 = 0x00000020U , GLB_RST0_CTIMER4 = 0x00000040U , GLB_RST0_FREQME = 0x00000080U ,
  GLB_RST0_UTICK0 = 0x00000100U , GLB_RST0_DMA = 0x00000400U , GLB_RST0_AOI0 = 0x00000800U , GLB_RST0_CRC0 = 0x00001000U ,
  GLB_RST0_EIM0 = 0x00002000U , GLB_RST0_ERM0 = 0x00004000U , GLB_RST0_AOI1 = 0x00010000U , GLB_RST0_FLEXIO0 = 0x00020000U ,
  GLB_RST0_LPI2C0 = 0x00040000U , GLB_RST0_LPI2C1 = 0x00080000U , GLB_RST0_LPSPI0 = 0x00100000U , GLB_RST0_LPSPI1 = 0x00200000U ,
  GLB_RST0_LPUART0 = 0x00400000U , GLB_RST0_LPUART1 = 0x00800000U , GLB_RST0_LPUART2 = 0x01000000U , GLB_RST0_LPUART3 = 0x02000000U ,
  GLB_RST0_LPUART4 = 0x04000000U , GLB_RST0_USB0 = 0x08000000U , GLB_RST0_QDC0 = 0x10000000U , GLB_RST0_QDC1 = 0x20000000U ,
  GLB_RST0_FLEXPWM0 = 0x40000000U , GLB_RST0_FLEXPWM1 = 0x80000000U , GLB_RST0_SET_DATA = 0xFFFFFFFFU , GLB_RST0_CLR_DATA = 0xFFFFFFFFU ,
  GLB_RST1_OSTIMER0 = 0x00000001U , GLB_RST1_ADC0 = 0x00000002U , GLB_RST1_ADC1 = 0x00000004U , GLB_RST1_CMP1 = 0x00000010U ,
  GLB_RST1_DAC0 = 0x00000020U , GLB_RST1_OPAMP0 = 0x00000040U , GLB_RST1_PORT0 = 0x00000080U , GLB_RST1_PORT1 = 0x00000100U ,
  GLB_RST1_PORT2 = 0x00000200U , GLB_RST1_PORT3 = 0x00000400U , GLB_RST1_PORT4 = 0x00000800U , GLB_RST1_FLEXCAN0 = 0x00001000U ,
  GLB_RST1_LPI2C2 = 0x00002000U , GLB_RST1_LPI2C3 = 0x00004000U , GLB_RST1_GPIO0 = 0x00100000U , GLB_RST1_GPIO1 = 0x00200000U ,
  GLB_RST1_GPIO2 = 0x00400000U , GLB_RST1_GPIO3 = 0x00800000U , GLB_RST1_GPIO4 = 0x01000000U , GLB_RST1_SET_DATA = 0xFFFFFFFFU ,
  GLB_RST1_CLR_DATA = 0xFFFFFFFFU , GLB_CC0_INPUTMUX0 = 0x00000001U , GLB_CC0_I3C0 = 0x00000002U , GLB_CC0_CTIMER0 = 0x00000004U ,
  GLB_CC0_CTIMER1 = 0x00000008U , GLB_CC0_CTIMER2 = 0x0000010U , GLB_CC0_CTIMER3 = 0x00000020U , GLB_CC0_CTIMER4 = 0x00000040U ,
  GLB_CC0_FREQME = 0x00000080U , GLB_CC0_UTICK0 = 0x00000100U , GLB_CC0_WWDT0 = 0x00000200U , GLB_CC0_DMA = 0x00000400U ,
  GLB_CC0_AOI0 = 0x00000800U , GLB_CC0_CRC0 = 0x00001000U , GLB_CC0_EIM0 = 0x00002000U , GLB_CC0_ERM0 = 0x00004000U ,
  GLB_CC0_FMC = 0x00008000U , GLB_CC0_AOI1 = 0x00010000U , GLB_CC0_FLEXIO0 = 0x00020000U , GLB_CC0_LPI2C0 = 0x00040000U ,
  GLB_CC0_LPI2C1 = 0x00080000U , GLB_CC0_LPSPI0 = 0x00100000U , GLB_CC0_LPSPI1 = 0x00200000U , GLB_CC0_LPUART0 = 0x00400000U ,
  GLB_CC0_LPUART1 = 0x00800000U , GLB_CC0_LPUART2 = 0x01000000U , GLB_CC0_LPUART3 = 0x02000000U , GLB_CC0_LPUART4 = 0x04000000U ,
  GLB_CC0_USB0 = 0x08000000U , GLB_CC0_QDC0 = 0x10000000U , GLB_CC0_QDC1 = 0x20000000U , GLB_CC0_FLEXPWM0 = 0x40000000U ,
  GLB_CC0_FLEXPWM1 = 0x80000000U , GLB_CC0_SET_DATA = 0xFFFFFFFFU , GLB_CC0_CLR_DATA = 0xFFFFFFFFU , GLB_CC1_OSTIMER0 = 0x00000001U ,
  GLB_CC1_ADC0 = 0x00000002U , GLB_CC1_ADC1 = 0x00000004U , GLB_CC1_CMP0 = 0x00000008U , GLB_CC1_CMP1 = 0x00000010U ,
  GLB_CC1_DAC0 = 0x00000020U , GLB_CC1_OPAMP0 = 0x00000040U , GLB_CC1_PORT0 = 0x00000080U , GLB_CC1_PORT1 = 0x00000100U ,
  GLB_CC1_PORT2 = 0x00000200U , GLB_CC1_PORT3 = 0x00000400U , GLB_CC1_PORT4 = 0x00000800U , GLB_CC1_FLEXCAN0 = 0x00001000U ,
  GLB_CC1_LPI2C2 = 0x00002000U , GLB_CC1_LPI2C3 = 0x00004000U , GLB_CC1_RAMA = 0x00040000U , GLB_CC1_RAMB = 0x00080000U ,
  GLB_CC1_GPIO0 = 0x00100000U , GLB_CC1_GPIO1 = 0x00200000U , GLB_CC1_GPIO2 = 0x00400000U , GLB_CC1_GPIO3 = 0x00800000U ,
  GLB_CC1_GPIO4 = 0x01000000U , GLB_CC1_ROMC = 0x02000000U , GLB_CC_SET_DATA = 0xFFFFFFFFU , GLB_CC_CLR_DATA = 0xFFFFFFFFU ,
  GLB_ACC0_INPUTMUX0 = 0x00000001U , GLB_ACC0_I3C0 = 0x00000002U , GLB_ACC0_CTIMER0 = 0x00000004U , GLB_ACC0_CTIMER1 = 0x00000008U ,
  GLB_ACC0_CTIMER2 = 0x00000010U , GLB_ACC0_CTIMER3 = 0x00000020U , GLB_ACC0_CTIMER4 = 0x00000040U , GLB_ACC0_FREQME = 0x00000080U ,
  GLB_ACC0_UTICK0 = 0x00000100U , GLB_ACC0_WWDT0 = 0x00000200U , GLB_ACC0_DMA = 0x00000400U , GLB_ACC0_AOI0 = 0x00000800U ,
  GLB_ACC0_CRC0 = 0x00001000U , GLB_ACC0_EIM0 = 0x00002000U , GLB_ACC0_ERM0 = 0x00004000U , GLB_ACC0_FMC = 0x00008000U ,
  GLB_ACC0_AOI1 = 0x00010000U , GLB_ACC0_FLEXIO0 = 0x00020000U , GLB_ACC0_LPI2C0 = 0x00040000U , GLB_ACC0_LPI2C1 = 0x00080000U ,
  GLB_ACC0_LPSPI0 = 0x00100000U , GLB_ACC0_LPSPI1 = 0x00200000U , GLB_ACC0_LPUART0 = 0x00400000U , GLB_ACC0_LPUART1 = 0x00800000U ,
  GLB_ACC0_LPUART2 = 0x01000000U , GLB_ACC0_LPUART3 = 0x02000000U , GLB_ACC0_LPUART4 = 0x04000000U , GLB_ACC0_USB0 = 0x08000000U ,
  GLB_ACC0_QDC0 = 0x10000000U , GLB_ACC0_QDC1 = 0x20000000U , GLB_ACC0_FLEXPWM0 = 0x40000000U , GLB_ACC0_FLEXPWM1 = 0x80000000U ,
  GLB_ACC1_OSTIMER0 = 0x00000001U , GLB_ACC1_ADC0 = 0x00000002U , GLB_ACC1_ADC1 = 0x00000004U , GLB_ACC1_CMP0 = 0x00000008U ,
  GLB_ACC1_CMP1 = 0x00000010U , GLB_ACC1_DAC0 = 0x00000020U , GLB_ACC1_OPAMP0 = 0x00000040U , GLB_ACC1_PORT0 = 0x00000080U ,
  GLB_ACC1_PORT1 = 0x00000100U , GLB_ACC1_PORT2 = 0x00000200U , GLB_ACC1_PORT3 = 0x00000400U , GLB_ACC1_PORT4 = 0x00000800U ,
  GLB_ACC1_FLEXCAN0 = 0x00001000U , GLB_ACC1_LPI2C2 = 0x00002000U , GLB_ACC1_LPI2C3 = 0x00004000U , GLB_ACC1_RAMA = 0x00040000U ,
  GLB_ACC1_RAMB = 0x00080000U , GLB_ACC1_GPIO0 = 0x00100000U , GLB_ACC1_GPIO1 = 0x00200000U , GLB_ACC1_GPIO2 = 0x00400000U ,
  GLB_ACC1_GPIO3 = 0x00800000U , GLB_ACC1_GPIO4 = 0x01000000U , GLB_ACC1_ROMC = 0x02000000U , I3C0_FCLK_CLKSEL_MUX = 0x00000007U ,
  I3C0_FCLK_CLKDIV_DIV = 0x0000000FU , I3C0_FCLK_CLKDIV_RESET = 0x20000000U , I3C0_FCLK_CLKDIV_HALT = 0x40000000U , I3C0_FCLK_CLKDIV_UNSTAB = 0x80000000U ,
  CTIMER0_CLKSEL_MUX = 0x00000007U , CTIMER0_CLKDIV_DIV = 0x0000000FU , CTIMER0_CLKDIV_RESET = 0x20000000U , CTIMER0_CLKDIV_HALT = 0x40000000U ,
  CTIMER0_CLKDIV_UNSTAB = 0x80000000U , CTIMER1_CLKSEL_MUX = 0x00000007U , CTIMER1_CLKDIV_DIV = 0x0000000FU , CTIMER1_CLKDIV_RESET = 0x20000000U ,
  CTIMER1_CLKDIV_HALT = 0x40000000U , CTIMER1_CLKDIV_UNSTAB = 0x80000000U , CTIMER2_CLKSEL_MUX = 0x00000007U , CTIMER2_CLKDIV_DIV = 0x0000000FU ,
  CTIMER2_CLKDIV_RESET = 0x20000000U , CTIMER2_CLKDIV_HALT = 0x40000000U , CTIMER2_CLKDIV_UNSTAB = 0x80000000U , CTIMER3_CLKSEL_MUX = 0x00000007U ,
  CTIMER3_CLKDIV_DIV = 0x0000000FU , CTIMER3_CLKDIV_RESET = 0x20000000U , CTIMER3_CLKDIV_HALT = 0x40000000U , CTIMER3_CLKDIV_UNSTAB = 0x80000000U ,
  CTIMER4_CLKSEL_MUX = 0x00000007U , CTIMER4_CLKDIV_DIV = 0x0000000FU , CTIMER4_CLKDIV_RESET = 0x20000000U , CTIMER4_CLKDIV_HALT = 0x40000000U ,
  CTIMER4_CLKDIV_UNSTAB = 0x80000000U , WWDT0_CLKDIV_DIV = 0x0000000FU , WWDT0_CLKDIV_RESET = 0x20000000U , WWDT0_CLKDIV_HALT = 0x40000000U ,
  WWDT0_CLKDIV_UNSTAB = 0x80000000U , FLEXIO0_CLKSEL_MUX = 0x00000007U , FLEXIO0_CLKDIV_DIV = 0x0000000FU , FLEXIO0_CLKDIV_RESET = 0x20000000U ,
  FLEXIO0_CLKDIV_HALT = 0x40000000U , FLEXIO0_CLKDIV_UNSTAB = 0x80000000U , LPI2C0_CLKSEL_MUX = 0x00000007U , LPI2C0_CLKDIV_DIV = 0x0000000FU ,
  LPI2C0_CLKDIV_RESET = 0x20000000U , LPI2C0_CLKDIV_HALT = 0x40000000U , LPI2C0_CLKDIV_UNSTAB = 0x80000000U , LPI2C1_CLKSEL_MUX = 0x00000007U ,
  LPI2C1_CLKDIV_DIV = 0x0000000FU , LPI2C1_CLKDIV_RESET = 0x20000000U , LPI2C1_CLKDIV_HALT = 0x40000000U , LPI2C1_CLKDIV_UNSTAB = 0x80000000U ,
  LPSPI0_CLKSEL_MUX = 0x00000007U , LPSPI0_CLKDIV_DIV = 0x0000000FU , LPSPI0_CLKDIV_RESET = 0x20000000U , LPSPI0_CLKDIV_HALT = 0x40000000U ,
  LPSPI0_CLKDIV_UNSTAB = 0x80000000U , LPSPI1_CLKSEL_MUX = 0x00000007U , LPSPI1_CLKDIV_DIV = 0x0000000FU , LPSPI1_CLKDIV_RESET = 0x20000000U ,
  LPSPI1_CLKDIV_HALT = 0x40000000U , LPSPI1_CLKDIV_UNSTAB = 0x80000000U , LPUART0_CLKSEL_MUX = 0x00000007U , LPUART0_CLKDIV_DIV = 0x0000000FU ,
  LPUART0_CLKDIV_RESET = 0x20000000U , LPUART0_CLKDIV_HALT = 0x40000000U , LPUART0_CLKDIV_UNSTAB = 0x80000000U , LPUART1_CLKSEL_MUX = 0x00000007U ,
  LPUART1_CLKDIV_DIV = 0x0000000FU , LPUART1_CLKDIV_RESET = 0x20000000U , LPUART1_CLKDIV_HALT = 0x40000000U , LPUART1_CLKDIV_UNSTAB = 0x80000000U ,
  LPUART2_CLKSEL_MUX = 0x00000007U , LPUART2_CLKDIV_DIV = 0x0000000FU , LPUART2_CLKDIV_RESET = 0x20000000U , LPUART2_CLKDIV_HALT = 0x40000000U ,
  LPUART2_CLKDIV_UNSTAB = 0x80000000U , LPUART3_CLKSEL_MUX = 0x00000007U , LPUART3_CLKDIV_DIV = 0x0000000FU , LPUART3_CLKDIV_RESET = 0x20000000U ,
  LPUART3_CLKDIV_HALT = 0x40000000U , LPUART3_CLKDIV_UNSTAB = 0x80000000U , LPUART4_CLKSEL_MUX = 0x00000007U , LPUART4_CLKDIV_DIV = 0x0000000FU ,
  LPUART4_CLKDIV_RESET = 0x20000000U , LPUART4_CLKDIV_HALT = 0x40000000U , LPUART4_CLKDIV_UNSTAB = 0x80000000U , USB0_CLKSEL_MUX = 0x00000003U ,
  LPTMR0_CLKSEL_MUX = 0x00000007U , LPTMR0_CLKDIV_DIV = 0x0000000FU , LPTMR0_CLKDIV_RESET = 0x20000000U , LPTMR0_CLKDIV_HALT = 0x40000000U ,
  LPTMR0_CLKDIV_UNSTAB = 0x80000000U , OSTIMER0_CLKSEL_MUX = 0x00000003U , ADC0_CLKSEL_MUX = 0x00000007U , ADC0_CLKDIV_DIV = 0x0000000FU ,
  ADC0_CLKDIV_RESET = 0x20000000U , ADC0_CLKDIV_HALT = 0x40000000U , ADC0_CLKDIV_UNSTAB = 0x80000000U , ADC1_CLKSEL_MUX = 0x00000007U ,
  ADC1_CLKDIV_DIV = 0x0000000FU , ADC1_CLKDIV_RESET = 0x20000000U , ADC1_CLKDIV_HALT = 0x40000000U , ADC1_CLKDIV_UNSTAB = 0x80000000U ,
  CMP0_FUNC_CLKDIV_DIV = 0x0000000FU , CMP0_FUNC_CLKDIV_RESET = 0x20000000U , CMP0_FUNC_CLKDIV_HALT = 0x40000000U , CMP0_FUNC_CLKDIV_UNSTAB = 0x80000000U ,
  CMP0_RR_CLKSEL_MUX = 0x00000007U , CMP0_RR_CLKDIV_DIV = 0x0000000FU , CMP0_RR_CLKDIV_RESET = 0x20000000U , CMP0_RR_CLKDIV_HALT = 0x40000000U ,
  CMP0_RR_CLKDIV_UNSTAB = 0x80000000U , CMP1_FUNC_CLKDIV_DIV = 0x0000000FU , CMP1_FUNC_CLKDIV_RESET = 0x20000000U , CMP1_FUNC_CLKDIV_HALT = 0x40000000U ,
  CMP1_FUNC_CLKDIV_UNSTAB = 0x80000000U , CMP1_RR_CLKSEL_MUX = 0x00000007U , CMP1_RR_CLKDIV_DIV = 0x0000000FU , CMP1_RR_CLKDIV_RESET = 0x20000000U ,
  CMP1_RR_CLKDIV_HALT = 0x40000000U , CMP1_RR_CLKDIV_UNSTAB = 0x80000000U , DAC0_CLKSEL_MUX = 0x00000007U , DAC0_CLKDIV_DIV = 0x0000000FU ,
  DAC0_CLKDIV_RESET = 0x20000000U , DAC0_CLKDIV_HALT = 0x40000000U , DAC0_CLKDIV_UNSTAB = 0x80000000U , FLEXCAN0_CLKSEL_MUX = 0x00000007U ,
  FLEXCAN0_CLKDIV_DIV = 0x0000000FU , FLEXCAN0_CLKDIV_RESET = 0x20000000U , FLEXCAN0_CLKDIV_HALT = 0x40000000U , FLEXCAN0_CLKDIV_UNSTAB = 0x80000000U ,
  LPI2C2_CLKSEL_MUX = 0x00000007U , LPI2C2_CLKDIV_DIV = 0x0000000FU , LPI2C2_CLKDIV_RESET = 0x20000000U , LPI2C2_CLKDIV_HALT = 0x40000000U ,
  LPI2C2_CLKDIV_UNSTAB = 0x80000000U , LPI2C3_CLKSEL_MUX = 0x00000007U , LPI2C3_CLKDIV_DIV = 0x0000000FU , LPI2C3_CLKDIV_RESET = 0x20000000U ,
  LPI2C3_CLKDIV_HALT = 0x40000000U , LPI2C3_CLKDIV_UNSTAB = 0x80000000U , DBG_TRACE_CLKSEL_MUX = 0x00000003U , DBG_TRACE_CLKDIV_DIV = 0x0000000FU ,
  DBG_TRACE_CLKDIV_RESET = 0x20000000U , DBG_TRACE_CLKDIV_HALT = 0x40000000U , DBG_TRACE_CLKDIV_UNSTAB = 0x80000000U , CLKOUT_CLKSEL_MUX = 0x00000007U ,
  CLKOUT_CLKDIV_DIV = 0x0000000FU , CLKOUT_CLKDIV_RESET = 0x20000000U , CLKOUT_CLKDIV_HALT = 0x40000000U , CLKOUT_CLKDIV_UNSTAB = 0x80000000U ,
  SYSTICK_CLKSEL_MUX = 0x00000003U , SYSTICK_CLKDIV_DIV = 0x0000000FU , SYSTICK_CLKDIV_RESET = 0x20000000U , SYSTICK_CLKDIV_HALT = 0x40000000U ,
  SYSTICK_CLKDIV_UNSTAB = 0x80000000U , FRO_HF_DIV_CLKDIV_DIV = 0x0000000FU , FRO_HF_DIV_CLKDIV_UNSTAB = 0x80000000U
}
 MRCC_Register_Masks MRCC Register Masks. 更多...
 
enum struct  Shift : unsigned int {
  GLB_RST0_INPUTMUX0 = 0U , GLB_RST0_I3C0 = 1U , GLB_RST0_CTIMER0 = 2U , GLB_RST0_CTIMER1 = 3U ,
  GLB_RST0_CTIMER2 = 4U , GLB_RST0_CTIMER3 = 5U , GLB_RST0_CTIMER4 = 6U , GLB_RST0_FREQME = 7U ,
  GLB_RST0_UTICK0 = 8U , GLB_RST0_DMA = 10U , GLB_RST0_AOI0 = 11U , GLB_RST0_CRC0 = 12U ,
  GLB_RST0_EIM0 = 13U , GLB_RST0_ERM0 = 14U , GLB_RST0_AOI1 = 16U , GLB_RST0_FLEXIO0 = 17U ,
  GLB_RST0_LPI2C0 = 18U , GLB_RST0_LPI2C1 = 19U , GLB_RST0_LPSPI0 = 20U , GLB_RST0_LPSPI1 = 21U ,
  GLB_RST0_LPUART0 = 22U , GLB_RST0_LPUART1 = 23U , GLB_RST0_LPUART2 = 24U , GLB_RST0_LPUART3 = 25U ,
  GLB_RST0_LPUART4 = 26U , GLB_RST0_USB0 = 27U , GLB_RST0_QDC0 = 28U , GLB_RST0_QDC1 = 29U ,
  GLB_RST0_FLEXPWM0 = 30U , GLB_RST0_FLEXPWM1 = 31U , GLB_RST0_SET_DATA = 0U , GLB_RST0_CLR_DATA = 0U ,
  GLB_RST1_OSTIMER0 = 0U , GLB_RST1_ADC0 = 1U , GLB_RST1_ADC1 = 2U , GLB_RST1_CMP1 = 4U ,
  GLB_RST1_DAC0 = 5U , GLB_RST1_OPAMP0 = 6U , GLB_RST1_PORT0 = 7U , GLB_RST1_PORT1 = 8U ,
  GLB_RST1_PORT2 = 9U , GLB_RST1_PORT3 = 10U , GLB_RST1_PORT4 = 11U , GLB_RST1_FLEXCAN0 = 12U ,
  GLB_RST1_LPI2C2 = 13U , GLB_RST1_LPI2C3 = 14U , GLB_RST1_GPIO0 = 20U , GLB_RST1_GPIO1 = 21U ,
  GLB_RST1_GPIO2 = 22U , GLB_RST1_GPIO3 = 23U , GLB_RST1_GPIO4 = 24U , GLB_RST1_SET_DATA = 0U ,
  GLB_RST1_CLR_DATA = 0U , GLB_CC0_INPUTMUX0 = 0U , GLB_CC0_I3C0 = 1U , GLB_CC0_CTIMER0 = 2U ,
  GLB_CC0_CTIMER1 = 3U , GLB_CC0_CTIMER2 = 4U , GLB_CC0_CTIMER3 = 5U , GLB_CC0_CTIMER4 = 6U ,
  GLB_CC0_FREQME = 7U , GLB_CC0_UTICK0 = 8U , GLB_CC0_WWDT0 = 9U , GLB_CC0_DMA = 10U ,
  GLB_CC0_AOI0 = 11U , GLB_CC0_CRC0 = 12U , GLB_CC0_EIM0 = 13U , GLB_CC0_ERM0 = 14U ,
  GLB_CC0_FMC = 15U , GLB_CC0_AOI1 = 16U , GLB_CC0_FLEXIO0 = 17U , GLB_CC0_LPI2C0 = 18U ,
  GLB_CC0_LPI2C1 = 19U , GLB_CC0_LPSPI0 = 20U , GLB_CC0_LPSPI1 = 21U , GLB_CC0_LPUART0 = 22U ,
  GLB_CC0_LPUART1 = 23U , GLB_CC0_LPUART2 = 24U , GLB_CC0_LPUART3 = 25U , GLB_CC0_LPUART4 = 26U ,
  GLB_CC0_USB0 = 27U , GLB_CC0_QDC0 = 28U , GLB_CC0_QDC1 = 29U , GLB_CC0_FLEXPWM0 = 30U ,
  GLB_CC0_FLEXPWM1 = 31U , GLB_CC0_SET_DATA = 0U , GLB_CC0_CLR_DATA = 0U , GLB_CC1_OSTIMER0 = 0U ,
  GLB_CC1_ADC0 = 1U , GLB_CC1_ADC1 = 2U , GLB_CC1_CMP0 = 3U , GLB_CC1_CMP1 = 4U ,
  GLB_CC1_DAC0 = 5U , GLB_CC1_OPAMP0 = 6U , GLB_CC1_PORT0 = 7U , GLB_CC1_PORT1 = 8U ,
  GLB_CC1_PORT2 = 9U , GLB_CC1_PORT3 = 10U , GLB_CC1_PORT4 = 11U , GLB_CC1_FLEXCAN0 = 12U ,
  GLB_CC1_LPI2C2 = 13U , GLB_CC1_LPI2C3 = 14U , GLB_CC1_RAMA = 18U , GLB_CC1_RAMB = 19U ,
  GLB_CC1_GPIO0 = 20U , GLB_CC1_GPIO1 = 21U , GLB_CC1_GPIO2 = 22U , GLB_CC1_GPIO3 = 23U ,
  GLB_CC1_GPIO4 = 24U , GLB_CC1_ROMC = 25U , GLB_CC_SET_DATA = 0U , GLB_CC_CLR_DATA = 0U ,
  GLB_ACC0_INPUTMUX0 = 0U , GLB_ACC0_I3C0 = 1U , GLB_ACC0_CTIMER0 = 2U , GLB_ACC0_CTIMER1 = 3U ,
  GLB_ACC0_CTIMER2 = 4U , GLB_ACC0_CTIMER3 = 5U , GLB_ACC0_CTIMER4 = 6U , GLB_ACC0_FREQME = 7U ,
  GLB_ACC0_UTICK0 = 8U , GLB_ACC0_WWDT0 = 9U , GLB_ACC0_DMA = 10U , GLB_ACC0_AOI0 = 11U ,
  GLB_ACC0_CRC0 = 12U , GLB_ACC0_EIM0 = 13U , GLB_ACC0_ERM0 = 14U , GLB_ACC0_FMC = 15U ,
  GLB_ACC0_AOI1 = 16U , GLB_ACC0_FLEXIO0 = 17U , GLB_ACC0_LPI2C0 = 18U , GLB_ACC0_LPI2C1 = 19U ,
  GLB_ACC0_LPSPI0 = 20U , GLB_ACC0_LPSPI1 = 21U , GLB_ACC0_LPUART0 = 22U , GLB_ACC0_LPUART1 = 23U ,
  GLB_ACC0_LPUART2 = 24U , GLB_ACC0_LPUART3 = 25U , GLB_ACC0_LPUART4 = 26U , GLB_ACC0_USB0 = 27U ,
  GLB_ACC0_QDC0 = 28U , GLB_ACC0_QDC1 = 29U , GLB_ACC0_FLEXPWM0 = 30U , GLB_ACC0_FLEXPWM1 = 31U ,
  GLB_ACC1_OSTIMER0 = 0U , GLB_ACC1_ADC0 = 1U , GLB_ACC1_ADC1 = 2U , GLB_ACC1_CMP0 = 3U ,
  GLB_ACC1_CMP1 = 4U , GLB_ACC1_DAC0 = 5U , GLB_ACC1_OPAMP0 = 6U , GLB_ACC1_PORT0 = 7U ,
  GLB_ACC1_PORT1 = 8U , GLB_ACC1_PORT2 = 9U , GLB_ACC1_PORT3 = 10U , GLB_ACC1_PORT4 = 11U ,
  GLB_ACC1_FLEXCAN0 = 12U , GLB_ACC1_LPI2C2 = 13U , GLB_ACC1_LPI2C3 = 14U , GLB_ACC1_RAMA = 18U ,
  GLB_ACC1_RAMB = 19U , GLB_ACC1_GPIO0 = 20U , GLB_ACC1_GPIO1 = 21U , GLB_ACC1_GPIO2 = 22U ,
  GLB_ACC1_GPIO3 = 23U , GLB_ACC1_GPIO4 = 24U , GLB_ACC1_ROMC = 25U , I3C0_FCLK_CLKSEL_MUX = 0U ,
  I3C0_FCLK_CLKDIV_DIV = 0U , I3C0_FCLK_CLKDIV_RESET = 29U , I3C0_FCLK_CLKDIV_HALT = 30U , I3C0_FCLK_CLKDIV_UNSTAB = 31U ,
  CTIMER0_CLKSEL_MUX = 0U , CTIMER0_CLKDIV_DIV = 0U , CTIMER0_CLKDIV_RESET = 29U , CTIMER0_CLKDIV_HALT = 30U ,
  CTIMER0_CLKDIV_UNSTAB = 31U , CTIMER1_CLKSEL_MUX = 0U , CTIMER1_CLKDIV_DIV = 0U , CTIMER1_CLKDIV_RESET = 29U ,
  CTIMER1_CLKDIV_HALT = 30U , CTIMER1_CLKDIV_UNSTAB = 31U , CTIMER2_CLKSEL_MUX = 0U , CTIMER2_CLKDIV_DIV = 0U ,
  CTIMER2_CLKDIV_RESET = 29U , CTIMER2_CLKDIV_HALT = 30U , CTIMER2_CLKDIV_UNSTAB = 31U , CTIMER3_CLKSEL_MUX = 0U ,
  CTIMER3_CLKDIV_DIV = 0U , CTIMER3_CLKDIV_RESET = 29U , CTIMER3_CLKDIV_HALT = 30U , CTIMER3_CLKDIV_UNSTAB = 31U ,
  CTIMER4_CLKSEL_MUX = 0U , CTIMER4_CLKDIV_DIV = 0U , CTIMER4_CLKDIV_RESET = 29U , CTIMER4_CLKDIV_HALT = 30U ,
  CTIMER4_CLKDIV_UNSTAB = 31U , WWDT0_CLKDIV_DIV = 0U , WWDT0_CLKDIV_RESET = 29U , WWDT0_CLKDIV_HALT = 30U ,
  WWDT0_CLKDIV_UNSTAB = 31U , FLEXIO0_CLKSEL_MUX = 0U , FLEXIO0_CLKDIV_DIV = 0U , FLEXIO0_CLKDIV_RESET = 29U ,
  FLEXIO0_CLKDIV_HALT = 30U , FLEXIO0_CLKDIV_UNSTAB = 31U , LPI2C0_CLKSEL_MUX = 0U , LPI2C0_CLKDIV_DIV = 0U ,
  LPI2C0_CLKDIV_RESET = 29U , LPI2C0_CLKDIV_HALT = 30U , LPI2C0_CLKDIV_UNSTAB = 31U , LPI2C1_CLKSEL_MUX = 0U ,
  LPI2C1_CLKDIV_DIV = 0U , LPI2C1_CLKDIV_RESET = 29U , LPI2C1_CLKDIV_HALT = 30U , LPI2C1_CLKDIV_UNSTAB = 31U ,
  LPSPI0_CLKSEL_MUX = 0U , LPSPI0_CLKDIV_DIV = 0U , LPSPI0_CLKDIV_RESET = 29U , LPSPI0_CLKDIV_HALT = 30U ,
  LPSPI0_CLKDIV_UNSTAB = 31U , LPSPI1_CLKSEL_MUX = 0U , LPSPI1_CLKDIV_DIV = 0U , LPSPI1_CLKDIV_RESET = 29U ,
  LPSPI1_CLKDIV_HALT = 30U , LPSPI1_CLKDIV_UNSTAB = 31U , LPUART0_CLKSEL_MUX = 0U , LPUART0_CLKDIV_DIV = 0U ,
  LPUART0_CLKDIV_RESET = 29U , LPUART0_CLKDIV_HALT = 30U , LPUART0_CLKDIV_UNSTAB = 31U , LPUART1_CLKSEL_MUX = 0U ,
  LPUART1_CLKDIV_DIV = 0U , LPUART1_CLKDIV_RESET = 29U , LPUART1_CLKDIV_HALT = 30U , LPUART1_CLKDIV_UNSTAB = 31U ,
  LPUART2_CLKSEL_MUX = 0U , LPUART2_CLKDIV_DIV = 0U , LPUART2_CLKDIV_RESET = 29U , LPUART2_CLKDIV_HALT = 30U ,
  LPUART2_CLKDIV_UNSTAB = 31U , LPUART3_CLKSEL_MUX = 0U , LPUART3_CLKDIV_DIV = 0U , LPUART3_CLKDIV_RESET = 29U ,
  LPUART3_CLKDIV_HALT = 30U , LPUART3_CLKDIV_UNSTAB = 31U , LPUART4_CLKSEL_MUX = 0U , LPUART4_CLKDIV_DIV = 0U ,
  LPUART4_CLKDIV_RESET = 29U , LPUART4_CLKDIV_HALT = 30U , LPUART4_CLKDIV_UNSTAB = 31U , USB0_CLKSEL_MUX = 0U ,
  LPTMR0_CLKSEL_MUX = 0U , LPTMR0_CLKDIV_DIV = 0U , LPTMR0_CLKDIV_RESET = 29U , LPTMR0_CLKDIV_HALT = 30U ,
  LPTMR0_CLKDIV_UNSTAB = 31U , OSTIMER0_CLKSEL_MUX = 0U , ADC0_CLKSEL_MUX = 0U , ADC0_CLKDIV_DIV = 0U ,
  ADC0_CLKDIV_RESET = 29U , ADC0_CLKDIV_HALT = 30U , ADC0_CLKDIV_UNSTAB = 31U , ADC1_CLKSEL_MUX = 0U ,
  ADC1_CLKDIV_DIV = 0U , ADC1_CLKDIV_RESET = 29U , ADC1_CLKDIV_HALT = 30U , ADC1_CLKDIV_UNSTAB = 31U ,
  CMP0_FUNC_CLKDIV_DIV = 0U , CMP0_FUNC_CLKDIV_RESET = 29U , CMP0_FUNC_CLKDIV_HALT = 30U , CMP0_FUNC_CLKDIV_UNSTAB = 31U ,
  CMP0_RR_CLKSEL_MUX = 0U , CMP0_RR_CLKDIV_DIV = 0U , CMP0_RR_CLKDIV_RESET = 29U , CMP0_RR_CLKDIV_HALT = 30U ,
  CMP0_RR_CLKDIV_UNSTAB = 31U , CMP1_FUNC_CLKDIV_DIV = 0U , CMP1_FUNC_CLKDIV_RESET = 29U , CMP1_FUNC_CLKDIV_HALT = 30U ,
  CMP1_FUNC_CLKDIV_UNSTAB = 31U , CMP1_RR_CLKSEL_MUX = 0U , CMP1_RR_CLKDIV_DIV = 0U , CMP1_RR_CLKDIV_RESET = 29U ,
  CMP1_RR_CLKDIV_HALT = 30U , CMP1_RR_CLKDIV_UNSTAB = 31U , DAC0_CLKSEL_MUX = 0U , DAC0_CLKDIV_DIV = 0U ,
  DAC0_CLKDIV_RESET = 29U , DAC0_CLKDIV_HALT = 30U , DAC0_CLKDIV_UNSTAB = 31U , FLEXCAN0_CLKSEL_MUX = 0U ,
  FLEXCAN0_CLKDIV_DIV = 0U , FLEXCAN0_CLKDIV_RESET = 29U , FLEXCAN0_CLKDIV_HALT = 30U , FLEXCAN0_CLKDIV_UNSTAB = 31U ,
  LPI2C2_CLKSEL_MUX = 0U , LPI2C2_CLKDIV_DIV = 0U , LPI2C2_CLKDIV_RESET = 29U , LPI2C2_CLKDIV_HALT = 30U ,
  LPI2C2_CLKDIV_UNSTAB = 31U , LPI2C3_CLKSEL_MUX = 0U , LPI2C3_CLKDIV_DIV = 0U , LPI2C3_CLKDIV_RESET = 29U ,
  LPI2C3_CLKDIV_HALT = 30U , LPI2C3_CLKDIV_UNSTAB = 31U , DBG_TRACE_CLKSEL_MUX = 0U , DBG_TRACE_CLKDIV_DIV = 0U ,
  DBG_TRACE_CLKDIV_RESET = 29U , DBG_TRACE_CLKDIV_HALT = 30U , DBG_TRACE_CLKDIV_UNSTAB = 31U , CLKOUT_CLKSEL_MUX = 0U ,
  CLKOUT_CLKDIV_DIV = 0U , CLKOUT_CLKDIV_RESET = 29U , CLKOUT_CLKDIV_HALT = 30U , CLKOUT_CLKDIV_UNSTAB = 31U ,
  SYSTICK_CLKSEL_MUX = 0U , SYSTICK_CLKDIV_DIV = 0U , SYSTICK_CLKDIV_RESET = 29U , SYSTICK_CLKDIV_HALT = 30U ,
  SYSTICK_CLKDIV_UNSTAB = 31U , FRO_HF_DIV_CLKDIV_DIV = 0U , FRO_HF_DIV_CLKDIV_UNSTAB = 31U
}
 

函式

constexpr unsigned int operator+ (Count e)
 
constexpr unsigned int operator+ (Mask e)
 
constexpr unsigned int operator+ (Shift e)
 

變數

Register & MRCC0
 

詳細描述

Copyright (c) 2020 ZxyKira All rights reserved.

SPDX-License-Identifier: MIT

列舉型態說明文件

◆ Count

enum struct chip::mrcc::Count : unsigned int
strong
列舉值
MRCC_GLB_CC_SET 

MRCC_GLB_CC_SET - MRCC_GLB_CC_SET.

AHB Clock Control Set 1 - The count of MRCC_GLB_CC_SET

MRCC_GLB_CC_CLR 

MRCC_GLB_CC_CLR - MRCC_GLB_CC_CLR.

AHB Clock Control Clear 1 - The count of MRCC_GLB_CC_CLR

◆ Mask

enum struct chip::mrcc::Mask : unsigned int
strong

MRCC_Register_Masks MRCC Register Masks.

列舉值
GLB_RST0_INPUTMUX0 

MRCC_GLB_RST0 - INPUTMUX0.

Peripheral Reset Control 0 - INPUTMUX0

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_I3C0 

MRCC_GLB_RST0 - I3C0.

Peripheral Reset Control 0 - I3C0

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_CTIMER0 

MRCC_GLB_RST0 - CTIMER0.

Peripheral Reset Control 0 - CTIMER0

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_CTIMER1 

MRCC_GLB_RST0 - CTIMER1.

Peripheral Reset Control 0 - CTIMER1

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_CTIMER2 

MRCC_GLB_RST0 - CTIMER2.

Peripheral Reset Control 0 - CTIMER2

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_CTIMER3 

MRCC_GLB_RST0 - CTIMER3.

Peripheral Reset Control 0 - CTIMER3

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_CTIMER4 

MRCC_GLB_RST0 - CTIMER4.

Peripheral Reset Control 0 - CTIMER4

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_FREQME 

MRCC_GLB_RST0 - FREQME.

Peripheral Reset Control 0 - FREQME

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_UTICK0 

MRCC_GLB_RST0 - UTICK0.

Peripheral Reset Control 0 - UTICK0

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_DMA 

MRCC_GLB_RST0 - DMA.

Peripheral Reset Control 0 - DMA

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_AOI0 

MRCC_GLB_RST0 - AOI0.

Peripheral Reset Control 0 - AOI0

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_CRC0 

MRCC_GLB_RST0 - CRC0.

Peripheral Reset Control 0 - CRC0

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_EIM0 

MRCC_GLB_RST0 - EIM0.

Peripheral Reset Control 0 - EIM0

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_ERM0 

MRCC_GLB_RST0 - ERM0.

Peripheral Reset Control 0 - ERM0

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_AOI1 

MRCC_GLB_RST0 - AOI1.

Peripheral Reset Control 0 - AOI1

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_FLEXIO0 

MRCC_GLB_RST0 - FLEXIO0.

Peripheral Reset Control 0 - FLEXIO0

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_LPI2C0 

MRCC_GLB_RST0 - LPI2C0.

Peripheral Reset Control 0 - LPI2C0

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_LPI2C1 

MRCC_GLB_RST0 - LPI2C1.

Peripheral Reset Control 0 - LPI2C1

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_LPSPI0 

MRCC_GLB_RST0 - LPSPI0.

Peripheral Reset Control 0 - LPSPI0

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_LPSPI1 

MRCC_GLB_RST0 - LPSPI1.

Peripheral Reset Control 0 - LPSPI1

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_LPUART0 

MRCC_GLB_RST0 - LPUART0.

Peripheral Reset Control 0 - LPUART0

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_LPUART1 

MRCC_GLB_RST0 - LPUART1.

Peripheral Reset Control 0 - LPUART1

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_LPUART2 

MRCC_GLB_RST0 - LPUART2.

Peripheral Reset Control 0 - LPUART2

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_LPUART3 

MRCC_GLB_RST0 - LPUART3.

Peripheral Reset Control 0 - LPUART3

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_LPUART4 

MRCC_GLB_RST0 - LPUART4.

Peripheral Reset Control 0 - LPUART4

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_USB0 

MRCC_GLB_RST0 - USB0.

Peripheral Reset Control 0 - USB0

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_QDC0 

MRCC_GLB_RST0 - QDC0.

Peripheral Reset Control 0 - QDC0

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_QDC1 

MRCC_GLB_RST0 - QDC1.

Peripheral Reset Control 0 - QDC1

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_FLEXPWM0 

MRCC_GLB_RST0 - FLEXPWM0.

Peripheral Reset Control 0 - FLEXPWM0

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_FLEXPWM1 

MRCC_GLB_RST0 - FLEXPWM1.

Peripheral Reset Control 0 - FLEXPWM1

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_SET_DATA 

MRCC_GLB_RST0_SET - DATA.

Peripheral Reset Control Set 0 - Data array value, refer to corresponding position in MRCC_GLB_RSTn.

GLB_RST0_CLR_DATA 

MRCC_GLB_RST0_CLR - DATA.

Peripheral Reset Control Clear 0 - Data array value, refer to corresponding position in MRCC_GLB_RSTn.

GLB_RST1_OSTIMER0 

MRCC_GLB_RST1 - OSTIMER0.

Peripheral Reset Control 1 - OSTIMER0

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST1_ADC0 

MRCC_GLB_RST1 - ADC0.

Peripheral Reset Control 1 - ADC0

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST1_ADC1 

MRCC_GLB_RST1 - ADC1.

Peripheral Reset Control 1 - ADC1

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST1_CMP1 

MRCC_GLB_RST1 - CMP1.

Peripheral Reset Control 1 - CMP1

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST1_DAC0 

MRCC_GLB_RST1 - DAC0.

Peripheral Reset Control 1 - DAC0

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST1_OPAMP0 

MRCC_GLB_RST1 - OPAMP0.

Peripheral Reset Control 1 - OPAMP0

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST1_PORT0 

MRCC_GLB_RST1 - PORT0.

Peripheral Reset Control 1 - PORT0

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST1_PORT1 

MRCC_GLB_RST1 - PORT1.

Peripheral Reset Control 1 - PORT1

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST1_PORT2 

MRCC_GLB_RST1 - PORT2.

Peripheral Reset Control 1 - PORT2

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST1_PORT3 

MRCC_GLB_RST1 - PORT3.

Peripheral Reset Control 1 - PORT3

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST1_PORT4 

MRCC_GLB_RST1 - PORT4.

Peripheral Reset Control 1 - PORT4

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST1_FLEXCAN0 

MRCC_GLB_RST1 - FLEXCAN0.

Peripheral Reset Control 1 - FLEXCAN0

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST1_LPI2C2 

MRCC_GLB_RST1 - LPI2C2.

Peripheral Reset Control 1 - LPI2C2

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST1_LPI2C3 

MRCC_GLB_RST1 - LPI2C3.

Peripheral Reset Control 1 - LPI2C3

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST1_GPIO0 

MRCC_GLB_RST1 - GPIO0.

Peripheral Reset Control 1 - GPIO0

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST1_GPIO1 

MRCC_GLB_RST1 - GPIO1.

Peripheral Reset Control 1 - GPIO1

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST1_GPIO2 

MRCC_GLB_RST1 - GPIO2.

Peripheral Reset Control 1 - GPIO2

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST1_GPIO3 

MRCC_GLB_RST1 - GPIO3.

Peripheral Reset Control 1 - GPIO3

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST1_GPIO4 

MRCC_GLB_RST1 - GPIO4.

Peripheral Reset Control 1 - GPIO4

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST1_SET_DATA 

MRCC_GLB_RST1_SET - DATA.

Peripheral Reset Control Set 1 - Data array value, refer to corresponding position in MRCC_GLB_RSTn.

GLB_RST1_CLR_DATA 

MRCC_GLB_RST1_CLR - DATA.

Peripheral Reset Control Clear 1 - Data array value, refer to corresponding position in MRCC_GLB_RSTn.

GLB_CC0_INPUTMUX0 

MRCC_GLB_CC0 - INPUTMUX0.

AHB Clock Control 0 - INPUTMUX0

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_I3C0 

MRCC_GLB_CC0 - I3C0.

AHB Clock Control 0 - I3C0

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_CTIMER0 

MRCC_GLB_CC0 - CTIMER0.

AHB Clock Control 0 - CTIMER0

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_CTIMER1 

MRCC_GLB_CC0 - CTIMER1.

AHB Clock Control 0 - CTIMER1

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_CTIMER2 

MRCC_GLB_CC0 - CTIMER2.

AHB Clock Control 0 - CTIMER2

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_CTIMER3 

MRCC_GLB_CC0 - CTIMER3.

AHB Clock Control 0 - CTIMER3

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_CTIMER4 

MRCC_GLB_CC0 - CTIMER4.

AHB Clock Control 0 - CTIMER4

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_FREQME 

MRCC_GLB_CC0 - FREQME.

AHB Clock Control 0 - FREQME

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_UTICK0 

MRCC_GLB_CC0 - UTICK0.

AHB Clock Control 0 - UTICK0

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_WWDT0 

MRCC_GLB_CC0 - WWDT0.

AHB Clock Control 0 - WWDT0

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_DMA 

MRCC_GLB_CC0 - DMA.

AHB Clock Control 0 - DMA

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_AOI0 

MRCC_GLB_CC0 - AOI0.

AHB Clock Control 0 - AOI0

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_CRC0 

MRCC_GLB_CC0 - CRC0.

AHB Clock Control 0 - CRC0

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_EIM0 

MRCC_GLB_CC0 - EIM0.

AHB Clock Control 0 - EIM0

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_ERM0 

MRCC_GLB_CC0 - ERM0.

AHB Clock Control 0 - ERM0

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_FMC 

MRCC_GLB_CC0 - FMC.

AHB Clock Control 0 - FMC

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_AOI1 

MRCC_GLB_CC0 - AOI1.

AHB Clock Control 0 - AOI1

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_FLEXIO0 

MRCC_GLB_CC0 - FLEXIO0.

AHB Clock Control 0 - FLEXIO0

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_LPI2C0 

MRCC_GLB_CC0 - LPI2C0.

AHB Clock Control 0 - LPI2C0

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_LPI2C1 

MRCC_GLB_CC0 - LPI2C1.

AHB Clock Control 0 - LPI2C1

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_LPSPI0 

MRCC_GLB_CC0 - LPSPI0.

AHB Clock Control 0 - LPSPI0

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_LPSPI1 

MRCC_GLB_CC0 - LPSPI1.

AHB Clock Control 0 - LPSPI1

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_LPUART0 

MRCC_GLB_CC0 - LPUART0.

AHB Clock Control 0 - LPUART0

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_LPUART1 

MRCC_GLB_CC0 - LPUART1.

AHB Clock Control 0 - LPUART1

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_LPUART2 

MRCC_GLB_CC0 - LPUART2.

AHB Clock Control 0 - LPUART2

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_LPUART3 

MRCC_GLB_CC0 - LPUART3.

AHB Clock Control 0 - LPUART3

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_LPUART4 

MRCC_GLB_CC0 - LPUART4.

AHB Clock Control 0 - LPUART4

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_USB0 

MRCC_GLB_CC0 - USB0.

AHB Clock Control 0 - USB0

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_QDC0 

MRCC_GLB_CC0 - QDC0.

AHB Clock Control 0 - QDC0

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_QDC1 

MRCC_GLB_CC0 - QDC1.

AHB Clock Control 0 - QDC1

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_FLEXPWM0 

MRCC_GLB_CC0 - FLEXPWM0.

AHB Clock Control 0 - FLEXPWM0

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_FLEXPWM1 

MRCC_GLB_CC0 - FLEXPWM1.

AHB Clock Control 0 - FLEXPWM1

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_SET_DATA 

MRCC_GLB_CC0_SET - DATA.

AHB Clock Control Set 0 - Data array value, refer to corresponding position in MRCC_GLB_CCn.

GLB_CC0_CLR_DATA 

MRCC_GLB_CC0_CLR - DATA.

AHB Clock Control Clear 0 - Data array value, refer to corresponding position in MRCC_GLB_CCn.

GLB_CC1_OSTIMER0 

MRCC_GLB_CC1 - OSTIMER0.

AHB Clock Control 1 - OSTIMER0

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC1_ADC0 

MRCC_GLB_CC1 - ADC0.

AHB Clock Control 1 - ADC0

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC1_ADC1 

MRCC_GLB_CC1 - ADC1.

AHB Clock Control 1 - ADC1

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC1_CMP0 

MRCC_GLB_CC1 - CMP0.

AHB Clock Control 1 - CMP0

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC1_CMP1 

MRCC_GLB_CC1 - CMP1.

AHB Clock Control 1 - CMP1

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC1_DAC0 

MRCC_GLB_CC1 - DAC0.

AHB Clock Control 1 - DAC0

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC1_OPAMP0 

MRCC_GLB_CC1 - OPAMP0.

AHB Clock Control 1 - OPAMP0

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC1_PORT0 

MRCC_GLB_CC1 - PORT0.

AHB Clock Control 1 - PORT0

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC1_PORT1 

MRCC_GLB_CC1 - PORT1.

AHB Clock Control 1

AHB Clock Control 1 - PORT1

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC1_PORT2 

MRCC_GLB_CC1 - PORT2.

AHB Clock Control 1 - PORT2

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC1_PORT3 

MRCC_GLB_CC1 - PORT3.

AHB Clock Control 1 - PORT3

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC1_PORT4 

MRCC_GLB_CC1 - PORT4.

AHB Clock Control 1 - PORT4

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC1_FLEXCAN0 

MRCC_GLB_CC1 - FLEXCAN0.

AHB Clock Control 1 - FLEXCAN0

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC1_LPI2C2 

MRCC_GLB_CC1 - LPI2C2.

AHB Clock Control 1 - LPI2C2

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC1_LPI2C3 

MRCC_GLB_CC1 - LPI2C3.

AHB Clock Control 1 - LPI2C3

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC1_RAMA 

MRCC_GLB_CC1 - RAMA.

AHB Clock Control 1 - RAMA

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC1_RAMB 

MRCC_GLB_CC1 - RAMB.

AHB Clock Control 1 - RAMB

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC1_GPIO0 

MRCC_GLB_CC1 - GPIO0.

AHB Clock Control 1 - GPIO0

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC1_GPIO1 

MRCC_GLB_CC1 - GPIO1.

AHB Clock Control 1 - GPIO1

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC1_GPIO2 

MRCC_GLB_CC1 - GPIO2.

AHB Clock Control 1 - GPIO2

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC1_GPIO3 

MRCC_GLB_CC1 - GPIO3.

AHB Clock Control 1 - GPIO3

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC1_GPIO4 

MRCC_GLB_CC1 - GPIO4.

AHB Clock Control 1 - GPIO4

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC1_ROMC 

MRCC_GLB_CC1 - ROMC.

AHB Clock Control 1 - ROMC

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC_SET_DATA 

MRCC_GLB_CC_SET - DATA.

AHB Clock Control Set 1 - Data array value, refer to corresponding position in MRCC_GLB_CCn.

GLB_CC_CLR_DATA 

MRCC_GLB_CC_CLR - DATA.

AHB Clock Control Clear 1 - Data array value, refer to corresponding position in MRCC_GLB_CCn.

GLB_ACC0_INPUTMUX0 

MRCC_GLB_ACC0 - INPUTMUX0.

Control Automatic Clock Gating 0 - INPUTMUX0

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_I3C0 

MRCC_GLB_ACC0 - I3C0.

Control Automatic Clock Gating 0 - I3C0

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_CTIMER0 

MRCC_GLB_ACC0 - CTIMER0.

Control Automatic Clock Gating 0 - CTIMER0

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_CTIMER1 

MRCC_GLB_ACC0 - CTIMER1.

Control Automatic Clock Gating 0 - CTIMER1

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_CTIMER2 

MRCC_GLB_ACC0 - CTIMER2.

Control Automatic Clock Gating 0 - CTIMER2

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_CTIMER3 

MRCC_GLB_ACC0 - CTIMER3.

Control Automatic Clock Gating 0 - CTIMER3

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_CTIMER4 

MRCC_GLB_ACC0 - CTIMER4.

Control Automatic Clock Gating 0 - CTIMER4

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_FREQME 

MRCC_GLB_ACC0 - FREQME.

Control Automatic Clock Gating 0 - FREQME

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_UTICK0 

MRCC_GLB_ACC0 - UTICK0.

Control Automatic Clock Gating 0 - UTICK0

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_WWDT0 

MRCC_GLB_ACC0 - WWDT0.

Control Automatic Clock Gating 0 - WWDT0

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_DMA 

MRCC_GLB_ACC0 - DMA.

Control Automatic Clock Gating 0 - DMA

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_AOI0 

MRCC_GLB_ACC0 - AOI0.

Control Automatic Clock Gating 0 - AOI0

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_CRC0 

MRCC_GLB_ACC0 - CRC0.

Control Automatic Clock Gating 0 - CRC0

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_EIM0 

MRCC_GLB_ACC0 - EIM0.

Control Automatic Clock Gating 0 - EIM0

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_ERM0 

MRCC_GLB_ACC0 - ERM0.

Control Automatic Clock Gating 0 - ERM0

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_FMC 

MRCC_GLB_ACC0 - FMC.

Control Automatic Clock Gating 0 - FMC

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_AOI1 

MRCC_GLB_ACC0 - AOI1.

Control Automatic Clock Gating 0 - AOI1

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_FLEXIO0 

MRCC_GLB_ACC0 - FLEXIO0.

Control Automatic Clock Gating 0 - FLEXIO0

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_LPI2C0 

MRCC_GLB_ACC0 - LPI2C0.

Control Automatic Clock Gating 0 - LPI2C0

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_LPI2C1 

MRCC_GLB_ACC0 - LPI2C1.

Control Automatic Clock Gating 0 - LPI2C1

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_LPSPI0 

MRCC_GLB_ACC0 - LPSPI0.

Control Automatic Clock Gating 0 - LPSPI0

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_LPSPI1 

MRCC_GLB_ACC0 - LPSPI1.

Control Automatic Clock Gating 0 - LPSPI1

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_LPUART0 

MRCC_GLB_ACC0 - LPUART0.

Control Automatic Clock Gating 0 - LPUART0

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_LPUART1 

MRCC_GLB_ACC0 - LPUART1.

Control Automatic Clock Gating 0 - LPUART1

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_LPUART2 

MRCC_GLB_ACC0 - LPUART2.

Control Automatic Clock Gating 0 - LPUART2

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_LPUART3 

MRCC_GLB_ACC0 - LPUART3.

Control Automatic Clock Gating 0 - LPUART3

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_LPUART4 

MRCC_GLB_ACC0 - LPUART4.

Control Automatic Clock Gating 0 - LPUART4

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_USB0 

MRCC_GLB_ACC0 - USB0.

Control Automatic Clock Gating 0 - USB0

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_QDC0 

MRCC_GLB_ACC0 - QDC0.

Control Automatic Clock Gating 0 - QDC0

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_QDC1 

MRCC_GLB_ACC0 - QDC1.

Control Automatic Clock Gating 0 - QDC1

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_FLEXPWM0 

MRCC_GLB_ACC0 - FLEXPWM0.

Control Automatic Clock Gating 0 - FLEXPWM0

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_FLEXPWM1 

MRCC_GLB_ACC0 - FLEXPWM1.

Control Automatic Clock Gating 0 - FLEXPWM1

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC1_OSTIMER0 

MRCC_GLB_ACC1 - OSTIMER0.

Control Automatic Clock Gating 1 - OSTIMER0

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC1_ADC0 

MRCC_GLB_ACC1 - ADC0.

Control Automatic Clock Gating 1 - ADC0

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC1_ADC1 

MRCC_GLB_ACC1 - ADC1.

Control Automatic Clock Gating 1 - ADC1

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC1_CMP0 

MRCC_GLB_ACC1 - CMP0.

Control Automatic Clock Gating 1 - CMP0

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC1_CMP1 

MRCC_GLB_ACC1 - CMP1.

Control Automatic Clock Gating 1 - CMP1

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC1_DAC0 

MRCC_GLB_ACC1 - DAC0.

Control Automatic Clock Gating 1 - DAC0

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC1_OPAMP0 

MRCC_GLB_ACC1 - OPAMP0.

Control Automatic Clock Gating 1 - OPAMP0

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC1_PORT0 

MRCC_GLB_ACC1 - PORT0.

Control Automatic Clock Gating 1 - PORT0

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC1_PORT1 

MRCC_GLB_ACC1 - PORT1.

Control Automatic Clock Gating 1 - PORT1

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC1_PORT2 

MRCC_GLB_ACC1 - PORT2.

Control Automatic Clock Gating 1 - PORT2

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC1_PORT3 

MRCC_GLB_ACC1 - PORT3.

Control Automatic Clock Gating 1 - PORT3

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC1_PORT4 

MRCC_GLB_ACC1 - PORT4.

Control Automatic Clock Gating 1 - PORT4

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC1_FLEXCAN0 

MRCC_GLB_ACC1 - FLEXCAN0.

Control Automatic Clock Gating 1 - FLEXCAN0

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC1_LPI2C2 

MRCC_GLB_ACC1 - LPI2C2.

Control Automatic Clock Gating 1 - LPI2C2

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC1_LPI2C3 

MRCC_GLB_ACC1 - LPI2C3.

Control Automatic Clock Gating 1 - LPI2C3

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC1_RAMA 

MRCC_GLB_ACC1 - RAMA.

Control Automatic Clock Gating 1 - RAMA

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC1_RAMB 

MRCC_GLB_ACC1 - RAMB.

Control Automatic Clock Gating 1 - RAMB

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC1_GPIO0 

MRCC_GLB_ACC1 - GPIO0.

Control Automatic Clock Gating 1 - GPIO0

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC1_GPIO1 

MRCC_GLB_ACC1 - GPIO1.

Control Automatic Clock Gating 1 - GPIO1

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC1_GPIO2 

MRCC_GLB_ACC1 - GPIO2.

Control Automatic Clock Gating 1 - GPIO2

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC1_GPIO3 

MRCC_GLB_ACC1 - GPIO3.

Control Automatic Clock Gating 1 - GPIO3

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC1_GPIO4 

MRCC_GLB_ACC1 - GPIO4.

Control Automatic Clock Gating 1 - GPIO4

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC1_ROMC 

MRCC_GLB_ACC1 - ROMC.

Control Automatic Clock Gating 1 - ROMC

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
I3C0_FCLK_CLKSEL_MUX 

MRCC_I3C0_FCLK_CLKSEL - MUX.

I3C0_FCLK clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b101]CLK_1M
  • [0b011]CLK_IN
  • [0b010]FRO_HF_DIV
  • [0b000]FRO_12M
I3C0_FCLK_CLKDIV_DIV 

MRCC_I3C0_FCLK_CLKDIV - DIV.

I3C0_FCLK clock divider control - Functional Clock Divider

I3C0_FCLK_CLKDIV_RESET 

MRCC_I3C0_FCLK_CLKDIV - RESET.

I3C0_FCLK clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
I3C0_FCLK_CLKDIV_HALT 

MRCC_I3C0_FCLK_CLKDIV - HALT.

I3C0_FCLK clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
I3C0_FCLK_CLKDIV_UNSTAB 

MRCC_I3C0_FCLK_CLKDIV - UNSTAB.

I3C0_FCLK clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
CTIMER0_CLKSEL_MUX 

MRCC_CTIMER0_CLKSEL - MUX.

CTIMER0 clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b101]CLK_1M
  • [0b100]CLK_16K
  • [0b011]CLK_IN
  • [0b001]FRO_HF_GATED
  • [0b000]FRO_12M
CTIMER0_CLKDIV_DIV 

MRCC_CTIMER0_CLKDIV - DIV.

CTIMER0 clock divider control - Functional Clock Divider

CTIMER0_CLKDIV_RESET 

MRCC_CTIMER0_CLKDIV - RESET.

CTIMER0 clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
CTIMER0_CLKDIV_HALT 

MRCC_CTIMER0_CLKDIV - HALT.

CTIMER0 clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
CTIMER0_CLKDIV_UNSTAB 

MRCC_CTIMER0_CLKDIV - UNSTAB.

CTIMER0 clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
CTIMER1_CLKSEL_MUX 

MRCC_CTIMER1_CLKSEL - MUX.

CTIMER1 clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b101]CLK_1M
  • [0b100]CLK_16K
  • [0b011]CLK_IN
  • [0b001]FRO_HF_GATED
  • [0b000]FRO_12M
CTIMER1_CLKDIV_DIV 

MRCC_CTIMER1_CLKDIV - DIV.

CTIMER1 clock divider control - Functional Clock Divider

CTIMER1_CLKDIV_RESET 

MRCC_CTIMER1_CLKDIV - RESET.

CTIMER1 clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
CTIMER1_CLKDIV_HALT 

MRCC_CTIMER1_CLKDIV - HALT.

CTIMER1 clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
CTIMER1_CLKDIV_UNSTAB 

MRCC_CTIMER1_CLKDIV - UNSTAB.

CTIMER1 clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
CTIMER2_CLKSEL_MUX 

MRCC_CTIMER2_CLKSEL - MUX.

CTIMER2 clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b101]CLK_1M
  • [0b100]CLK_16K
  • [0b011]CLK_IN
  • [0b001]FRO_HF_GATED
  • [0b000]FRO_12M
CTIMER2_CLKDIV_DIV 

MRCC_CTIMER2_CLKDIV - DIV.

CTIMER2 clock divider control - Functional Clock Divider

CTIMER2_CLKDIV_RESET 

MRCC_CTIMER2_CLKDIV - RESET.

CTIMER2 clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
CTIMER2_CLKDIV_HALT 

MRCC_CTIMER2_CLKDIV - HALT.

CTIMER2 clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
CTIMER2_CLKDIV_UNSTAB 

MRCC_CTIMER2_CLKDIV - UNSTAB.

CTIMER2 clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
CTIMER3_CLKSEL_MUX 

MRCC_CTIMER3_CLKSEL - MUX.

CTIMER3 clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b101]CLK_1M
  • [0b100]CLK_16K
  • [0b011]CLK_IN
  • [0b001]FRO_HF_GATED
  • [0b000]FRO_12M
CTIMER3_CLKDIV_DIV 

MRCC_CTIMER3_CLKDIV - DIV.

CTIMER3 clock divider control - Functional Clock Divider

CTIMER3_CLKDIV_RESET 

MRCC_CTIMER3_CLKDIV - RESET.

CTIMER3 clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
CTIMER3_CLKDIV_HALT 

MRCC_CTIMER3_CLKDIV - HALT.

CTIMER3 clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
CTIMER3_CLKDIV_UNSTAB 

MRCC_CTIMER3_CLKDIV - UNSTAB.

CTIMER3 clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
CTIMER4_CLKSEL_MUX 

MRCC_CTIMER4_CLKSEL - MUX.

CTIMER4 clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b101]CLK_1M
  • [0b100]CLK_16K
  • [0b011]CLK_IN
  • [0b001]FRO_HF_GATED
  • [0b000]FRO_12M
CTIMER4_CLKDIV_DIV 

MRCC_CTIMER4_CLKDIV - DIV.

CTIMER4 clock divider control - Functional Clock Divider

CTIMER4_CLKDIV_RESET 

MRCC_CTIMER4_CLKDIV - RESET.

CTIMER4 clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
CTIMER4_CLKDIV_HALT 

MRCC_CTIMER4_CLKDIV - HALT.

CTIMER4 clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
CTIMER4_CLKDIV_UNSTAB 

MRCC_CTIMER4_CLKDIV - UNSTAB.

CTIMER4 clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
WWDT0_CLKDIV_DIV 

MRCC_WWDT0_CLKDIV - DIV.

WWDT0 clock divider control - Functional Clock Divider

WWDT0_CLKDIV_RESET 

MRCC_WWDT0_CLKDIV - RESET.

WWDT0 clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
WWDT0_CLKDIV_HALT 

MRCC_WWDT0_CLKDIV - HALT.

WWDT0 clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
WWDT0_CLKDIV_UNSTAB 

MRCC_WWDT0_CLKDIV - UNSTAB.

WWDT0 clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
FLEXIO0_CLKSEL_MUX 

MRCC_FLEXIO0_CLKSEL - MUX.

FLEXIO0 clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b101]CLK_1M
  • [0b011]CLK_IN
  • [0b001]FRO_HF_GATED
  • [0b000]FRO_12M
FLEXIO0_CLKDIV_DIV 

MRCC_FLEXIO0_CLKDIV - DIV.

FLEXIO0 clock divider control - Functional Clock Divider

FLEXIO0_CLKDIV_RESET 

MRCC_FLEXIO0_CLKDIV - RESET.

FLEXIO0 clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
FLEXIO0_CLKDIV_HALT 

MRCC_FLEXIO0_CLKDIV - HALT.

FLEXIO0 clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
FLEXIO0_CLKDIV_UNSTAB 

MRCC_FLEXIO0_CLKDIV - UNSTAB.

FLEXIO0 clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
LPI2C0_CLKSEL_MUX 

MRCC_LPI2C0_CLKSEL - MUX.

LPI2C0 clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b101]CLK_1M
  • [0b011]CLK_IN
  • [0b010]FRO_HF_DIV
  • [0b000]FRO_12M
LPI2C0_CLKDIV_DIV 

MRCC_LPI2C0_CLKDIV - DIV.

LPI2C0 clock divider control - Functional Clock Divider

LPI2C0_CLKDIV_RESET 

MRCC_LPI2C0_CLKDIV - RESET.

LPI2C0 clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
LPI2C0_CLKDIV_HALT 

MRCC_LPI2C0_CLKDIV - HALT.

LPI2C0 clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
LPI2C0_CLKDIV_UNSTAB 

MRCC_LPI2C0_CLKDIV - UNSTAB.

LPI2C0 clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
LPI2C1_CLKSEL_MUX 

MRCC_LPI2C1_CLKSEL - MUX.

LPI2C1 clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b101]CLK_1M
  • [0b011]CLK_IN
  • [0b010]FRO_HF_DIV
  • [0b000]FRO_12M
LPI2C1_CLKDIV_DIV 

MRCC_LPI2C1_CLKDIV - DIV.

LPI2C1 clock divider control - Functional Clock Divider

LPI2C1_CLKDIV_RESET 

MRCC_LPI2C1_CLKDIV - RESET.

LPI2C1 clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
LPI2C1_CLKDIV_HALT 

MRCC_LPI2C1_CLKDIV - HALT.

LPI2C1 clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
LPI2C1_CLKDIV_UNSTAB 

MRCC_LPI2C1_CLKDIV - UNSTAB.

LPI2C1 clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
LPSPI0_CLKSEL_MUX 

MRCC_LPSPI0_CLKSEL - MUX.

LPSPI0 clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b101]CLK_1M
  • [0b011]CLK_IN
  • [0b010]FRO_HF_DIV
  • [0b000]FRO_12M
LPSPI0_CLKDIV_DIV 

MRCC_LPSPI0_CLKDIV - DIV.

LPSPI0 clock divider control - Functional Clock Divider

LPSPI0_CLKDIV_RESET 

MRCC_LPSPI0_CLKDIV - RESET.

LPSPI0 clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
LPSPI0_CLKDIV_HALT 

MRCC_LPSPI0_CLKDIV - HALT.

LPSPI0 clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
LPSPI0_CLKDIV_UNSTAB 

MRCC_LPSPI0_CLKDIV - UNSTAB.

LPSPI0 clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
LPSPI1_CLKSEL_MUX 

MRCC_LPSPI1_CLKSEL - MUX.

LPSPI1 clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b101]CLK_1M
  • [0b011]CLK_IN
  • [0b010]FRO_HF_DIV
  • [0b000]FRO_12M
LPSPI1_CLKDIV_DIV 

MRCC_LPSPI1_CLKDIV - DIV.

LPSPI1 clock divider control - Functional Clock Divider

LPSPI1_CLKDIV_RESET 

MRCC_LPSPI1_CLKDIV - RESET.

LPSPI1 clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
LPSPI1_CLKDIV_HALT 

MRCC_LPSPI1_CLKDIV - HALT.

LPSPI1 clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
LPSPI1_CLKDIV_UNSTAB 

MRCC_LPSPI1_CLKDIV - UNSTAB.

LPSPI1 clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
LPUART0_CLKSEL_MUX 

MRCC_LPUART0_CLKSEL - MUX.

LPUART0 clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b101]CLK_1M
  • [0b100]CLK_16K
  • [0b011]CLK_IN
  • [0b010]FRO_HF_DIV
  • [0b000]FRO_12M
LPUART0_CLKDIV_DIV 

MRCC_LPUART0_CLKDIV - DIV.

LPUART0 clock divider control - Functional Clock Divider

LPUART0_CLKDIV_RESET 

MRCC_LPUART0_CLKDIV - RESET.

LPUART0 clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
LPUART0_CLKDIV_HALT 

MRCC_LPUART0_CLKDIV - HALT.

LPUART0 clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
LPUART0_CLKDIV_UNSTAB 

MRCC_LPUART0_CLKDIV - UNSTAB.

LPUART0 clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
LPUART1_CLKSEL_MUX 

MRCC_LPUART1_CLKSEL - MUX.

LPUART1 clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b101]CLK_1M
  • [0b100]CLK_16K
  • [0b011]CLK_IN
  • [0b010]FRO_HF_DIV
  • [0b000]FRO_12M
LPUART1_CLKDIV_DIV 

MRCC_LPUART1_CLKDIV - DIV.

LPUART1 clock divider control - Functional Clock Divider

LPUART1_CLKDIV_RESET 

MRCC_LPUART1_CLKDIV - RESET.

LPUART1 clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
LPUART1_CLKDIV_HALT 

MRCC_LPUART1_CLKDIV - HALT.

LPUART1 clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
LPUART1_CLKDIV_UNSTAB 

MRCC_LPUART1_CLKDIV - UNSTAB.

LPUART1 clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
LPUART2_CLKSEL_MUX 

MRCC_LPUART2_CLKSEL - MUX.

LPUART2 clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b101]CLK_1M
  • [0b100]CLK_16K
  • [0b011]CLK_IN
  • [0b010]FRO_HF_DIV
  • [0b000]FRO_12M
LPUART2_CLKDIV_DIV 

MRCC_LPUART2_CLKDIV - DIV.

LPUART2 clock divider control - Functional Clock Divider

LPUART2_CLKDIV_RESET 

MRCC_LPUART2_CLKDIV - RESET.

LPUART2 clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
LPUART2_CLKDIV_HALT 

MRCC_LPUART2_CLKDIV - HALT.

LPUART2 clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
LPUART2_CLKDIV_UNSTAB 

MRCC_LPUART2_CLKDIV - UNSTAB.

LPUART2 clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
LPUART3_CLKSEL_MUX 

MRCC_LPUART3_CLKSEL - MUX.

LPUART3 clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b101]CLK_1M
  • [0b100]CLK_16K
  • [0b011]CLK_IN
  • [0b010]FRO_HF_DIV
  • [0b000]FRO_12M
LPUART3_CLKDIV_DIV 

MRCC_LPUART3_CLKDIV - DIV.

LPUART3 clock divider control - Functional Clock Divider

LPUART3_CLKDIV_RESET 

MRCC_LPUART3_CLKDIV - RESET.

LPUART3 clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
LPUART3_CLKDIV_HALT 

MRCC_LPUART3_CLKDIV - HALT.

LPUART3 clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
LPUART3_CLKDIV_UNSTAB 

MRCC_LPUART3_CLKDIV - UNSTAB.

LPUART3 clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
LPUART4_CLKSEL_MUX 

MRCC_LPUART4_CLKSEL - MUX.

LPUART4 clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b101]CLK_1M
  • [0b100]CLK_16K
  • [0b011]CLK_IN
  • [0b010]FRO_HF_DIV
  • [0b000]FRO_12M
LPUART4_CLKDIV_DIV 

MRCC_LPUART4_CLKDIV - DIV.

LPUART4 clock divider control - Functional Clock Divider

LPUART4_CLKDIV_RESET 

MRCC_LPUART4_CLKDIV - RESET.

LPUART4 clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
LPUART4_CLKDIV_HALT 

MRCC_LPUART4_CLKDIV - HALT.

LPUART4 clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
LPUART4_CLKDIV_UNSTAB 

MRCC_LPUART4_CLKDIV - UNSTAB.

LPUART4 clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
USB0_CLKSEL_MUX 

MRCC_USB0_CLKSEL - MUX.

USB0 clock selection control - Functional Clock Mux Select

  • [0b11]Reserved(NO Clock)
  • [0b10]CLK_IN
  • [0b01]CLK_48M
LPTMR0_CLKSEL_MUX 

MRCC_LPTMR0_CLKSEL - MUX.

LPTMR0 clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b101]CLK_1M
  • [0b011]CLK_IN
  • [0b010]FRO_HF_DIV
  • [0b000]FRO_12M
LPTMR0_CLKDIV_DIV 

MRCC_LPTMR0_CLKDIV - DIV.

LPTMR0 clock divider control - Functional Clock Divider

LPTMR0_CLKDIV_RESET 

MRCC_LPTMR0_CLKDIV - RESET.

LPTMR0 clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
LPTMR0_CLKDIV_HALT 

MRCC_LPTMR0_CLKDIV - HALT.

LPTMR0 clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
LPTMR0_CLKDIV_UNSTAB 

MRCC_LPTMR0_CLKDIV - UNSTAB.

LPTMR0 clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
OSTIMER0_CLKSEL_MUX 

MRCC_OSTIMER0_CLKSEL - MUX.

OSTIMER0 clock selection control - Functional Clock Mux Select

  • [0b11]Reserved2(NO Clock)
  • [0b10]CLK_1M
  • [0b00]CLK_16K
ADC0_CLKSEL_MUX 

MRCC_ADC0_CLKSEL - MUX.

ADC0 clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b101]CLK_1M
  • [0b011]CLK_IN
  • [0b001]FRO_HF_GATED
  • [0b000]FRO_12M
ADC0_CLKDIV_DIV 

MRCC_ADC0_CLKDIV - DIV.

ADC0 clock divider control - Functional Clock Divider

ADC0_CLKDIV_RESET 

MRCC_ADC0_CLKDIV - RESET.

ADC0 clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
ADC0_CLKDIV_HALT 

MRCC_ADC0_CLKDIV - HALT.

ADC0 clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
ADC0_CLKDIV_UNSTAB 

MRCC_ADC0_CLKDIV - UNSTAB.

ADC0 clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
ADC1_CLKSEL_MUX 

MRCC_ADC1_CLKSEL - MUX.

ADC1 clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b101]CLK_1M
  • [0b011]CLK_IN
  • [0b001]FRO_HF_GATED
  • [0b000]FRO_12M
ADC1_CLKDIV_DIV 

MRCC_ADC1_CLKDIV - DIV.

ADC1 clock divider control - Functional Clock Divider

ADC1_CLKDIV_RESET 

MRCC_ADC1_CLKDIV - RESET.

ADC1 clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
ADC1_CLKDIV_HALT 

MRCC_ADC1_CLKDIV - HALT.

ADC1 clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
ADC1_CLKDIV_UNSTAB 

MRCC_ADC1_CLKDIV - UNSTAB.

ADC1 clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
CMP0_FUNC_CLKDIV_DIV 

MRCC_CMP0_FUNC_CLKDIV - DIV.

CMP0_FUNC clock divider control - Functional Clock Divider

CMP0_FUNC_CLKDIV_RESET 

MRCC_CMP0_FUNC_CLKDIV - RESET.

CMP0_FUNC clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
CMP0_FUNC_CLKDIV_HALT 

MRCC_CMP0_FUNC_CLKDIV - HALT.

CMP0_FUNC clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
CMP0_FUNC_CLKDIV_UNSTAB 

MRCC_CMP0_FUNC_CLKDIV - UNSTAB.

CMP0_FUNC clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
CMP0_RR_CLKSEL_MUX 

MRCC_CMP0_RR_CLKSEL - MUX.

CMP0_RR clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b101]CLK_1M
  • [0b011]CLK_IN
  • [0b010]FRO_HF_DIV
  • [0b000]FRO_12M
CMP0_RR_CLKDIV_DIV 

MRCC_CMP0_RR_CLKDIV - DIV.

CMP0_RR clock divider control - Functional Clock Divider

CMP0_RR_CLKDIV_RESET 

MRCC_CMP0_RR_CLKDIV - RESET.

CMP0_RR clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
CMP0_RR_CLKDIV_HALT 

MRCC_CMP0_RR_CLKDIV - HALT.

CMP0_RR clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
CMP0_RR_CLKDIV_UNSTAB 

MRCC_CMP0_RR_CLKDIV - UNSTAB.

CMP0_RR clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
CMP1_FUNC_CLKDIV_DIV 

MRCC_CMP1_FUNC_CLKDIV - DIV.

CMP1_FUNC clock divider control - Functional Clock Divider

CMP1_FUNC_CLKDIV_RESET 

MRCC_CMP1_FUNC_CLKDIV - RESET.

CMP1_FUNC clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
CMP1_FUNC_CLKDIV_HALT 

MRCC_CMP1_FUNC_CLKDIV - HALT.

CMP1_FUNC clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
CMP1_FUNC_CLKDIV_UNSTAB 

MRCC_CMP1_FUNC_CLKDIV - UNSTAB.

CMP1_FUNC clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
CMP1_RR_CLKSEL_MUX 

MRCC_CMP1_RR_CLKSEL - MUX.

CMP1_RR clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b101]CLK_1M
  • [0b011]CLK_IN
  • [0b010]FRO_HF_DIV
  • [0b000]FRO_12M
CMP1_RR_CLKDIV_DIV 

MRCC_CMP1_RR_CLKDIV - CDIV.

CMP1_RR clock divider control - Functional Clock Divider

CMP1_RR_CLKDIV_RESET 

MRCC_CMP1_RR_CLKDIV - CRESET.

CMP1_RR clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
CMP1_RR_CLKDIV_HALT 

MRCC_CMP1_RR_CLKDIV - CHALT.

CMP1_RR clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
CMP1_RR_CLKDIV_UNSTAB 

MRCC_CMP1_RR_CLKDIV - CUNSTAB.

CMP1_RR clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
DAC0_CLKSEL_MUX 

MRCC_DAC0_CLKSEL - MUX.

DAC0 clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b101]CLK_1M
  • [0b011]CLK_IN
  • [0b010]FRO_HF_DIV
  • [0b000]FRO_12M
DAC0_CLKDIV_DIV 

MRCC_DAC0_CLKDIV - DIV.

DAC0 clock divider control - Functional Clock Divider

DAC0_CLKDIV_RESET 

MRCC_DAC0_CLKDIV - RESET.

DAC0 clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
DAC0_CLKDIV_HALT 

MRCC_DAC0_CLKDIV - HALT.

DAC0 clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
DAC0_CLKDIV_UNSTAB 

MRCC_DAC0_CLKDIV - UNSTAB.

DAC0 clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
FLEXCAN0_CLKSEL_MUX 

MRCC_FLEXCAN0_CLKSEL - MUX.

FLEXCAN0 clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b011]CLK_IN
  • [0b010]FRO_HF_DIV
FLEXCAN0_CLKDIV_DIV 

MRCC_FLEXCAN0_CLKDIV - DIV.

FLEXCAN0 clock divider control - Functional Clock Divider

FLEXCAN0_CLKDIV_RESET 

MRCC_FLEXCAN0_CLKDIV - RESET.

FLEXCAN0 clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
FLEXCAN0_CLKDIV_HALT 

MRCC_FLEXCAN0_CLKDIV - HALT.

FLEXCAN0 clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
FLEXCAN0_CLKDIV_UNSTAB 

MRCC_FLEXCAN0_CLKDIV - UNSTAB.

FLEXCAN0 clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
LPI2C2_CLKSEL_MUX 

MRCC_LPI2C2_CLKSEL - MUX.

LPI2C2 clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b101]CLK_1M
  • [0b011]CLK_IN
  • [0b010]FRO_HF_DIV
  • [0b000]FRO_12M
LPI2C2_CLKDIV_DIV 

MRCC_LPI2C2_CLKDIV - DIV.

LPI2C2 clock divider control - Functional Clock Divider

LPI2C2_CLKDIV_RESET 

MRCC_LPI2C2_CLKDIV - RESET.

LPI2C2 clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
LPI2C2_CLKDIV_HALT 

MRCC_LPI2C2_CLKDIV - HALT.

LPI2C2 clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
LPI2C2_CLKDIV_UNSTAB 

MRCC_LPI2C2_CLKDIV - UNSTAB.

LPI2C2 clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
LPI2C3_CLKSEL_MUX 

MRCC_LPI2C3_CLKSEL - MUX.

LPI2C3 clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b101]CLK_1M
  • [0b011]CLK_IN
  • [0b010]FRO_HF_DIV
  • [0b000]FRO_12M
LPI2C3_CLKDIV_DIV 

MRCC_LPI2C3_CLKDIV - DIV.

LPI2C3 clock divider control - Functional Clock Divider

LPI2C3_CLKDIV_RESET 

MRCC_LPI2C3_CLKDIV - RESET.

LPI2C3 clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
LPI2C3_CLKDIV_HALT 

MRCC_LPI2C3_CLKDIV - HALT.

LPI2C3 clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
LPI2C3_CLKDIV_UNSTAB 

MRCC_LPI2C3_CLKDIV - UNSTAB.

LPI2C3 clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
DBG_TRACE_CLKSEL_MUX 

MRCC_DBG_TRACE_CLKSEL - MUX.

DBG_TRACE clock selection control - Functional Clock Mux Select

  • [0b11]Reserved1(NO Clock)
  • [0b10]CLK_16K
  • [0b01]CLK_1M
  • [0b00]CPU_CLK
DBG_TRACE_CLKDIV_DIV 

MRCC_DBG_TRACE_CLKDIV - DIV.

DBG_TRACE clock divider control - Functional Clock Divider

DBG_TRACE_CLKDIV_RESET 

MRCC_DBG_TRACE_CLKDIV - RESET.

DBG_TRACE clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
DBG_TRACE_CLKDIV_HALT 

MRCC_DBG_TRACE_CLKDIV - HALT.

DBG_TRACE clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
DBG_TRACE_CLKDIV_UNSTAB 

MRCC_DBG_TRACE_CLKDIV - UNSTAB.

DBG_TRACE clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
CLKOUT_CLKSEL_MUX 

MRCC_CLKOUT_CLKSEL - MUX.

CLKOUT clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b110]SLOW_CLK
  • [0b011]CLK_16K
  • [0b010]CLK_IN
  • [0b001]FRO_HF_DIV
  • [0b000]FRO_12M
CLKOUT_CLKDIV_DIV 

MRCC_CLKOUT_CLKDIV - DIV.

CLKOUT clock divider control - Functional Clock Divider

CLKOUT_CLKDIV_RESET 

MRCC_CLKOUT_CLKDIV - RESET.

CLKOUT clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
CLKOUT_CLKDIV_HALT 

MRCC_CLKOUT_CLKDIV - HALT.

CLKOUT clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
CLKOUT_CLKDIV_UNSTAB 

MRCC_CLKOUT_CLKDIV - UNSTAB.

CLKOUT clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
SYSTICK_CLKSEL_MUX 

MRCC_SYSTICK_CLKSEL - MUX.

SYSTICK clock selection control - Functional Clock Mux Select

  • [0b11]Reserved1(NO Clock)
  • [0b10]CLK_16K
  • [0b01]CLK_1M
  • [0b00]CPU_CLK
SYSTICK_CLKDIV_DIV 

MRCC_SYSTICK_CLKDIV - DIV.

SYSTICK clock divider control - Functional Clock Divider

SYSTICK_CLKDIV_RESET 

MRCC_SYSTICK_CLKDIV - RESET.

SYSTICK clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
SYSTICK_CLKDIV_HALT 

MRCC_SYSTICK_CLKDIV - HALT.

SYSTICK clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
SYSTICK_CLKDIV_UNSTAB 

MRCC_SYSTICK_CLKDIV - UNSTAB.

SYSTICK clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
FRO_HF_DIV_CLKDIV_DIV 

MRCC_FRO_HF_DIV_CLKDIV - DIV.

FRO_HF_DIV clock divider control - Functional Clock Divider

FRO_HF_DIV_CLKDIV_UNSTAB 

MRCC_FRO_HF_DIV_CLKDIV - UNSTAB.

FRO_HF_DIV clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable

◆ Shift

enum struct chip::mrcc::Shift : unsigned int
strong
列舉值
GLB_RST0_INPUTMUX0 

GLB_RST0 - INPUTMUX0.

Peripheral Reset Control 0 - INPUTMUX0

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_I3C0 

GLB_RST0 - I3C0.

Peripheral Reset Control 0 - I3C0

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_CTIMER0 

GLB_RST0 - CTIMER0.

Peripheral Reset Control 0 - CTIMER0

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_CTIMER1 

GLB_RST0 - CTIMER1.

Peripheral Reset Control 0 - CTIMER1

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_CTIMER2 

GLB_RST0 - CTIMER2.

Peripheral Reset Control 0 - CTIMER2

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_CTIMER3 

GLB_RST0 - CTIMER3.

Peripheral Reset Control 0 - CTIMER3

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_CTIMER4 

GLB_RST0 - CTIMER4.

Peripheral Reset Control 0 - CTIMER4

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_FREQME 

GLB_RST0 - FREQME.

Peripheral Reset Control 0 - FREQME

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_UTICK0 

GLB_RST0 - UTICK0.

Peripheral Reset Control 0 - UTICK0

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_DMA 

GLB_RST0 - DMA.

Peripheral Reset Control 0 - DMA

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_AOI0 

GLB_RST0 - AOI0.

Peripheral Reset Control 0 - AOI0

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_CRC0 

GLB_RST0 - CRC0.

Peripheral Reset Control 0 - CRC0

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_EIM0 

GLB_RST0 - EIM0.

Peripheral Reset Control 0 - EIM0

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_ERM0 

GLB_RST0 - ERM0.

Peripheral Reset Control 0 - ERM0

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_AOI1 

GLB_RST0 - AOI1.

Peripheral Reset Control 0 - AOI1

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_FLEXIO0 

GLB_RST0 - FLEXIO0.

Peripheral Reset Control 0 - FLEXIO0

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_LPI2C0 

GLB_RST0 - LPI2C0.

Peripheral Reset Control 0 - LPI2C0

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_LPI2C1 

GLB_RST0 - LPI2C1.

Peripheral Reset Control 0 - LPI2C1

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_LPSPI0 

GLB_RST0 - LPSPI0.

Peripheral Reset Control 0 - LPSPI0

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_LPSPI1 

GLB_RST0 - LPSPI1.

Peripheral Reset Control 0 - LPSPI1

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_LPUART0 

GLB_RST0 - LPUART0.

Peripheral Reset Control 0 - LPUART0

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_LPUART1 

GLB_RST0 - LPUART1.

Peripheral Reset Control 0 - LPUART1

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_LPUART2 

GLB_RST0 - LPUART2.

Peripheral Reset Control 0 - LPUART2

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_LPUART3 

GLB_RST0 - LPUART3.

Peripheral Reset Control 0 - LPUART3

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_LPUART4 

GLB_RST0 - LPUART4.

Peripheral Reset Control 0 - LPUART4

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_USB0 

GLB_RST0 - USB0.

Peripheral Reset Control 0 - USB0

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_QDC0 

GLB_RST0 - QDC0.

Peripheral Reset Control 0 - QDC0

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_QDC1 

GLB_RST0 - QDC1.

Peripheral Reset Control 0 - QDC1

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_FLEXPWM0 

GLB_RST0 - FLEXPWM0.

Peripheral Reset Control 0 - FLEXPWM0

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_FLEXPWM1 

GLB_RST0 - FLEXPWM1.

Peripheral Reset Control 0 - FLEXPWM1

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST0_SET_DATA 

GLB_RST0_SET - DATA.

Peripheral Reset Control Set 0 - Data array value, refer to corresponding position in MRCC_GLB_RSTn.

GLB_RST0_CLR_DATA 

GLB_RST0_CLR - DATA.

Peripheral Reset Control Clear 0 - Data array value, refer to corresponding position in MRCC_GLB_RSTn.

GLB_RST1_OSTIMER0 

GLB_RST1 - OSTIMER0.

Peripheral Reset Control 1 - OSTIMER0

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST1_ADC0 

GLB_RST1 - ADC0.

Peripheral Reset Control 1 - ADC0

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST1_ADC1 

GLB_RST1 - ADC1.

Peripheral Reset Control 1 - ADC1

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST1_CMP1 

GLB_RST1 - CMP1.

Peripheral Reset Control 1 - CMP1

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST1_DAC0 

GLB_RST1 - DAC0.

Peripheral Reset Control 1 - DAC0

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST1_OPAMP0 

GLB_RST1 - OPAMP0.

Peripheral Reset Control 1 - OPAMP0

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST1_PORT0 

GLB_RST1 - PORT0.

Peripheral Reset Control 1 - PORT0

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST1_PORT1 

GLB_RST1 - PORT1.

Peripheral Reset Control 1 - PORT1

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST1_PORT2 

GLB_RST1 - PORT2.

Peripheral Reset Control 1 - PORT2

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST1_PORT3 

GLB_RST1 - PORT3.

Peripheral Reset Control 1 - PORT3

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST1_PORT4 

GLB_RST1 - PORT4.

Peripheral Reset Control 1 - PORT4

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST1_FLEXCAN0 

GLB_RST1 - FLEXCAN0.

Peripheral Reset Control 1 - FLEXCAN0

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST1_LPI2C2 

GLB_RST1 - LPI2C2.

Peripheral Reset Control 1 - LPI2C2

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST1_LPI2C3 

GLB_RST1 - LPI2C3.

Peripheral Reset Control 1 - LPI2C3

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST1_GPIO0 

GLB_RST1 - GPIO0.

Peripheral Reset Control 1 - GPIO0

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST1_GPIO1 

GLB_RST1 - GPIO1.

Peripheral Reset Control 1 - GPIO1

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST1_GPIO2 

GLB_RST1 - GPIO2.

Peripheral Reset Control 1 - GPIO2

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST1_GPIO3 

GLB_RST1 - GPIO3.

Peripheral Reset Control 1 - GPIO3

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST1_GPIO4 

GLB_RST1 - GPIO4.

Peripheral Reset Control 1 - GPIO4

  • [0b0]Peripheral is held in reset
  • [0b1]Peripheral is released from reset
GLB_RST1_SET_DATA 

GLB_RST1_SET - DATA.

Peripheral Reset Control Set 1 - Data array value, refer to corresponding position in MRCC_GLB_RSTn.

GLB_RST1_CLR_DATA 

GLB_RST1_CLR - DATA.

Peripheral Reset Control Clear 1 - Data array value, refer to corresponding position in MRCC_GLB_RSTn.

GLB_CC0_INPUTMUX0 

GLB_CC0 - INPUTMUX0.

AHB Clock Control 0 - INPUTMUX0

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_I3C0 

GLB_CC0 - I3C0.

AHB Clock Control 0 - I3C0

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_CTIMER0 

GLB_CC0 - CTIMER0.

AHB Clock Control 0 - CTIMER0

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_CTIMER1 

GLB_CC0 - CTIMER1.

AHB Clock Control 0 - CTIMER1

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_CTIMER2 

GLB_CC0 - CTIMER2.

AHB Clock Control 0 - CTIMER2

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_CTIMER3 

GLB_CC0 - CTIMER3.

AHB Clock Control 0 - CTIMER3

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_CTIMER4 

GLB_CC0 - CTIMER4.

AHB Clock Control 0 - CTIMER4

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_FREQME 

GLB_CC0 - FREQME.

AHB Clock Control 0 - FREQME

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_UTICK0 

GLB_CC0 - UTICK0.

AHB Clock Control 0 - UTICK0

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_WWDT0 

GLB_CC0 - WWDT0.

AHB Clock Control 0 - WWDT0

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_DMA 

GLB_CC0 - DMA.

AHB Clock Control 0 - DMA

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_AOI0 

GLB_CC0 - AOI0.

AHB Clock Control 0 - AOI0

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_CRC0 

GLB_CC0 - CRC0.

AHB Clock Control 0 - CRC0

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_EIM0 

GLB_CC0 - EIM0.

AHB Clock Control 0 - EIM0

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_ERM0 

GLB_CC0 - ERM0.

AHB Clock Control 0 - ERM0

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_FMC 

GLB_CC0 - FMC.

AHB Clock Control 0 - FMC

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_AOI1 

GLB_CC0 - AOI1.

AHB Clock Control 0 - AOI1

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_FLEXIO0 

GLB_CC0 - FLEXIO0.

AHB Clock Control 0 - FLEXIO0

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_LPI2C0 

GLB_CC0 - LPI2C0.

AHB Clock Control 0 - LPI2C0

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_LPI2C1 

GLB_CC0 - LPI2C1.

AHB Clock Control 0 - LPI2C1

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_LPSPI0 

GLB_CC0 - LPSPI0.

AHB Clock Control 0 - LPSPI0

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_LPSPI1 

GLB_CC0 - LPSPI1.

AHB Clock Control 0 - LPSPI1

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_LPUART0 

GLB_CC0 - LPUART0.

AHB Clock Control 0 - LPUART0

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_LPUART1 

GLB_CC0 - LPUART1.

AHB Clock Control 0 - LPUART1

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_LPUART2 

GLB_CC0 - LPUART2.

AHB Clock Control 0 - LPUART2

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_LPUART3 

GLB_CC0 - LPUART3.

AHB Clock Control 0 - LPUART3

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_LPUART4 

GLB_CC0 - LPUART4.

AHB Clock Control 0 - LPUART4

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_USB0 

GLB_CC0 - USB0.

AHB Clock Control 0 - USB0

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_QDC0 

GLB_CC0 - QDC0.

AHB Clock Control 0 - QDC0

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_QDC1 

GLB_CC0 - QDC1.

AHB Clock Control 0 - QDC1

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_FLEXPWM0 

GLB_CC0 - FLEXPWM0.

AHB Clock Control 0 - FLEXPWM0

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_FLEXPWM1 

GLB_CC0 - FLEXPWM1.

AHB Clock Control 0 - FLEXPWM1

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC0_SET_DATA 

GLB_CC0_SET - DATA.

AHB Clock Control Set 0 - Data array value, refer to corresponding position in MRCC_GLB_CCn.

GLB_CC0_CLR_DATA 

GLB_CC0_CLR - DATA.

AHB Clock Control Clear 0 - Data array value, refer to corresponding position in MRCC_GLB_CCn.

GLB_CC1_OSTIMER0 

GLB_CC1 - OSTIMER0.

AHB Clock Control 1 - OSTIMER0

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC1_ADC0 

GLB_CC1 - ADC0.

AHB Clock Control 1 - ADC0

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC1_ADC1 

GLB_CC1 - ADC1.

AHB Clock Control 1 - ADC1

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC1_CMP0 

GLB_CC1 - CMP0.

AHB Clock Control 1 - CMP0

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC1_CMP1 

GLB_CC1 - CMP1.

AHB Clock Control 1 - CMP1

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC1_DAC0 

GLB_CC1 - DAC0.

AHB Clock Control 1 - DAC0

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC1_OPAMP0 

GLB_CC1 - OPAMP0.

AHB Clock Control 1 - OPAMP0

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC1_PORT0 

GLB_CC1 - PORT0.

AHB Clock Control 1 - PORT0

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC1_PORT1 

GLB_CC1 - PORT1.

AHB Clock Control 1

AHB Clock Control 1 - PORT1

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC1_PORT2 

GLB_CC1 - PORT2.

AHB Clock Control 1 - PORT2

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC1_PORT3 

GLB_CC1 - PORT3.

AHB Clock Control 1 - PORT3

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC1_PORT4 

GLB_CC1 - PORT4.

AHB Clock Control 1 - PORT4

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC1_FLEXCAN0 

GLB_CC1 - FLEXCAN0.

AHB Clock Control 1 - FLEXCAN0

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC1_LPI2C2 

GLB_CC1 - LPI2C2.

AHB Clock Control 1 - LPI2C2

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC1_LPI2C3 

GLB_CC1 - LPI2C3.

AHB Clock Control 1 - LPI2C3

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC1_RAMA 

GLB_CC1 - RAMA.

AHB Clock Control 1 - RAMA

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC1_RAMB 

GLB_CC1 - RAMB.

AHB Clock Control 1 - RAMB

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC1_GPIO0 

GLB_CC1 - GPIO0.

AHB Clock Control 1 - GPIO0

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC1_GPIO1 

GLB_CC1 - GPIO1.

AHB Clock Control 1 - GPIO1

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC1_GPIO2 

GLB_CC1 - GPIO2.

AHB Clock Control 1 - GPIO2

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC1_GPIO3 

GLB_CC1 - GPIO3.

AHB Clock Control 1 - GPIO3

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC1_GPIO4 

GLB_CC1 - GPIO4.

AHB Clock Control 1 - GPIO4

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC1_ROMC 

GLB_CC1 - ROMC.

AHB Clock Control 1 - ROMC

  • [0b0]Peripheral clock is disabled
  • [0b1]Peripheral clock is enabled
GLB_CC_SET_DATA 

GLB_CC_SET - DATA.

AHB Clock Control Set 1 - Data array value, refer to corresponding position in MRCC_GLB_CCn.

GLB_CC_CLR_DATA 

GLB_CC_CLR - DATA.

AHB Clock Control Clear 1 - Data array value, refer to corresponding position in MRCC_GLB_CCn.

GLB_ACC0_INPUTMUX0 

GLB_ACC0 - INPUTMUX0.

Control Automatic Clock Gating 0 - INPUTMUX0

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_I3C0 

GLB_ACC0 - I3C0.

Control Automatic Clock Gating 0 - I3C0

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_CTIMER0 

GLB_ACC0 - CTIMER0.

Control Automatic Clock Gating 0 - CTIMER0

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_CTIMER1 

GLB_ACC0 - CTIMER1.

Control Automatic Clock Gating 0 - CTIMER1

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_CTIMER2 

GLB_ACC0 - CTIMER2.

Control Automatic Clock Gating 0 - CTIMER2

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_CTIMER3 

GLB_ACC0 - CTIMER3.

Control Automatic Clock Gating 0 - CTIMER3

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_CTIMER4 

GLB_ACC0 - CTIMER4.

Control Automatic Clock Gating 0 - CTIMER4

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_FREQME 

GLB_ACC0 - FREQME.

Control Automatic Clock Gating 0 - FREQME

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_UTICK0 

GLB_ACC0 - UTICK0.

Control Automatic Clock Gating 0 - UTICK0

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_WWDT0 

GLB_ACC0 - WWDT0.

Control Automatic Clock Gating 0 - WWDT0

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_DMA 

GLB_ACC0 - DMA.

Control Automatic Clock Gating 0 - DMA

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_AOI0 

GLB_ACC0 - AOI0.

Control Automatic Clock Gating 0 - AOI0

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_CRC0 

GLB_ACC0 - CRC0.

Control Automatic Clock Gating 0 - CRC0

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_EIM0 

GLB_ACC0 - EIM0.

Control Automatic Clock Gating 0 - EIM0

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_ERM0 

GLB_ACC0 - ERM0.

Control Automatic Clock Gating 0 - ERM0

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_FMC 

GLB_ACC0 - FMC.

Control Automatic Clock Gating 0 - FMC

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_AOI1 

GLB_ACC0 - AOI1.

Control Automatic Clock Gating 0 - AOI1

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_FLEXIO0 

GLB_ACC0 - FLEXIO0.

Control Automatic Clock Gating 0 - FLEXIO0

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_LPI2C0 

GLB_ACC0 - LPI2C0.

Control Automatic Clock Gating 0 - LPI2C0

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_LPI2C1 

GLB_ACC0 - LPI2C1.

Control Automatic Clock Gating 0 - LPI2C1

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_LPSPI0 

GLB_ACC0 - LPSPI0.

Control Automatic Clock Gating 0 - LPSPI0

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_LPSPI1 

GLB_ACC0 - LPSPI1.

Control Automatic Clock Gating 0 - LPSPI1

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_LPUART0 

GLB_ACC0 - LPUART0.

Control Automatic Clock Gating 0 - LPUART0

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_LPUART1 

GLB_ACC0 - LPUART1.

Control Automatic Clock Gating 0 - LPUART1

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_LPUART2 

GLB_ACC0 - LPUART2.

Control Automatic Clock Gating 0 - LPUART2

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_LPUART3 

GLB_ACC0 - LPUART3.

Control Automatic Clock Gating 0 - LPUART3

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_LPUART4 

GLB_ACC0 - LPUART4.

Control Automatic Clock Gating 0 - LPUART4

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_USB0 

GLB_ACC0 - USB0.

Control Automatic Clock Gating 0 - USB0

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_QDC0 

GLB_ACC0 - QDC0.

Control Automatic Clock Gating 0 - QDC0

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_QDC1 

GLB_ACC0 - QDC1.

Control Automatic Clock Gating 0 - QDC1

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_FLEXPWM0 

GLB_ACC0 - FLEXPWM0.

Control Automatic Clock Gating 0 - FLEXPWM0

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC0_FLEXPWM1 

GLB_ACC0 - FLEXPWM1.

Control Automatic Clock Gating 0 - FLEXPWM1

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC1_OSTIMER0 

GLB_ACC1 - OSTIMER0.

Control Automatic Clock Gating 1 - OSTIMER0

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC1_ADC0 

GLB_ACC1 - ADC0.

Control Automatic Clock Gating 1 - ADC0

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC1_ADC1 

GLB_ACC1 - ADC1.

Control Automatic Clock Gating 1 - ADC1

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC1_CMP0 

GLB_ACC1 - CMP0.

Control Automatic Clock Gating 1 - CMP0

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC1_CMP1 

GLB_ACC1 - CMP1.

Control Automatic Clock Gating 1 - CMP1

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC1_DAC0 

GLB_ACC1 - DAC0.

Control Automatic Clock Gating 1 - DAC0

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC1_OPAMP0 

GLB_ACC1 - OPAMP0.

Control Automatic Clock Gating 1 - OPAMP0

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC1_PORT0 

GLB_ACC1 - PORT0.

Control Automatic Clock Gating 1 - PORT0

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC1_PORT1 

GLB_ACC1 - PORT1.

Control Automatic Clock Gating 1 - PORT1

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC1_PORT2 

GLB_ACC1 - PORT2.

Control Automatic Clock Gating 1 - PORT2

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC1_PORT3 

GLB_ACC1 - PORT3.

Control Automatic Clock Gating 1 - PORT3

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC1_PORT4 

GLB_ACC1 - PORT4.

Control Automatic Clock Gating 1 - PORT4

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC1_FLEXCAN0 

GLB_ACC1 - FLEXCAN0.

Control Automatic Clock Gating 1 - FLEXCAN0

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC1_LPI2C2 

GLB_ACC1 - LPI2C2.

Control Automatic Clock Gating 1 - LPI2C2

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC1_LPI2C3 

GLB_ACC1 - LPI2C3.

Control Automatic Clock Gating 1 - LPI2C3

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC1_RAMA 

GLB_ACC1 - RAMA.

Control Automatic Clock Gating 1 - RAMA

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC1_RAMB 

GLB_ACC1 - RAMB.

Control Automatic Clock Gating 1 - RAMB

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC1_GPIO0 

GLB_ACC1 - GPIO0.

Control Automatic Clock Gating 1 - GPIO0

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC1_GPIO1 

GLB_ACC1 - GPIO1.

Control Automatic Clock Gating 1 - GPIO1

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC1_GPIO2 

GLB_ACC1 - GPIO2.

Control Automatic Clock Gating 1 - GPIO2

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC1_GPIO3 

GLB_ACC1 - GPIO3.

Control Automatic Clock Gating 1 - GPIO3

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC1_GPIO4 

GLB_ACC1 - GPIO4.

Control Automatic Clock Gating 1 - GPIO4

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
GLB_ACC1_ROMC 

GLB_ACC1 - ROMC.

Control Automatic Clock Gating 1 - ROMC

  • [0b0]Automatic clock gating is disabled
  • [0b1]Automatic clock gating is enabled
I3C0_FCLK_CLKSEL_MUX 

I3C0_FCLK_CLKSEL - MUX.

I3C0_FCLK clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b101]CLK_1M
  • [0b011]CLK_IN
  • [0b010]FRO_HF_DIV
  • [0b000]FRO_12M
I3C0_FCLK_CLKDIV_DIV 

I3C0_FCLK_CLKDIV - DIV.

I3C0_FCLK clock divider control - Functional Clock Divider

I3C0_FCLK_CLKDIV_RESET 

I3C0_FCLK_CLKDIV - RESET.

I3C0_FCLK clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
I3C0_FCLK_CLKDIV_HALT 

I3C0_FCLK_CLKDIV - HALT.

I3C0_FCLK clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
I3C0_FCLK_CLKDIV_UNSTAB 

I3C0_FCLK_CLKDIV - UNSTAB.

I3C0_FCLK clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
CTIMER0_CLKSEL_MUX 

CTIMER0_CLKSEL - MUX.

CTIMER0 clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b101]CLK_1M
  • [0b100]CLK_16K
  • [0b011]CLK_IN
  • [0b001]FRO_HF_GATED
  • [0b000]FRO_12M
CTIMER0_CLKDIV_DIV 

CTIMER0_CLKDIV - DIV.

CTIMER0 clock divider control - Functional Clock Divider

CTIMER0_CLKDIV_RESET 

CTIMER0_CLKDIV - RESET.

CTIMER0 clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
CTIMER0_CLKDIV_HALT 

CTIMER0_CLKDIV - HALT.

CTIMER0 clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
CTIMER0_CLKDIV_UNSTAB 

CTIMER0_CLKDIV - UNSTAB.

CTIMER0 clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
CTIMER1_CLKSEL_MUX 

CTIMER1_CLKSEL - MUX.

CTIMER1 clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b101]CLK_1M
  • [0b100]CLK_16K
  • [0b011]CLK_IN
  • [0b001]FRO_HF_GATED
  • [0b000]FRO_12M
CTIMER1_CLKDIV_DIV 

CTIMER1_CLKDIV - DIV.

CTIMER1 clock divider control - Functional Clock Divider

CTIMER1_CLKDIV_RESET 

CTIMER1_CLKDIV - RESET.

CTIMER1 clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
CTIMER1_CLKDIV_HALT 

CTIMER1_CLKDIV - HALT.

CTIMER1 clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
CTIMER1_CLKDIV_UNSTAB 

CTIMER1_CLKDIV - UNSTAB.

CTIMER1 clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
CTIMER2_CLKSEL_MUX 

CTIMER2_CLKSEL - MUX.

CTIMER2 clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b101]CLK_1M
  • [0b100]CLK_16K
  • [0b011]CLK_IN
  • [0b001]FRO_HF_GATED
  • [0b000]FRO_12M
CTIMER2_CLKDIV_DIV 

CTIMER2_CLKDIV - DIV.

CTIMER2 clock divider control - Functional Clock Divider

CTIMER2_CLKDIV_RESET 

CTIMER2_CLKDIV - RESET.

CTIMER2 clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
CTIMER2_CLKDIV_HALT 

CTIMER2_CLKDIV - HALT.

CTIMER2 clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
CTIMER2_CLKDIV_UNSTAB 

CTIMER2_CLKDIV - UNSTAB.

CTIMER2 clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
CTIMER3_CLKSEL_MUX 

CTIMER3_CLKSEL - MUX.

CTIMER3 clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b101]CLK_1M
  • [0b100]CLK_16K
  • [0b011]CLK_IN
  • [0b001]FRO_HF_GATED
  • [0b000]FRO_12M
CTIMER3_CLKDIV_DIV 

CTIMER3_CLKDIV - DIV.

CTIMER3 clock divider control - Functional Clock Divider

CTIMER3_CLKDIV_RESET 

CTIMER3_CLKDIV - RESET.

CTIMER3 clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
CTIMER3_CLKDIV_HALT 

CTIMER3_CLKDIV - HALT.

CTIMER3 clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
CTIMER3_CLKDIV_UNSTAB 

CTIMER3_CLKDIV - UNSTAB.

CTIMER3 clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
CTIMER4_CLKSEL_MUX 

CTIMER4_CLKSEL - MUX.

CTIMER4 clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b101]CLK_1M
  • [0b100]CLK_16K
  • [0b011]CLK_IN
  • [0b001]FRO_HF_GATED
  • [0b000]FRO_12M
CTIMER4_CLKDIV_DIV 

CTIMER4_CLKDIV - DIV.

CTIMER4 clock divider control - Functional Clock Divider

CTIMER4_CLKDIV_RESET 

CTIMER4_CLKDIV - RESET.

CTIMER4 clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
CTIMER4_CLKDIV_HALT 

CTIMER4_CLKDIV - HALT.

CTIMER4 clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
CTIMER4_CLKDIV_UNSTAB 

CTIMER4_CLKDIV - UNSTAB.

CTIMER4 clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
WWDT0_CLKDIV_DIV 

WWDT0_CLKDIV - DIV.

WWDT0 clock divider control - Functional Clock Divider

WWDT0_CLKDIV_RESET 

WWDT0_CLKDIV - RESET.

WWDT0 clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
WWDT0_CLKDIV_HALT 

WWDT0_CLKDIV - HALT.

WWDT0 clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
WWDT0_CLKDIV_UNSTAB 

WWDT0_CLKDIV - UNSTAB.

WWDT0 clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
FLEXIO0_CLKSEL_MUX 

FLEXIO0_CLKSEL - MUX.

FLEXIO0 clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b101]CLK_1M
  • [0b011]CLK_IN
  • [0b001]FRO_HF_GATED
  • [0b000]FRO_12M
FLEXIO0_CLKDIV_DIV 

FLEXIO0_CLKDIV - DIV.

FLEXIO0 clock divider control - Functional Clock Divider

FLEXIO0_CLKDIV_RESET 

FLEXIO0_CLKDIV - RESET.

FLEXIO0 clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
FLEXIO0_CLKDIV_HALT 

FLEXIO0_CLKDIV - HALT.

FLEXIO0 clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
FLEXIO0_CLKDIV_UNSTAB 

FLEXIO0_CLKDIV - UNSTAB.

FLEXIO0 clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
LPI2C0_CLKSEL_MUX 

LPI2C0_CLKSEL - MUX.

LPI2C0 clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b101]CLK_1M
  • [0b011]CLK_IN
  • [0b010]FRO_HF_DIV
  • [0b000]FRO_12M
LPI2C0_CLKDIV_DIV 

LPI2C0_CLKDIV - DIV.

LPI2C0 clock divider control - Functional Clock Divider

LPI2C0_CLKDIV_RESET 

LPI2C0_CLKDIV - RESET.

LPI2C0 clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
LPI2C0_CLKDIV_HALT 

LPI2C0_CLKDIV - HALT.

LPI2C0 clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
LPI2C0_CLKDIV_UNSTAB 

LPI2C0_CLKDIV - UNSTAB.

LPI2C0 clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
LPI2C1_CLKSEL_MUX 

LPI2C1_CLKSEL - MUX.

LPI2C1 clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b101]CLK_1M
  • [0b011]CLK_IN
  • [0b010]FRO_HF_DIV
  • [0b000]FRO_12M
LPI2C1_CLKDIV_DIV 

LPI2C1_CLKDIV - DIV.

LPI2C1 clock divider control - Functional Clock Divider

LPI2C1_CLKDIV_RESET 

LPI2C1_CLKDIV - RESET.

LPI2C1 clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
LPI2C1_CLKDIV_HALT 

LPI2C1_CLKDIV - HALT.

LPI2C1 clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
LPI2C1_CLKDIV_UNSTAB 

LPI2C1_CLKDIV - UNSTAB.

LPI2C1 clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
LPSPI0_CLKSEL_MUX 

LPSPI0_CLKSEL - MUX.

LPSPI0 clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b101]CLK_1M
  • [0b011]CLK_IN
  • [0b010]FRO_HF_DIV
  • [0b000]FRO_12M
LPSPI0_CLKDIV_DIV 

LPSPI0_CLKDIV - DIV.

LPSPI0 clock divider control - Functional Clock Divider

LPSPI0_CLKDIV_RESET 

LPSPI0_CLKDIV - RESET.

LPSPI0 clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
LPSPI0_CLKDIV_HALT 

LPSPI0_CLKDIV - HALT.

LPSPI0 clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
LPSPI0_CLKDIV_UNSTAB 

LPSPI0_CLKDIV - UNSTAB.

LPSPI0 clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
LPSPI1_CLKSEL_MUX 

LPSPI1_CLKSEL - MUX.

LPSPI1 clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b101]CLK_1M
  • [0b011]CLK_IN
  • [0b010]FRO_HF_DIV
  • [0b000]FRO_12M
LPSPI1_CLKDIV_DIV 

LPSPI1_CLKDIV - DIV.

LPSPI1 clock divider control - Functional Clock Divider

LPSPI1_CLKDIV_RESET 

LPSPI1_CLKDIV - RESET.

LPSPI1 clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
LPSPI1_CLKDIV_HALT 

LPSPI1_CLKDIV - HALT.

LPSPI1 clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
LPSPI1_CLKDIV_UNSTAB 

LPSPI1_CLKDIV - UNSTAB.

LPSPI1 clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
LPUART0_CLKSEL_MUX 

LPUART0_CLKSEL - MUX.

LPUART0 clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b101]CLK_1M
  • [0b100]CLK_16K
  • [0b011]CLK_IN
  • [0b010]FRO_HF_DIV
  • [0b000]FRO_12M
LPUART0_CLKDIV_DIV 

LPUART0_CLKDIV - DIV.

LPUART0 clock divider control - Functional Clock Divider

LPUART0_CLKDIV_RESET 

LPUART0_CLKDIV - RESET.

LPUART0 clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
LPUART0_CLKDIV_HALT 

LPUART0_CLKDIV - HALT.

LPUART0 clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
LPUART0_CLKDIV_UNSTAB 

LPUART0_CLKDIV - UNSTAB.

LPUART0 clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
LPUART1_CLKSEL_MUX 

LPUART1_CLKSEL - MUX.

LPUART1 clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b101]CLK_1M
  • [0b100]CLK_16K
  • [0b011]CLK_IN
  • [0b010]FRO_HF_DIV
  • [0b000]FRO_12M
LPUART1_CLKDIV_DIV 

LPUART1_CLKDIV - DIV.

LPUART1 clock divider control - Functional Clock Divider

LPUART1_CLKDIV_RESET 

LPUART1_CLKDIV - RESET.

LPUART1 clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
LPUART1_CLKDIV_HALT 

LPUART1_CLKDIV - HALT.

LPUART1 clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
LPUART1_CLKDIV_UNSTAB 

LPUART1_CLKDIV - UNSTAB.

LPUART1 clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
LPUART2_CLKSEL_MUX 

LPUART2_CLKSEL - MUX.

LPUART2 clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b101]CLK_1M
  • [0b100]CLK_16K
  • [0b011]CLK_IN
  • [0b010]FRO_HF_DIV
  • [0b000]FRO_12M
LPUART2_CLKDIV_DIV 

LPUART2_CLKDIV - DIV.

LPUART2 clock divider control - Functional Clock Divider

LPUART2_CLKDIV_RESET 

LPUART2_CLKDIV - RESET.

LPUART2 clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
LPUART2_CLKDIV_HALT 

LPUART2_CLKDIV - HALT.

LPUART2 clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
LPUART2_CLKDIV_UNSTAB 

LPUART2_CLKDIV - UNSTAB.

LPUART2 clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
LPUART3_CLKSEL_MUX 

LPUART3_CLKSEL - MUX.

LPUART3 clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b101]CLK_1M
  • [0b100]CLK_16K
  • [0b011]CLK_IN
  • [0b010]FRO_HF_DIV
  • [0b000]FRO_12M
LPUART3_CLKDIV_DIV 

LPUART3_CLKDIV - DIV.

LPUART3 clock divider control - Functional Clock Divider

LPUART3_CLKDIV_RESET 

LPUART3_CLKDIV - RESET.

LPUART3 clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
LPUART3_CLKDIV_HALT 

LPUART3_CLKDIV - HALT.

LPUART3 clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
LPUART3_CLKDIV_UNSTAB 

LPUART3_CLKDIV - UNSTAB.

LPUART3 clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
LPUART4_CLKSEL_MUX 

LPUART4_CLKSEL - MUX.

LPUART4 clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b101]CLK_1M
  • [0b100]CLK_16K
  • [0b011]CLK_IN
  • [0b010]FRO_HF_DIV
  • [0b000]FRO_12M
LPUART4_CLKDIV_DIV 

LPUART4_CLKDIV - DIV.

LPUART4 clock divider control - Functional Clock Divider

LPUART4_CLKDIV_RESET 

LPUART4_CLKDIV - RESET.

LPUART4 clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
LPUART4_CLKDIV_HALT 

LPUART4_CLKDIV - HALT.

LPUART4 clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
LPUART4_CLKDIV_UNSTAB 

LPUART4_CLKDIV - UNSTAB.

LPUART4 clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
USB0_CLKSEL_MUX 

USB0_CLKSEL - MUX.

USB0 clock selection control - Functional Clock Mux Select

  • [0b11]Reserved(NO Clock)
  • [0b10]CLK_IN
  • [0b01]CLK_48M
LPTMR0_CLKSEL_MUX 

LPTMR0_CLKSEL - MUX.

LPTMR0 clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b101]CLK_1M
  • [0b011]CLK_IN
  • [0b010]FRO_HF_DIV
  • [0b000]FRO_12M
LPTMR0_CLKDIV_DIV 

LPTMR0_CLKDIV - DIV.

LPTMR0 clock divider control - Functional Clock Divider

LPTMR0_CLKDIV_RESET 

LPTMR0_CLKDIV - RESET.

LPTMR0 clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
LPTMR0_CLKDIV_HALT 

LPTMR0_CLKDIV - HALT.

LPTMR0 clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
LPTMR0_CLKDIV_UNSTAB 

LPTMR0_CLKDIV - UNSTAB.

LPTMR0 clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
OSTIMER0_CLKSEL_MUX 

OSTIMER0_CLKSEL - MUX.

OSTIMER0 clock selection control - Functional Clock Mux Select

  • [0b11]Reserved2(NO Clock)
  • [0b10]CLK_1M
  • [0b00]CLK_16K
ADC0_CLKSEL_MUX 

ADC0_CLKSEL - MUX.

ADC0 clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b101]CLK_1M
  • [0b011]CLK_IN
  • [0b001]FRO_HF_GATED
  • [0b000]FRO_12M
ADC0_CLKDIV_DIV 

ADC0_CLKDIV - DIV.

ADC0 clock divider control - Functional Clock Divider

ADC0_CLKDIV_RESET 

ADC0_CLKDIV - RESET.

ADC0 clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
ADC0_CLKDIV_HALT 

ADC0_CLKDIV - HALT.

ADC0 clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
ADC0_CLKDIV_UNSTAB 

ADC0_CLKDIV - UNSTAB.

ADC0 clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
ADC1_CLKSEL_MUX 

ADC1_CLKSEL - MUX.

ADC1 clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b101]CLK_1M
  • [0b011]CLK_IN
  • [0b001]FRO_HF_GATED
  • [0b000]FRO_12M
ADC1_CLKDIV_DIV 

ADC1_CLKDIV - DIV.

ADC1 clock divider control - Functional Clock Divider

ADC1_CLKDIV_RESET 

ADC1_CLKDIV - RESET.

ADC1 clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
ADC1_CLKDIV_HALT 

ADC1_CLKDIV - HALT.

ADC1 clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
ADC1_CLKDIV_UNSTAB 

ADC1_CLKDIV - UNSTAB.

ADC1 clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
CMP0_FUNC_CLKDIV_DIV 

CMP0_FUNC_CLKDIV - DIV.

CMP0_FUNC clock divider control - Functional Clock Divider

CMP0_FUNC_CLKDIV_RESET 

CMP0_FUNC_CLKDIV - RESET.

CMP0_FUNC clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
CMP0_FUNC_CLKDIV_HALT 

CMP0_FUNC_CLKDIV - HALT.

CMP0_FUNC clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
CMP0_FUNC_CLKDIV_UNSTAB 

CMP0_FUNC_CLKDIV - UNSTAB.

CMP0_FUNC clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
CMP0_RR_CLKSEL_MUX 

CMP0_RR_CLKSEL - MUX.

CMP0_RR clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b101]CLK_1M
  • [0b011]CLK_IN
  • [0b010]FRO_HF_DIV
  • [0b000]FRO_12M
CMP0_RR_CLKDIV_DIV 

CMP0_RR_CLKDIV - DIV.

CMP0_RR clock divider control - Functional Clock Divider

CMP0_RR_CLKDIV_RESET 

CMP0_RR_CLKDIV - RESET.

CMP0_RR clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
CMP0_RR_CLKDIV_HALT 

CMP0_RR_CLKDIV - HALT.

CMP0_RR clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
CMP0_RR_CLKDIV_UNSTAB 

CMP0_RR_CLKDIV - UNSTAB.

CMP0_RR clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
CMP1_FUNC_CLKDIV_DIV 

CMP1_FUNC_CLKDIV - DIV.

CMP1_FUNC clock divider control - Functional Clock Divider

CMP1_FUNC_CLKDIV_RESET 

CMP1_FUNC_CLKDIV - RESET.

CMP1_FUNC clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
CMP1_FUNC_CLKDIV_HALT 

CMP1_FUNC_CLKDIV - HALT.

CMP1_FUNC clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
CMP1_FUNC_CLKDIV_UNSTAB 

CMP1_FUNC_CLKDIV - UNSTAB.

CMP1_FUNC clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
CMP1_RR_CLKSEL_MUX 

CMP1_RR_CLKSEL - MUX.

CMP1_RR clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b101]CLK_1M
  • [0b011]CLK_IN
  • [0b010]FRO_HF_DIV
  • [0b000]FRO_12M
CMP1_RR_CLKDIV_DIV 

CMP1_RR_CLKDIV - CDIV.

CMP1_RR clock divider control - Functional Clock Divider

CMP1_RR_CLKDIV_RESET 

CMP1_RR_CLKDIV - CRESET.

CMP1_RR clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
CMP1_RR_CLKDIV_HALT 

CMP1_RR_CLKDIV - CHALT.

CMP1_RR clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
CMP1_RR_CLKDIV_UNSTAB 

CMP1_RR_CLKDIV - CUNSTAB.

CMP1_RR clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
DAC0_CLKSEL_MUX 

DAC0_CLKSEL - MUX.

DAC0 clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b101]CLK_1M
  • [0b011]CLK_IN
  • [0b010]FRO_HF_DIV
  • [0b000]FRO_12M
DAC0_CLKDIV_DIV 

DAC0_CLKDIV - DIV.

DAC0 clock divider control - Functional Clock Divider

DAC0_CLKDIV_RESET 

DAC0_CLKDIV - RESET.

DAC0 clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
DAC0_CLKDIV_HALT 

DAC0_CLKDIV - HALT.

DAC0 clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
DAC0_CLKDIV_UNSTAB 

DAC0_CLKDIV - UNSTAB.

DAC0 clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
FLEXCAN0_CLKSEL_MUX 

FLEXCAN0_CLKSEL - MUX.

FLEXCAN0 clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b011]CLK_IN
  • [0b010]FRO_HF_DIV
FLEXCAN0_CLKDIV_DIV 

FLEXCAN0_CLKDIV - DIV.

FLEXCAN0 clock divider control - Functional Clock Divider

FLEXCAN0_CLKDIV_RESET 

FLEXCAN0_CLKDIV - RESET.

FLEXCAN0 clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
FLEXCAN0_CLKDIV_HALT 

FLEXCAN0_CLKDIV - HALT.

FLEXCAN0 clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
FLEXCAN0_CLKDIV_UNSTAB 

FLEXCAN0_CLKDIV - UNSTAB.

FLEXCAN0 clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
LPI2C2_CLKSEL_MUX 

LPI2C2_CLKSEL - MUX.

LPI2C2 clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b101]CLK_1M
  • [0b011]CLK_IN
  • [0b010]FRO_HF_DIV
  • [0b000]FRO_12M
LPI2C2_CLKDIV_DIV 

LPI2C2_CLKDIV - DIV.

LPI2C2 clock divider control - Functional Clock Divider

LPI2C2_CLKDIV_RESET 

LPI2C2_CLKDIV - RESET.

LPI2C2 clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
LPI2C2_CLKDIV_HALT 

LPI2C2_CLKDIV - HALT.

LPI2C2 clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
LPI2C2_CLKDIV_UNSTAB 

LPI2C2_CLKDIV - UNSTAB.

LPI2C2 clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
LPI2C3_CLKSEL_MUX 

LPI2C3_CLKSEL - MUX.

LPI2C3 clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b101]CLK_1M
  • [0b011]CLK_IN
  • [0b010]FRO_HF_DIV
  • [0b000]FRO_12M
LPI2C3_CLKDIV_DIV 

LPI2C3_CLKDIV - DIV.

LPI2C3 clock divider control - Functional Clock Divider

LPI2C3_CLKDIV_RESET 

LPI2C3_CLKDIV - RESET.

LPI2C3 clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
LPI2C3_CLKDIV_HALT 

LPI2C3_CLKDIV - HALT.

LPI2C3 clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
LPI2C3_CLKDIV_UNSTAB 

LPI2C3_CLKDIV - UNSTAB.

LPI2C3 clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
DBG_TRACE_CLKSEL_MUX 

DBG_TRACE_CLKSEL - MUX.

DBG_TRACE clock selection control - Functional Clock Mux Select

  • [0b11]Reserved1(NO Clock)
  • [0b10]CLK_16K
  • [0b01]CLK_1M
  • [0b00]CPU_CLK
DBG_TRACE_CLKDIV_DIV 

DBG_TRACE_CLKDIV - DIV.

DBG_TRACE clock divider control - Functional Clock Divider

DBG_TRACE_CLKDIV_RESET 

DBG_TRACE_CLKDIV - RESET.

DBG_TRACE clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
DBG_TRACE_CLKDIV_HALT 

DBG_TRACE_CLKDIV - HALT.

DBG_TRACE clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
DBG_TRACE_CLKDIV_UNSTAB 

DBG_TRACE_CLKDIV - UNSTAB.

DBG_TRACE clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
CLKOUT_CLKSEL_MUX 

CLKOUT_CLKSEL - MUX.

CLKOUT clock selection control - Functional Clock Mux Select

  • [0b111]Reserved(NO Clock)
  • [0b110]SLOW_CLK
  • [0b011]CLK_16K
  • [0b010]CLK_IN
  • [0b001]FRO_HF_DIV
  • [0b000]FRO_12M
CLKOUT_CLKDIV_DIV 

CLKOUT_CLKDIV - DIV.

CLKOUT clock divider control - Functional Clock Divider

CLKOUT_CLKDIV_RESET 

CLKOUT_CLKDIV - RESET.

CLKOUT clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
CLKOUT_CLKDIV_HALT 

CLKOUT_CLKDIV - HALT.

CLKOUT clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
CLKOUT_CLKDIV_UNSTAB 

CLKOUT_CLKDIV - UNSTAB.

CLKOUT clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
SYSTICK_CLKSEL_MUX 

SYSTICK_CLKSEL - MUX.

SYSTICK clock selection control - Functional Clock Mux Select

  • [0b11]Reserved1(NO Clock)
  • [0b10]CLK_16K
  • [0b01]CLK_1M
  • [0b00]CPU_CLK
SYSTICK_CLKDIV_DIV 

SYSTICK_CLKDIV - DIV.

SYSTICK clock divider control - Functional Clock Divider

SYSTICK_CLKDIV_RESET 

SYSTICK_CLKDIV - RESET.

SYSTICK clock divider control - Reset divider counter

  • [0b0]Divider isn't reset
  • [0b1]Divider is reset
SYSTICK_CLKDIV_HALT 

SYSTICK_CLKDIV - HALT.

SYSTICK clock divider control - Halt divider counter

  • [0b0]Divider clock is running
  • [0b1]Divider clock is stopped
SYSTICK_CLKDIV_UNSTAB 

SYSTICK_CLKDIV - UNSTAB.

SYSTICK clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable
FRO_HF_DIV_CLKDIV_DIV 

FRO_HF_DIV_CLKDIV - DIV.

FRO_HF_DIV clock divider control - Functional Clock Divider

FRO_HF_DIV_CLKDIV_UNSTAB 

FRO_HF_DIV_CLKDIV - UNSTAB.

FRO_HF_DIV clock divider control - Divider status flag

  • [0b0]Divider clock is stable
  • [0b1]Clock frequency isn't stable