chip::spc 命名空間(Namespace)參考文件

複合項目
struct	ActiveModeCoreLdoOption
	Core LDO regulator options in Active mode. 更多...
struct	ActiveModeRegulatorsConfig
struct	CoreVoltageDetectConfig
struct	LowPowerModeCoreLdoOption
struct	LowPowerModeRegulatorsConfig
struct	LowPowerRequestConfig
	Low Power Request output pin configuration. 更多...
struct	Register
class	SPC
struct	SramVoltageConfig
struct	SystemVoltageDetectConfig
struct	VoltageDetectOption

列舉型態
enum struct	AnalogModuleControl : unsigned int {   VREF = 1UL << 0UL , USB_3V_DET = 1UL << 1UL , DAC0 = 1UL << 4UL , DAC1 = 1UL << 5UL ,   DAC2 = 1UL << 6UL , OPAMP0 = 1UL << 8UL , OPAMP1 = 1UL << 9UL , OPAMP2 = 1UL << 10UL ,   CMP0 = 1UL << 16UL , CMP1 = 1UL << 17UL , CMP2 = 1UL << 18UL , CMP0_DAC = 1UL << 20UL ,   CMP1_DAC = 1UL << 21UL , CMP2_DAC = 1UL << 22UL , ALL_MODULES = 0x770773UL }
enum struct	BandgapMode : unsigned char { DISABLED = 0x0U , ENABLED_BUFFER_DISABLED = 0x1U , ENABLED_BUFFER_ENABLED = 0x2U , RESERVED = 0x3U }
	SPC Bandgap mode enumeration in Active mode or Low Power mode. 更多...
enum struct	CoreLdoDriveStrength : unsigned char { LOW = 0x0U , NORMAL = 0x1U }
enum struct	CoreLdoVoltageLevel : unsigned char {   UNDER_DRIVE_VOLTAGE = 0x0U , RETENTION_VOLTAGE = 0x0U , MID_DRIVE_VOLTAGE = 0x1U , NORMAL_VOLTAGE = 0x2U ,   OVER_DRIVE_VOLTAGE = 0x3U }
	Core LDO regulator voltage level enumeration in Active mode or Low Power mode. 更多...
enum struct	Count : unsigned int { PD_STATUS = 1U }
enum struct	LowPowerRequestOutputOverride : unsigned char { NOT_FORCED = 0x0U , RESERVED = 0x1U , FORCED_LOW = 0x2U , FORCED_HIGH = 0x3U }
	SPC low power request output override. 更多...
enum struct	LowPowerRequestPinPolarity : unsigned char { HIGH_TRUE_POLARITY = 0x0U , LOW_TRUE_POLARITY = 0x1U }
	SPC low power request output pin polarity. 更多...
enum struct	LowVoltageLevelSelect : unsigned char { NORMAL_LEVEL = 0x0U , SAFE_LEVEL = 0x1U , HIGH_RANGE = 0x0U , LOW_RANGE = 0x1U }
enum struct	Mask : unsigned int {   VERID_FEATURE = 0x0000FFFFU , VERID_MINOR = 0x00FF0000U , VERID_MAJOR = 0xFF000000U , SC_BUSY = 0x00000001U ,   SC_SPC_LP_REQ = 0x00000002U , SC_SPC_LP_MODE = 0x000000F0U , SC_ISO_CLR = 0x00010000U , SC_SWITCH_STATE = 0x80000000U ,   LPREQ_CFG_LPREQOE = 0x00000001U , LPREQ_CFG_LPREQPOL = 0x00000002U , LPREQ_CFG_LPREQOV = 0x0000000CU , CFG_INTG_PWSWTCH_SLEEP_EN = 0x00000001U ,   CFG_INTG_PWSWTCH_WKUP_EN = 0x00000002U , CFG_INTG_PWSWTCH_SLEEP_ACTIVE_EN = 0x00000004U , CFG_INTG_PWSWTCH_WKUP_ACTIVE_EN = 0x00000008U , PD_STATUS_PWR_REQ_STATUS = 0x00000001U ,   PD_STATUS_PD_LP_REQ = 0x00000010U , PD_STATUS_LP_MODE = 0x00000F00U , SRAMCTL_VSM = 0x00000003U , SRAMCTL_REQ = 0x40000000U ,   SRAMCTL_ACK = 0x80000000U , SRAMRETLDO_REFTRIM_REFTRIM = 0x0000001FU , SRAMRETLDO_CNTRL_SRAMLDO_ON = 0x00000001U , SRAMRETLDO_CNTRL_SRAM_RET_EN = 0x00000F00U ,   ACTIVE_CFG_CORELDO_VDD_DS = 0x00000001U , ACTIVE_CFG_CORELDO_VDD_LVL = 0x0000000CU , ACTIVE_CFG_BGMODE = 0x00300000U , ACTIVE_CFG_VDD_VD_DISABLE = 0x00800000U ,   ACTIVE_CFG_CORE_LVDE = 0x01000000U , ACTIVE_CFG_SYS_LVDE = 0x02000000U , ACTIVE_CFG_SYS_HVDE = 0x10000000U , ACTIVE_CFG1_SOC_CNTRL = 0xFFFFFFFFU ,   LP_CFG_CORELDO_VDD_DS = 0x00000001U , LP_CFG_CORELDO_VDD_LVL = 0x0000000CU , LP_CFG_SRAMLDO_DPD_ON = 0x00080000U , LP_CFG_BGMODE = 0x00300000U ,   LP_CFG_LP_IREFEN = 0x00800000U , LP_CFG_CORE_LVDE = 0x01000000U , LP_CFG_SYS_LVDE = 0x02000000U , LP_CFG_SYS_HVDE = 0x10000000U ,   LP_CFG1_SOC_CNTRL = 0xFFFFFFFFU , LPWKUP_DELAY_LPWKUP_DELAY = 0x0000FFFFU , ACTIVE_VDELAY_ACTIVE_VDELAY = 0x0000FFFFU , VD_STAT_COREVDD_LVDF = 0x00000001U ,   VD_STAT_SYSVDD_LVDF = 0x00000002U , VD_STAT_SYSVDD_HVDF = 0x00000020U , VD_CORE_CFG_LVDRE = 0x00000001U , VD_CORE_CFG_LVDIE = 0x00000002U ,   VD_CORE_CFG_LOCK = 0x00010000U , VD_SYS_CFG_LVDRE = 0x00000001U , VD_SYS_CFG_LVDIE = 0x00000002U , VD_SYS_CFG_HVDRE = 0x00000004U ,   VD_SYS_CFG_HVDIE = 0x00000008U , VD_SYS_CFG_LVSEL = 0x00000100U , VD_SYS_CFG_LOCK = 0x00010000U , EVD_CFG_EVDISO = 0x00000007U ,   EVD_CFG_EVDLPISO = 0x00000700U , EVD_CFG_EVDSTAT = 0x00070000U }
	SPC_Register_Masks SPC Register Masks. 更多...
enum struct	PowerDomainID : unsigned char { DOMAIN0 = 0U , DOMAIN1 = 1U }
enum struct	PowerDomainLowPowerMode : unsigned char { SLEEP_WITH_SYS_CLOCK_RUNNING = 0U , DEEP_SLEEP_WITH_SYS_CLOCK_OFF = 1U , POWER_DOWN_WITH_SYS_CLOCK_OFF = 2U , DEEP_POWER_DOWN_WITH_SYS_CLOCK_OFF = 4U }
enum struct	PowerDomains : unsigned int { MAIN = 1UL << 16U , WAKE = 1UL << 17U }
enum struct	Shift : unsigned int {   VERID_FEATURE = 0U , VERID_MINOR = 16U , VERID_MAJOR = 24U , SC_BUSY = 0U ,   SC_SPC_LP_REQ = 1U , SC_SPC_LP_MODE = 4U , SC_ISO_CLR = 16U , SC_SWITCH_STATE = 31U ,   LPREQ_CFG_LPREQOE = 0U , LPREQ_CFG_LPREQPOL = 1U , LPREQ_CFG_LPREQOV = 2U , CFG_INTG_PWSWTCH_SLEEP_EN = 0U ,   CFG_INTG_PWSWTCH_WKUP_EN = 1U , CFG_INTG_PWSWTCH_SLEEP_ACTIVE_EN = 2U , CFG_INTG_PWSWTCH_WKUP_ACTIVE_EN = 3U , PD_STATUS_PWR_REQ_STATUS = 0U ,   PD_STATUS_PD_LP_REQ = 4U , PD_STATUS_LP_MODE = 8U , SRAMCTL_VSM = 0U , SRAMCTL_REQ = 30U ,   SRAMCTL_ACK = 31U , SRAMRETLDO_REFTRIM_REFTRIM = 0U , SRAMRETLDO_CNTRL_SRAMLDO_ON = 0U , SRAMRETLDO_CNTRL_SRAM_RET_EN = 8U ,   ACTIVE_CFG_CORELDO_VDD_DS = 0U , ACTIVE_CFG_CORELDO_VDD_LVL = 2U , ACTIVE_CFG_BGMODE = 20U , ACTIVE_CFG_VDD_VD_DISABLE = 23U ,   ACTIVE_CFG_CORE_LVDE = 24U , ACTIVE_CFG_SYS_LVDE = 25U , ACTIVE_CFG_SYS_HVDE = 28U , ACTIVE_CFG1_SOC_CNTRL = 0U ,   LP_CFG_CORELDO_VDD_DS = 0U , LP_CFG_CORELDO_VDD_LVL = 2U , LP_CFG_SRAMLDO_DPD_ON = 19U , LP_CFG_BGMODE = 20U ,   LP_CFG_LP_IREFEN = 23U , LP_CFG_CORE_LVDE = 24U , LP_CFG_SYS_LVDE = 25U , LP_CFG_SYS_HVDE = 28U ,   LP_CFG1_SOC_CNTRL = 0U , LPWKUP_DELAY_LPWKUP_DELAY = 0U , ACTIVE_VDELAY_ACTIVE_VDELAY = 0U , VD_STAT_COREVDD_LVDF = 0U ,   VD_STAT_SYSVDD_LVDF = 1U , VD_STAT_SYSVDD_HVDF = 5U , VD_CORE_CFG_LVDRE = 0U , VD_CORE_CFG_LVDIE = 1U ,   VD_CORE_CFG_LOCK = 16U , VD_SYS_CFG_LVDRE = 0U , VD_SYS_CFG_LVDIE = 1U , VD_SYS_CFG_HVDRE = 2U ,   VD_SYS_CFG_HVDIE = 3U , VD_SYS_CFG_LVSEL = 8U , VD_SYS_CFG_LOCK = 16U , EVD_CFG_EVDISO = 0U ,   EVD_CFG_EVDLPISO = 8U , EVD_CFG_EVDSTAT = 16U , EVD_CFG_REG_EVDISO = 0U , EVD_CFG_REG_EVDLPISO = 8U ,   EVD_CFG_REG_EVDSTAT = 16U }
enum struct	SramOperateVoltage : unsigned char { AT_1P0V = 0x1U , AT_1P1V = 0x2U , AT_1P2V = 0x3U }
	OperateVoltage. 更多...
enum struct	Status : unsigned int {   SUCCESS = +chip::Status::SUCCESS , FAIL = +chip::Status::FAIL , READONLY = +chip::Status::READONLY , OUT_OF_RANGE = +chip::Status::OUT_OF_RANGE ,   INVALID_ARGUMENT = +chip::Status::INVALID_ARGUMENT , TIMEOUT = +chip::Status::TIMEOUT , NO_TRANSFER_IN_PROGRESS = +chip::Status::NO_TRANSFER_IN_PROGRESS , BUSY = +chip::Status::BUSY ,   NO_DATA = +chip::Status::NO_DATA , SPC_BUSY = chip::MAKE_STATUS(chip::StatusGroup::SPC, 0U) , DCDC_LOW_DRIVE_STRENGTH_IGNORE = chip::MAKE_STATUS(chip::StatusGroup::SPC, 1U) , DCDC_PULSE_REFRESH_MODE_IGNORE = chip::MAKE_STATUS(chip::StatusGroup::SPC, 2U) ,   SYSLDO_OVER_DRIVE_VOLTAGE_FAIL = chip::MAKE_STATUS(chip::StatusGroup::SPC, 3U) , SYSLDO_LOW_DRIVE_STRENGTH_IGNORE = chip::MAKE_STATUS(chip::StatusGroup::SPC, 4U) , CORELDO_LOW_DRIVE_STRENGTH_IGNORE = chip::MAKE_STATUS(chip::StatusGroup::SPC, 5U) , CORELDO_VOLTAGE_WRONG = chip::MAKE_STATUS(chip::StatusGroup::SPC, 7U) ,   CORELDO_VOLTAGE_SET_FAIL = chip::MAKE_STATUS(chip::StatusGroup::SPC, 8U) , BANDGAP_MODE_WRONG = chip::MAKE_STATUS(chip::StatusGroup::SPC, 6U) }
	SPC status enumeration. 更多...
enum struct	VoltageDetectFlag : unsigned int { SYSTEM_VDD_HIGH = +Mask::VD_STAT_SYSVDD_HVDF , SYSTEM_VDD_LOW = +Mask::VD_STAT_SYSVDD_LVDF , CORE_VDD_LOW = +Mask::VD_STAT_COREVDD_LVDF }
	Voltage Detect Status Flags. 更多...

函式
constexpr unsigned char	operator+ (BandgapMode e)
constexpr unsigned char	operator+ (CoreLdoDriveStrength e)
constexpr unsigned char	operator+ (CoreLdoVoltageLevel e)
constexpr unsigned int	operator+ (Count e)
constexpr unsigned char	operator+ (LowPowerRequestOutputOverride e)
constexpr unsigned char	operator+ (LowPowerRequestPinPolarity e)
constexpr unsigned int	operator+ (Mask e)
constexpr unsigned char	operator+ (PowerDomainID e)
constexpr unsigned int	operator+ (Shift e)
constexpr unsigned char	operator+ (SramOperateVoltage e)
constexpr unsigned int	operator+ (Status e)

變數
Register &	SPC0

詳細描述

Copyright (c) 2020 ZxyKira All rights reserved.

SPDX-License-Identifier: MIT

列舉型態說明文件

AnalogModuleControl

enum struct chip::spc::AnalogModuleControl : unsigned int

strong

列舉值
VREF	Enable/disable VREF in active or low-power modes.
USB_3V_DET	Enable/disable USB3V_Det in active or low-power modes.
DAC0	Enable/disable DAC0 in active or low-power modes.
DAC1	Enable/disable DAC1 in active or low-power modes.
DAC2	Enable/disable DAC2 in active or low-power modes.
OPAMP0	Enable/disable OPAMP0 in active or low-power modes.
OPAMP1	Enable/disable OPAMP1 in active or low-power modes.
OPAMP2	Enable/disable OPAMP2 in active or low-power modes.
CMP0	Enable/disable CMP0 in active or low-power modes.
CMP1	Enable/disable CMP1 in active or low-power modes.
CMP2	Enable/disable CMP2 in active or low-power modes.
CMP0_DAC	Enable/disable CMP0_DAC in active or low-power modes.
CMP1_DAC	Enable/disable CMP1_DAC in active or low-power modes.
CMP2_DAC	Enable/disable CMP2_DAC in active or low-power modes.
ALL_MODULES	Enable/disable all modules in active or low-power modes.

BandgapMode

enum struct chip::spc::BandgapMode : unsigned char

strong

SPC Bandgap mode enumeration in Active mode or Low Power mode.

列舉值
DISABLED	Bandgap disabled.
ENABLED_BUFFER_DISABLED	Bandgap enabled with Buffer disabled.
ENABLED_BUFFER_ENABLED	Bandgap enabled with Buffer enabled.
RESERVED	Reserved.

CoreLdoDriveStrength

enum struct chip::spc::CoreLdoDriveStrength : unsigned char

strong

列舉值
LOW	Core LDO VDD regulator Drive Strength set to low.
NORMAL	Core LDO VDD regulator Drive Strength set to Normal.

CoreLdoVoltageLevel

enum struct chip::spc::CoreLdoVoltageLevel : unsigned char

strong

Core LDO regulator voltage level enumeration in Active mode or Low Power mode.

列舉值
UNDER_DRIVE_VOLTAGE	過時 UNDER_DRIVE_VOLTAGE deprecated to align with description of latest RM please use RETENTION_VOLTAGE as instead.
RETENTION_VOLTAGE	MID_DRIVE_VOLTAGE. Core LDO VDD regulator regulate to retention voltage please note that only useful in low power modes and not all devices support this options please refer to devices' RM for details.
MID_DRIVE_VOLTAGE	MID_DRIVE_VOLTAGE. Core LDO VDD regulator regulate to Mid Drive Voltage
NORMAL_VOLTAGE	NORMAL_VOLTAGE. Core LDO VDD regulator regulate to Normal Voltage.
OVER_DRIVE_VOLTAGE	OVER_DRIVE_VOLTAGE. Core LDO VDD regulator regulate to overdrive Voltage.

Count

enum struct chip::spc::Count : unsigned int

strong

列舉值
PD_STATUS	PD_STATUS - SPC_PD_STATUS. SPC Power Domain Mode Status - The count of SPC_PD_STATUS

LowPowerRequestOutputOverride

enum struct chip::spc::LowPowerRequestOutputOverride : unsigned char

strong

SPC low power request output override.

列舉值
NOT_FORCED	Not Forced.
RESERVED	Reserved.
FORCED_LOW	Forced Low (Ignore LowPower request output polarity setting.)
FORCED_HIGH	Forced High (Ignore LowPower request output polarity setting.)

LowPowerRequestPinPolarity

enum struct chip::spc::LowPowerRequestPinPolarity : unsigned char

strong

SPC low power request output pin polarity.

列舉值
HIGH_TRUE_POLARITY	Control the High Polarity of the Low Power Reqest Pin.
LOW_TRUE_POLARITY	Control the Low Polarity of the Low Power Reqest Pin.

LowVoltageLevelSelect

enum struct chip::spc::LowVoltageLevelSelect : unsigned char

strong

列舉值
NORMAL_LEVEL	過時 NORMAL_LEVEL please use HIGH_RANGE as instead.
SAFE_LEVEL	過時 SAFE_LEVEL please use LOW_RANGE as instead.
HIGH_RANGE	High range LVD threshold.
LOW_RANGE	Low range LVD threshold.

Mask

enum struct chip::spc::Mask : unsigned int

strong

SPC_Register_Masks SPC Register Masks.

列舉值
VERID_FEATURE	VERID - FEATURE. Version ID - Feature Specification Number [0b0000000000000000..Standard features *..
VERID_MINOR	VERID - MINOR. Version ID - Minor Version Number
VERID_MAJOR	VERID - MAJOR. Version ID - Major Version Number
SC_BUSY	SC - BUSY. Status Control - SPC Busy Status Flag [0b0]Not busy [0b1]Busy
SC_SPC_LP_REQ	SC - SPC_LP_REQ. Status Control - SPC Power Mode Configuration Status Flag [0b0]SPC is in Active mode; the ACTIVE_CFG register has control [0b1]All power domains requested low-power mode; SPC entered a low-power state; power-mode configuration based on the LP_CFG register [0b0]No effect [0b1]Clear the flag
SC_SPC_LP_MODE	SC - SPC_LP_MODE. Status Control - Power Domain Low-Power Mode Request [0b0000]Sleep mode with system clock running [0b0001]DSLEEP with system clock off [0b0010]PDOWN with system clock off [0b0100] [0b1000]DPDOWN with system clock off
SC_ISO_CLR	SC - ISO_CLR. Status Control - Isolation Clear Flags
SC_SWITCH_STATE	SC - SWITCH_STATE. Status Control - Power Switch State [0b0]Off [0b1]On
LPREQ_CFG_LPREQOE	LPREQ_CFG - LPREQOE. Low-Power Request Configuration - Low-Power Request Output Enable [0b0]Disable [0b1]Enable
LPREQ_CFG_LPREQPOL	LPREQ_CFG - LPREQPOL. Low-Power Request Configuration - Low-Power Request Output Pin Polarity Control [0b0]High [0b1]Low
LPREQ_CFG_LPREQOV	LPREQ_CFG - LPREQOV. Low-Power Request Configuration - Low-Power Request Output Override [0b00]Not forced [0b01] [0b10]Forced low (ignore LPREQPOL settings) [0b11]Forced high (ignore LPREQPOL settings)
CFG_INTG_PWSWTCH_SLEEP_EN	CFG - INTG_PWSWTCH_SLEEP_EN. SPC Configuration - Integrated Power Switch Sleep Enable [0b0]Disable [0b1]Enable
CFG_INTG_PWSWTCH_WKUP_EN	CFG - INTG_PWSWTCH_WKUP_EN. SPC Configuration - Integrated Power Switch Wake-up Enable [0b0]Disable [0b1]Enable
CFG_INTG_PWSWTCH_SLEEP_ACTIVE_EN	CFG - INTG_PWSWTCH_SLEEP_ACTIVE_EN. SPC Configuration - Integrated Power Switch Active Enable [0b0]Disable [0b1]Enable
CFG_INTG_PWSWTCH_WKUP_ACTIVE_EN	CFG - INTG_PWSWTCH_WKUP_ACTIVE_EN. SPC Configuration - Integrated Power Switch Wake-up Enable [0b0]Disable [0b1]Enable
PD_STATUS_PWR_REQ_STATUS	PD_STATUS - PWR_REQ_STATUS. SPC Power Domain Mode Status - Power Request Status Flag [0b0]Did not request [0b1]Requested
PD_STATUS_PD_LP_REQ	PD_STATUS - PD_LP_REQ. SPC Power Domain Mode Status - Power Domain Low Power Request Flag [0b0]Did not request [0b1]Requested
PD_STATUS_LP_MODE	PD_STATUS - LP_MODE. SPC Power Domain Mode Status - Power Domain Low Power Mode Request [0b0000]SLEEP with system clock running [0b0001]DSLEEP with system clock off [0b0010]PDOWN with system clock off [0b0100] [0b1000]DPDOWN with system clock off
SRAMCTL_VSM	SRAMCTL - VSM. SRAM Control - Voltage Select Margin [0b00] [0b01]1.0 V [0b10]1.1 V [0b11]SRAM configured for 1.2 V operation
SRAMCTL_REQ	SRAMCTL - REQ. SRAM Control - SRAM Voltage Update Request [0b0]Do not request [0b1]Request
SRAMCTL_ACK	SRAMCTL - ACK. SRAM Control - SRAM Voltage Update Request Acknowledge [0b0]Not acknowledged [0b1]Acknowledged
SRAMRETLDO_REFTRIM_REFTRIM	SRAMRETLDO_REFTRIM - REFTRIM. SRAM Retention Reference Trim - Reference Trim. Voltage range is around 0.48V - 0.85V. Trim step is 12 mV.
SRAMRETLDO_CNTRL_SRAMLDO_ON	SRAMRETLDO_CNTRL - SRAMLDO_ON. SRAM Retention LDO Control - SRAM LDO Regulator Enable [0b0]Disable [0b1]Enable
SRAMRETLDO_CNTRL_SRAM_RET_EN	SRAMRETLDO_CNTRL - SRAM_RET_EN. SRAM Retention LDO Control - SRAM Retention
ACTIVE_CFG_CORELDO_VDD_DS	ACTIVE_CFG - CORELDO_VDD_DS. Active Power Mode Configuration - LDO_CORE VDD Drive Strength [0b0]Low [0b1]Normal
ACTIVE_CFG_CORELDO_VDD_LVL	ACTIVE_CFG - CORELDO_VDD_LVL. Active Power Mode Configuration - LDO_CORE VDD Regulator Voltage Level [0b00] [0b01]Regulate to mid voltage (1.0 V) [0b10]Regulate to normal voltage (1.1 V) [0b11]Regulate to overdrive voltage (1.15 V)
ACTIVE_CFG_BGMODE	ACTIVE_CFG - BGMODE. Active Power Mode Configuration - Bandgap Mode [0b00]Bandgap disabled [0b01]Bandgap enabled, buffer disabled [0b10]Bandgap enabled, buffer enabled [0b11]
ACTIVE_CFG_VDD_VD_DISABLE	ACTIVE_CFG - VDD_VD_DISABLE. Active Power Mode Configuration - VDD Voltage Detect Disable [0b0]Enable [0b1]Disable
ACTIVE_CFG_CORE_LVDE	ACTIVE_CFG - CORE_LVDE. Active Power Mode Configuration - Core Low-Voltage Detection Enable [0b0]Disable [0b1]Enable
ACTIVE_CFG_SYS_LVDE	ACTIVE_CFG - SYS_LVDE. Active Power Mode Configuration - System Low-Voltage Detection Enable [0b0]Disable [0b1]Enable
ACTIVE_CFG_SYS_HVDE	ACTIVE_CFG - SYS_HVDE. Active Power Mode Configuration - System High-Voltage Detection Enable [0b0]Disable [0b1]Enable
ACTIVE_CFG1_SOC_CNTRL	ACTIVE_CFG1 - SOC_CNTRL. Active Power Mode Configuration 1 - Active Config Chip Control
LP_CFG_CORELDO_VDD_DS	LP_CFG - CORELDO_VDD_DS. Low-Power Mode Configuration - LDO_CORE VDD Drive Strength [0b0]Low [0b1]Normal
LP_CFG_CORELDO_VDD_LVL	LP_CFG - CORELDO_VDD_LVL. Low-Power Mode Configuration - LDO_CORE VDD Regulator Voltage Level [0b00]Reserved [0b01]Mid voltage (1.0 V) [0b10]Normal voltage (1.1 V) [0b11]Overdrive voltage (1.15 V) *]
LP_CFG_SRAMLDO_DPD_ON	LP_CFG - SRAMLDO_DPD_ON. Low-Power Mode Configuration - SRAM_LDO Deep Power Low Power IREF Enable [0b0]Low Power IREF is disabled for power saving in Deep Power Down mode [0b1]Low Power IREF is enabled
LP_CFG_BGMODE	LP_CFG - BGMODE. Low-Power Mode Configuration - Bandgap Mode [0b00]Bandgap disabled [0b01]Bandgap enabled, buffer disabled [0b10]Bandgap enabled, buffer enabled [0b11]
LP_CFG_LP_IREFEN	LP_CFG - LP_IREFEN. Low-Power Mode Configuration - Low-Power IREF Enable [0b0]Disable for power saving in Deep Power Down mode [0b1]Enable
LP_CFG_CORE_LVDE	LP_CFG - CORE_LVDE. Low-Power Mode Configuration - Core Low Voltage Detect Enable [0b0]Disable [0b1]Enable
LP_CFG_SYS_LVDE	LP_CFG - SYS_LVDE. Low-Power Mode Configuration - System Low Voltage Detect Enable [0b0]Disable [0b1]Enable
LP_CFG_SYS_HVDE	LP_CFG - SYS_HVDE. Low-Power Mode Configuration - System High Voltage Detect Enable [0b0]Disable [0b1]Enable
LP_CFG1_SOC_CNTRL	LP_CFG1 - SOC_CNTRL. Low Power Mode Configuration 1 - Low-Power Configuration Chip Control
LPWKUP_DELAY_LPWKUP_DELAY	LPWKUP_DELAY - LPWKUP_DELAY. Low Power Wake-Up Delay - Low-Power Wake-Up Delay
ACTIVE_VDELAY_ACTIVE_VDELAY	ACTIVE_VDELAY - ACTIVE_VDELAY. Active Voltage Trim Delay - Active Voltage Delay
VD_STAT_COREVDD_LVDF	VD_STAT - COREVDD_LVDF. Voltage Detect Status - Core Low-Voltage Detect Flag [0b0]Event not detected [0b1]Event detected [0b0]No effect [0b1]Clear the flag
VD_STAT_SYSVDD_LVDF	VD_STAT - SYSVDD_LVDF. Voltage Detect Status - System Low-Voltage Detect Flag [0b0]Event not detected [0b1]Event detected [0b0]No effect [0b1]Clear the flag
VD_STAT_SYSVDD_HVDF	VD_STAT - SYSVDD_HVDF. Voltage Detect Status - System HVD Flag [0b0]Event not detected [0b1]Event detected [0b0]No effect [0b1]Clear the flag
VD_CORE_CFG_LVDRE	VD_CORE_CFG - LVDRE. Core Voltage Detect Configuration - Core LVD Reset Enable [0b0]Disable [0b1]Enable
VD_CORE_CFG_LVDIE	VD_CORE_CFG - LVDIE. Core Voltage Detect Configuration - Core LVD Interrupt Enable [0b0]Disable [0b1]Enable
VD_CORE_CFG_LOCK	VD_CORE_CFG - LOCK. Core Voltage Detect Configuration - Core Voltage Detect Reset Enable Lock [0b0]Allow [0b1]Deny
VD_SYS_CFG_LVDRE	VD_SYS_CFG - LVDRE. System Voltage Detect Configuration - System LVD Reset Enable [0b0]Disable [0b1]Enable
VD_SYS_CFG_LVDIE	VD_SYS_CFG - LVDIE. System Voltage Detect Configuration - System LVD Interrupt Enable [0b0]Disable [0b1]Enable
VD_SYS_CFG_HVDRE	VD_SYS_CFG - HVDRE. System Voltage Detect Configuration - System HVD Reset Enable [0b0]Disable [0b1]Enable
VD_SYS_CFG_HVDIE	VD_SYS_CFG - HVDIE. System Voltage Detect Configuration - System HVD Interrupt Enable [0b0]Disable [0b1]Enable
VD_SYS_CFG_LVSEL	VD_SYS_CFG - LVSEL. System Voltage Detect Configuration - System Low-Voltage Level Select [0b0]Normal [0b1]Safe
VD_SYS_CFG_LOCK	VD_SYS_CFG - LOCK. System Voltage Detect Configuration - System Voltage Detect Reset Enable Lock [0b0]Allow [0b1]Deny
EVD_CFG_EVDISO	EVD_CFG - EVDISO. External Voltage Domain Configuration - External Voltage Domain Isolation
EVD_CFG_EVDLPISO	EVD_CFG - EVDLPISO. External Voltage Domain Configuration - External Voltage Domain Low-Power Isolation
EVD_CFG_EVDSTAT	EVD_CFG - EVDSTAT. External Voltage Domain Configuration - External Voltage Domain Status

PowerDomainID

enum struct chip::spc::PowerDomainID : unsigned char

strong

列舉值
DOMAIN0	Power domain0, the connected power domain is chip specific.
DOMAIN1	Power domain1, the connected power domain is chip specific.

PowerDomainLowPowerMode

enum struct chip::spc::PowerDomainLowPowerMode : unsigned char

strong

列舉值
SLEEP_WITH_SYS_CLOCK_RUNNING	Power domain request SLEEP mode with SYS clock running.
DEEP_SLEEP_WITH_SYS_CLOCK_OFF	Power domain request deep sleep mode with system clock off.
POWER_DOWN_WITH_SYS_CLOCK_OFF	Power domain request power down mode with system clock off.
DEEP_POWER_DOWN_WITH_SYS_CLOCK_OFF	Power domain request deep power down mode with system clock off.

PowerDomains

enum struct chip::spc::PowerDomains : unsigned int

strong

列舉值
MAIN	Peripherals and IO pads retain in MAIN Power Domain.
WAKE	Peripherals and IO pads retain in WAKE Power Domain.

Shift

enum struct chip::spc::Shift : unsigned int

strong

列舉值
VERID_FEATURE	VERID - FEATURE. Version ID - Feature Specification Number [0b0000000000000000..Standard features *..
VERID_MINOR	VERID - MINOR. Version ID - Minor Version Number
VERID_MAJOR	VERID - MAJOR. Version ID - Major Version Number
SC_BUSY	SC - BUSY. Status Control - SPC Busy Status Flag [0b0]Not busy [0b1]Busy
SC_SPC_LP_REQ	SC - SPC_LP_REQ. Status Control - SPC Power Mode Configuration Status Flag [0b0]SPC is in Active mode; the ACTIVE_CFG register has control [0b1]All power domains requested low-power mode; SPC entered a low-power state; power-mode configuration based on the LP_CFG register [0b0]No effect [0b1]Clear the flag
SC_SPC_LP_MODE	SC - SPC_LP_MODE. Status Control - Power Domain Low-Power Mode Request [0b0000]Sleep mode with system clock running [0b0001]DSLEEP with system clock off [0b0010]PDOWN with system clock off [0b0100] [0b1000]DPDOWN with system clock off
SC_ISO_CLR	SC - ISO_CLR. Status Control - Isolation Clear Flags
SC_SWITCH_STATE	SC - SWITCH_STATE. Status Control - Power Switch State [0b0]Off [0b1]On
LPREQ_CFG_LPREQOE	LPREQ_CFG - LPREQOE. Low-Power Request Configuration - Low-Power Request Output Enable [0b0]Disable [0b1]Enable
LPREQ_CFG_LPREQPOL	LPREQ_CFG - LPREQPOL. Low-Power Request Configuration - Low-Power Request Output Pin Polarity Control [0b0]High [0b1]Low
LPREQ_CFG_LPREQOV	LPREQ_CFG - LPREQOV. Low-Power Request Configuration - Low-Power Request Output Override [0b00]Not forced [0b01] [0b10]Forced low (ignore LPREQPOL settings) [0b11]Forced high (ignore LPREQPOL settings)
CFG_INTG_PWSWTCH_SLEEP_EN	CFG - INTG_PWSWTCH_SLEEP_EN. SPC Configuration - Integrated Power Switch Sleep Enable [0b0]Disable [0b1]Enable
CFG_INTG_PWSWTCH_WKUP_EN	CFG - INTG_PWSWTCH_WKUP_EN. SPC Configuration - Integrated Power Switch Wake-up Enable [0b0]Disable [0b1]Enable
CFG_INTG_PWSWTCH_SLEEP_ACTIVE_EN	CFG - INTG_PWSWTCH_SLEEP_ACTIVE_EN. SPC Configuration - Integrated Power Switch Active Enable [0b0]Disable [0b1]Enable
CFG_INTG_PWSWTCH_WKUP_ACTIVE_EN	CFG - INTG_PWSWTCH_WKUP_ACTIVE_EN. SPC Configuration - Integrated Power Switch Wake-up Enable [0b0]Disable [0b1]Enable
PD_STATUS_PWR_REQ_STATUS	PD_STATUS - PWR_REQ_STATUS. SPC Power Domain Mode Status - Power Request Status Flag [0b0]Did not request [0b1]Requested
PD_STATUS_PD_LP_REQ	PD_STATUS - PD_LP_REQ. SPC Power Domain Mode Status - Power Domain Low Power Request Flag [0b0]Did not request [0b1]Requested
PD_STATUS_LP_MODE	PD_STATUS - LP_MODE. SPC Power Domain Mode Status - Power Domain Low Power Mode Request [0b0000]SLEEP with system clock running [0b0001]DSLEEP with system clock off [0b0010]PDOWN with system clock off [0b0100] [0b1000]DPDOWN with system clock off
SRAMCTL_VSM	SRAMCTL - VSM. SRAM Control - Voltage Select Margin [0b00] [0b01]1.0 V [0b10]1.1 V [0b11]SRAM configured for 1.2 V operation
SRAMCTL_REQ	SRAMCTL - REQ. SRAM Control - SRAM Voltage Update Request [0b0]Do not request [0b1]Request
SRAMCTL_ACK	SRAMCTL - ACK. SRAM Control - SRAM Voltage Update Request Acknowledge [0b0]Not acknowledged [0b1]Acknowledged
SRAMRETLDO_REFTRIM_REFTRIM	SRAMRETLDO_REFTRIM - REFTRIM. SRAM Retention Reference Trim - Reference Trim. Voltage range is around 0.48V - 0.85V. Trim step is 12 mV.
SRAMRETLDO_CNTRL_SRAMLDO_ON	SRAMRETLDO_CNTRL - SRAMLDO_ON. SRAM Retention LDO Control - SRAM LDO Regulator Enable [0b0]Disable [0b1]Enable
SRAMRETLDO_CNTRL_SRAM_RET_EN	SRAMRETLDO_CNTRL - SRAM_RET_EN. SRAM Retention LDO Control - SRAM Retention
ACTIVE_CFG_CORELDO_VDD_DS	ACTIVE_CFG - CORELDO_VDD_DS. Active Power Mode Configuration - LDO_CORE VDD Drive Strength [0b0]Low [0b1]Normal
ACTIVE_CFG_CORELDO_VDD_LVL	ACTIVE_CFG - CORELDO_VDD_LVL. Active Power Mode Configuration - LDO_CORE VDD Regulator Voltage Level [0b00] [0b01]Regulate to mid voltage (1.0 V) [0b10]Regulate to normal voltage (1.1 V) [0b11]Regulate to overdrive voltage (1.15 V)
ACTIVE_CFG_BGMODE	ACTIVE_CFG - BGMODE. Active Power Mode Configuration - Bandgap Mode [0b00]Bandgap disabled [0b01]Bandgap enabled, buffer disabled [0b10]Bandgap enabled, buffer enabled [0b11]
ACTIVE_CFG_VDD_VD_DISABLE	ACTIVE_CFG - VDD_VD_DISABLE. Active Power Mode Configuration - VDD Voltage Detect Disable [0b0]Enable [0b1]Disable
ACTIVE_CFG_CORE_LVDE	ACTIVE_CFG - CORE_LVDE. Active Power Mode Configuration - Core Low-Voltage Detection Enable [0b0]Disable [0b1]Enable
ACTIVE_CFG_SYS_LVDE	ACTIVE_CFG - SYS_LVDE. Active Power Mode Configuration - System Low-Voltage Detection Enable [0b0]Disable [0b1]Enable
ACTIVE_CFG_SYS_HVDE	ACTIVE_CFG - SYS_HVDE. Active Power Mode Configuration - System High-Voltage Detection Enable [0b0]Disable [0b1]Enable
ACTIVE_CFG1_SOC_CNTRL	ACTIVE_CFG1 - SOC_CNTRL. Active Power Mode Configuration 1 - Active Config Chip Control
LP_CFG_CORELDO_VDD_DS	LP_CFG - CORELDO_VDD_DS. Low-Power Mode Configuration - LDO_CORE VDD Drive Strength [0b0]Low [0b1]Normal
LP_CFG_CORELDO_VDD_LVL	LP_CFG - CORELDO_VDD_LVL. Low-Power Mode Configuration - LDO_CORE VDD Regulator Voltage Level [0b00]Reserved [0b01]Mid voltage (1.0 V) [0b10]Normal voltage (1.1 V) [0b11]Overdrive voltage (1.15 V) *]
LP_CFG_SRAMLDO_DPD_ON	LP_CFG - SRAMLDO_DPD_ON. Low-Power Mode Configuration - SRAM_LDO Deep Power Low Power IREF Enable [0b0]Low Power IREF is disabled for power saving in Deep Power Down mode [0b1]Low Power IREF is enabled
LP_CFG_BGMODE	LP_CFG - BGMODE. Low-Power Mode Configuration - Bandgap Mode [0b00]Bandgap disabled [0b01]Bandgap enabled, buffer disabled [0b10]Bandgap enabled, buffer enabled [0b11]
LP_CFG_LP_IREFEN	LP_CFG - LP_IREFEN. Low-Power Mode Configuration - Low-Power IREF Enable [0b0]Disable for power saving in Deep Power Down mode [0b1]Enable
LP_CFG_CORE_LVDE	LP_CFG - CORE_LVDE. Low-Power Mode Configuration - Core Low Voltage Detect Enable [0b0]Disable [0b1]Enable
LP_CFG_SYS_LVDE	LP_CFG - SYS_LVDE. Low-Power Mode Configuration - System Low Voltage Detect Enable [0b0]Disable [0b1]Enable
LP_CFG_SYS_HVDE	LP_CFG - SYS_HVDE. Low-Power Mode Configuration - System High Voltage Detect Enable [0b0]Disable [0b1]Enable
LP_CFG1_SOC_CNTRL	LP_CFG1 - SOC_CNTRL. Low Power Mode Configuration 1 - Low-Power Configuration Chip Control
LPWKUP_DELAY_LPWKUP_DELAY	LPWKUP_DELAY - LPWKUP_DELAY. Low Power Wake-Up Delay - Low-Power Wake-Up Delay
ACTIVE_VDELAY_ACTIVE_VDELAY	ACTIVE_VDELAY - ACTIVE_VDELAY. Active Voltage Trim Delay - Active Voltage Delay
VD_STAT_COREVDD_LVDF	VD_STAT - COREVDD_LVDF. Voltage Detect Status - Core Low-Voltage Detect Flag [0b0]Event not detected [0b1]Event detected [0b0]No effect [0b1]Clear the flag
VD_STAT_SYSVDD_LVDF	VD_STAT - SYSVDD_LVDF. Voltage Detect Status - System Low-Voltage Detect Flag [0b0]Event not detected [0b1]Event detected [0b0]No effect [0b1]Clear the flag
VD_STAT_SYSVDD_HVDF	VD_STAT - SYSVDD_HVDF. Voltage Detect Status - System HVD Flag [0b0]Event not detected [0b1]Event detected [0b0]No effect [0b1]Clear the flag
VD_CORE_CFG_LVDRE	VD_CORE_CFG - LVDRE. Core Voltage Detect Configuration - Core LVD Reset Enable [0b0]Disable [0b1]Enable
VD_CORE_CFG_LVDIE	VD_CORE_CFG - LVDIE. Core Voltage Detect Configuration - Core LVD Interrupt Enable [0b0]Disable [0b1]Enable
VD_CORE_CFG_LOCK	VD_CORE_CFG - LOCK. Core Voltage Detect Configuration - Core Voltage Detect Reset Enable Lock [0b0]Allow [0b1]Deny
VD_SYS_CFG_LVDRE	VD_SYS_CFG - LVDRE. System Voltage Detect Configuration - System LVD Reset Enable [0b0]Disable [0b1]Enable
VD_SYS_CFG_LVDIE	VD_SYS_CFG - LVDIE. System Voltage Detect Configuration - System LVD Interrupt Enable [0b0]Disable [0b1]Enable
VD_SYS_CFG_HVDRE	VD_SYS_CFG - HVDRE. System Voltage Detect Configuration - System HVD Reset Enable [0b0]Disable [0b1]Enable
VD_SYS_CFG_HVDIE	VD_SYS_CFG - HVDIE. System Voltage Detect Configuration - System HVD Interrupt Enable [0b0]Disable [0b1]Enable
VD_SYS_CFG_LVSEL	VD_SYS_CFG - LVSEL. System Voltage Detect Configuration - System Low-Voltage Level Select [0b0]Normal [0b1]Safe
VD_SYS_CFG_LOCK	VD_SYS_CFG - LOCK. System Voltage Detect Configuration - System Voltage Detect Reset Enable Lock [0b0]Allow [0b1]Deny
EVD_CFG_EVDISO	EVD_CFG - EVDISO. External Voltage Domain Configuration - External Voltage Domain Isolation
EVD_CFG_EVDLPISO	EVD_CFG - EVDLPISO. External Voltage Domain Configuration - External Voltage Domain Low-Power Isolation
EVD_CFG_EVDSTAT	EVD_CFG - EVDSTAT. External Voltage Domain Configuration - External Voltage Domain Status

SramOperateVoltage

enum struct chip::spc::SramOperateVoltage : unsigned char

strong

OperateVoltage.

The list of the operating voltage for the SRAM's read/write timing margin.

列舉值
AT_1P0V	SRAM configured for 1.0V operation.
AT_1P1V	SRAM configured for 1.1V operation.
AT_1P2V	SRAM configured for 1.2V operation.

Status

enum struct chip::spc::Status : unsigned int

strong

SPC status enumeration.

註

Some device(such as MCXA family) do not equip DCDC or System LDO, please refer to the reference manual to check.

列舉值
SUCCESS	Generic status for Success.
FAIL	Generic status for Fail.
READONLY	Generic status for read only failure.
OUT_OF_RANGE	Generic status for out of range access.
INVALID_ARGUMENT	Generic status for invalid argument check.
TIMEOUT	Generic status for timeout.
NO_TRANSFER_IN_PROGRESS	Generic status for no transfer in progress.
BUSY	Generic status for module is busy.
NO_DATA	Generic status for no data is found for the operation.
SPC_BUSY	The SPC instance is busy executing any type of power mode transition.
DCDC_LOW_DRIVE_STRENGTH_IGNORE	DCDC Low drive strength setting be ignored for LVD/HVD enabled.
DCDC_PULSE_REFRESH_MODE_IGNORE	DCDC Pulse Refresh Mode drive strength setting be ignored for LVD/HVD enabled.
SYSLDO_OVER_DRIVE_VOLTAGE_FAIL	SYS LDO regulate to Over drive voltage failed for SYS LDO HVD must be disabled.
SYSLDO_LOW_DRIVE_STRENGTH_IGNORE	SYS LDO Low driver strength setting be ignored for LDO LVD/HVD enabled.
CORELDO_LOW_DRIVE_STRENGTH_IGNORE	CORE LDO Low driver strength setting be ignored for LDO LVD/HVD enabled.
CORELDO_VOLTAGE_WRONG	Core LDO voltage is wrong.
CORELDO_VOLTAGE_SET_FAIL	Core LDO voltage set fail.
BANDGAP_MODE_WRONG	Selected Bandgap Mode wrong.

VoltageDetectFlag

enum struct chip::spc::VoltageDetectFlag : unsigned int

strong

Voltage Detect Status Flags.

列舉值
SYSTEM_VDD_HIGH	System VDD High-Voltage detect flag.
SYSTEM_VDD_LOW	System VDD Low-Voltage detect flag.
CORE_VDD_LOW	Core VDD Low-Voltage detect flag.