複合項目
class	LPI2C

struct	Register

列舉型態
enum struct	Mask : unsigned int { VERID_FEATURE = 0xFFFFU , VERID_MINOR = 0xFF0000U , VERID_MAJOR = 0xFF000000U , PARAM_MTXFIFO = 0xFU , PARAM_MRXFIFO = 0xF00U , MCR_MEN = 0x1U , MCR_RST = 0x2U , MCR_DOZEN = 0x4U , MCR_DBGEN = 0x8U , MCR_RTF = 0x100U , MCR_RRF = 0x200U , MSR_TDF = 0x1U , MSR_RDF = 0x2U , MSR_EPF = 0x100U , MSR_SDF = 0x200U , MSR_NDF = 0x400U , MSR_ALF = 0x800U , MSR_FEF = 0x1000U , MSR_PLTF = 0x2000U , MSR_DMF = 0x4000U , MSR_STF = 0x8000U , MSR_MBF = 0x1000000U , MSR_BBF = 0x2000000U , MIER_TDIE = 0x1U , MIER_RDIE = 0x2U , MIER_EPIE = 0x100U , MIER_SDIE = 0x200U , MIER_NDIE = 0x400U , MIER_ALIE = 0x800U , MIER_FEIE = 0x1000U , MIER_PLTIE = 0x2000U , MIER_DMIE = 0x4000U , MIER_STIE = 0x8000U , MDER_TDDE = 0x1U , MDER_RDDE = 0x2U , MCFGR0_HREN = 0x1U , MCFGR0_HRPOL = 0x2U , MCFGR0_HRSEL = 0x4U , MCFGR0_HRDIR = 0x8U , MCFGR0_CIRFIFO = 0x100U , MCFGR0_RDMO = 0x200U , MCFGR0_RELAX = 0x10000U , MCFGR0_ABORT = 0x20000U , MCFGR1_PRESCALE = 0x7U , MCFGR1_AUTOSTOP = 0x100U , MCFGR1_IGNACK = 0x200U , MCFGR1_TIMECFG = 0x400U , MCFGR1_STOPCFG = 0x800U , MCFGR1_STARTCFG = 0x1000U , MCFGR1_MATCFG = 0x70000U , MCFGR1_PINCFG = 0x7000000U , MCFGR2_BUSIDLE = 0xFFFU , MCFGR2_FILTSCL = 0xF0000U , MCFGR2_FILTSDA = 0xF000000U , MCFGR3_PINLOW = 0xFFF00U , MDMR_MATCH0 = 0xFFU , MDMR_MATCH1 = 0xFF0000U , MCCR0_CLKLO = 0x3FU , MCCR0_CLKHI = 0x3F00U , MCCR0_SETHOLD = 0x3F0000U , MCCR0_DATAVD = 0x3F000000U , MCCR1_CLKLO = 0x3FU , MCCR1_CLKHI = 0x3F00U , MCCR1_SETHOLD = 0x3F0000U , MCCR1_DATAVD = 0x3F000000U , MFCR_TXWATER = 0x3U , MFCR_RXWATER = 0x30000U , MFSR_TXCOUNT = 0x7U , MFSR_RXCOUNT = 0x70000U , MTDR_DATA = 0xFFU , MTDR_CMD = 0x700U , MRDR_DATA = 0xFFU , MRDR_RXEMPTY = 0x4000U , MRDROR_DATA = 0xFFU , MRDROR_RXEMPTY = 0x4000U , SCR_SEN = 0x1U , SCR_RST = 0x2U , SCR_FILTEN = 0x10U , SCR_FILTDZ = 0x20U , SCR_RTF = 0x100U , SCR_RRF = 0x200U , SSR_TDF = 0x1U , SSR_RDF = 0x2U , SSR_AVF = 0x4U , SSR_TAF = 0x8U , SSR_RSF = 0x100U , SSR_SDF = 0x200U , SSR_BEF = 0x400U , SSR_FEF = 0x800U , SSR_AM0F = 0x1000U , SSR_AM1F = 0x2000U , SSR_GCF = 0x4000U , SSR_SARF = 0x8000U , SSR_SBF = 0x1000000U , SSR_BBF = 0x2000000U , SIER_TDIE = 0x1U , SIER_RDIE = 0x2U , SIER_AVIE = 0x4U , SIER_TAIE = 0x8U , SIER_RSIE = 0x100U , SIER_SDIE = 0x200U , SIER_BEIE = 0x400U , SIER_FEIE = 0x800U , SIER_AM0IE = 0x1000U , SIER_AM1IE = 0x2000U , SIER_GCIE = 0x4000U , SIER_SARIE = 0x8000U , SDER_TDDE = 0x1U , SDER_RDDE = 0x2U , SDER_AVDE = 0x4U , SDER_RSDE = 0x100U , SDER_SDDE = 0x200U , SCFGR0_RDREQ = 0x1U , SCFGR0_RDACK = 0x2U , SCFGR1_ADRSTALL = 0x1U , SCFGR1_RXSTALL = 0x2U , SCFGR1_TXDSTALL = 0x4U , SCFGR1_ACKSTALL = 0x8U , SCFGR1_RXNACK = 0x10U , SCFGR1_GCEN = 0x100U , SCFGR1_SAEN = 0x200U , SCFGR1_TXCFG = 0x400U , SCFGR1_RXCFG = 0x800U , SCFGR1_IGNACK = 0x1000U , SCFGR1_HSMEN = 0x2000U , SCFGR1_ADDRCFG = 0x70000U , SCFGR1_RXALL = 0x1000000U , SCFGR1_RSCFG = 0x2000000U , SCFGR1_SDCFG = 0x4000000U , SCFGR2_CLKHOLD = 0xFU , SCFGR2_DATAVD = 0x3F00U , SCFGR2_FILTSCL = 0xF0000U , SCFGR2_FILTSDA = 0xF000000U , SAMR_ADDR0 = 0x7FEU , SAMR_ADDR1 = 0x7FE0000U , SASR_RADDR = 0x7FFU , SASR_ANV = 0x4000U , STAR_TXNACK = 0x1U , STDR_DATA = 0xFFU , SRDR_DATA = 0xFFU , SRDR_RADDR = 0x700U , SRDR_RXEMPTY = 0x4000U , SRDR_SOF = 0x8000U , SRDROR_DATA = 0xFFU , SRDROR_RADDR = 0x700U , SRDROR_RXEMPTY = 0x4000U , SRDROR_SOF = 0x8000U }

enum struct	Shift : unsigned int { VERID_FEATURE = 0U , VERID_MINOR = 16U , VERID_MAJOR = 24U , PARAM_MTXFIFO = 0U , PARAM_MRXFIFO = 8U , MCR_MEN = 0U , MCR_RST = 1U , MCR_DOZEN = 2U , MCR_DBGEN = 3U , MCR_RTF = 8U , MCR_RRF = 9U , MSR_TDF = 0U , MSR_RDF = 1U , MSR_EPF = 8U , MSR_SDF = 9U , MSR_NDF = 10U , MSR_ALF = 11U , MSR_FEF = 12U , MSR_PLTF = 13U , MSR_DMF = 14U , MSR_STF = 15U , MSR_MBF = 24U , MSR_BBF = 25U , MIER_TDIE = 0U , MIER_RDIE = 1U , MIER_EPIE = 8U , MIER_SDIE = 9U , MIER_NDIE = 10U , MIER_ALIE = 11U , MIER_FEIE = 12U , MIER_PLTIE = 13U , MIER_DMIE = 14U , MIER_STIE = 15U , MDER_TDDE = 0U , MDER_RDDE = 1U , MCFGR0_HREN = 0U , MCFGR0_HRPOL = 1U , MCFGR0_HRSEL = 2U , MCFGR0_HRDIR = 3U , MCFGR0_CIRFIFO = 8U , MCFGR0_RDMO = 9U , MCFGR0_RELAX = 16U , MCFGR0_ABORT = 17U , MCFGR1_PRESCALE = 0U , MCFGR1_AUTOSTOP = 8U , MCFGR1_IGNACK = 9U , MCFGR1_TIMECFG = 10U , MCFGR1_STOPCFG = 11U , MCFGR1_STARTCFG = 12U , MCFGR1_MATCFG = 16U , MCFGR1_PINCFG = 24U , MCFGR2_BUSIDLE = 0U , MCFGR2_FILTSCL = 16U , MCFGR2_FILTSDA = 24U , MCFGR3_PINLOW = 8U , MDMR_MATCH0 = 0U , MDMR_MATCH1 = 16U , MCCR0_CLKLO = 0U , MCCR0_CLKHI = 8U , MCCR0_SETHOLD = 16U , MCCR0_DATAVD = 24U , MCCR1_CLKLO = 0U , MCCR1_CLKHI = 8U , MCCR1_SETHOLD = 16U , MCCR1_DATAVD = 24U , MFCR_TXWATER = 0U , MFCR_RXWATER = 16U , MFSR_TXCOUNT = 0U , MFSR_RXCOUNT = 16U , MTDR_DATA = 0U , MTDR_CMD = 8U , MRDR_DATA = 0U , MRDR_RXEMPTY = 14U , MRDROR_DATA = 0U , MRDROR_RXEMPTY = 14U , SCR_SEN = 0U , SCR_RST = 1U , SCR_FILTEN = 4U , SCR_FILTDZ = 5U , SCR_RTF = 8U , SCR_RRF = 9U , SSR_TDF = 0U , SSR_RDF = 1U , SSR_AVF = 2U , SSR_TAF = 3U , SSR_RSF = 8U , SSR_SDF = 9U , SSR_BEF = 10U , SSR_FEF = 11U , SSR_AM0F = 12U , SSR_AM1F = 13U , SSR_GCF = 14U , SSR_SARF = 15U , SSR_SBF = 24U , SSR_BBF = 25U , SIER_TDIE = 0U , SIER_RDIE = 1U , SIER_AVIE = 2U , SIER_TAIE = 3U , SIER_RSIE = 8U , SIER_SDIE = 9U , SIER_BEIE = 10U , SIER_FEIE = 11U , SIER_AM0IE = 12U , SIER_AM1IE = 13U , SIER_GCIE = 14U , SIER_SARIE = 15U , SDER_TDDE = 0U , SDER_RDDE = 1U , SDER_AVDE = 2U , SDER_RSDE = 8U , SDER_SDDE = 9U , SCFGR0_RDREQ = 0U , SCFGR0_RDACK = 1U , SCFGR1_ADRSTALL = 0U , SCFGR1_RXSTALL = 1U , SCFGR1_TXDSTALL = 2U , SCFGR1_ACKSTALL = 3U , SCFGR1_RXNACK = 4U , SCFGR1_GCEN = 8U , SCFGR1_SAEN = 9U , SCFGR1_TXCFG = 10U , SCFGR1_RXCFG = 11U , SCFGR1_IGNACK = 12U , SCFGR1_HSMEN = 13U , SCFGR1_ADDRCFG = 16U , SCFGR1_RXALL = 24U , SCFGR1_RSCFG = 25U , SCFGR1_SDCFG = 26U , SCFGR2_CLKHOLD = 0U , SCFGR2_DATAVD = 8U , SCFGR2_FILTSCL = 16U , SCFGR2_FILTSDA = 24U , SAMR_ADDR0 = 1U , SAMR_ADDR1 = 17U , SASR_RADDR = 0U , SASR_ANV = 14U , STAR_TXNACK = 0U , STDR_DATA = 0U , SRDR_DATA = 0U , SRDR_RADDR = 8U , SRDR_RXEMPTY = 14U , SRDR_SOF = 15U , SRDROR_DATA = 0U , SRDROR_RADDR = 8U , SRDROR_RXEMPTY = 14U , SRDROR_SOF = 15U }

函式
constexpr unsigned int	operator+ (Mask e)

constexpr unsigned int	operator+ (Shift e)

變數
Register &	LPI2C0

詳細描述

SPDX-License-Identifier: MIT

列舉型態說明文件

◆ Mask

enum struct chip::lpi2c::Mask : unsigned int

strong

列舉值
VERID_FEATURE	VERID - FEATURE. Version ID - Feature Specification Number [0b0000000000000010] Controller only, with standard feature set [0b0000000000000011] Controller and target, with standard feature set
VERID_MINOR	VERID - MINOR. Version ID - Minor Version Number
VERID_MAJOR	VERID - MAJOR. Version ID - Major Version Number
PARAM_MTXFIFO	PARAM - MTXFIFO. Parameter - Controller Transmit FIFO Size
PARAM_MRXFIFO	PARAM - MRXFIFO. Parameter - Controller Receive FIFO Size
MCR_MEN	MCR - MEN. Controller Control - Controller Enable [0b0] Disable [0b1] Enable
MCR_RST	MCR - RST. Controller Control - Software Reset [0b0] No effect [0b1] Reset
MCR_DOZEN	MCR - DOZEN. Controller Control - Doze Mode Enable [0b0] Enable [0b1] Disable
MCR_DBGEN	MCR - DBGEN. Controller Control - Debug Enable [0b0] Disable [0b1] Enable
MCR_RTF	MCR - RTF. Controller Control - Reset Transmit FIFO [0b0] No effect [0b1] Reset transmit FIFO
MCR_RRF	MCR - RRF. Controller Control - Reset Receive FIFO [0b0] No effect [0b1] Reset receive FIFO
MSR_TDF	MSR - TDF. Controller Status - Transmit Data Flag [0b0] Transmit data not requested [0b1] Transmit data requested
MSR_RDF	MSR - RDF. Controller Status - Receive Data Flag [0b0] Receive data not ready [0b1] Receive data ready
MSR_EPF	MSR - EPF. Controller Status - End Packet Flag [0b0] No Stop or repeated Start generated [0b1] Stop or repeated Start generated [0b0] No effect [0b1] Clear the flag
MSR_SDF	MSR - SDF. Controller Status - Stop Detect Flag [0b0] No Stop condition generated [0b1] Stop condition generated [0b0] No effect [0b1] Clear the flag
MSR_NDF	MSR - NDF. Controller Status - NACK Detect Flag [0b0] No unexpected NACK detected [0b1] Unexpected NACK detected [0b0] No effect [0b1] Clear the flag
MSR_ALF	MSR - ALF. Controller Status - Arbitration Lost Flag [0b0] Controller did not lose arbitration [0b1] Controller lost arbitration [0b0] No effect [0b1] Clear the flag
MSR_FEF	MSR - FEF. Controller Status - FIFO Error Flag [0b0] No FIFO error [0b1] FIFO error [0b0] No effect [0b1] Clear the flag
MSR_PLTF	MSR - PLTF. Controller Status - Pin Low Timeout Flag [0b0] Pin low timeout did not occur [0b1] Pin low timeout occurred [0b0] No effect [0b1] Clear the flag
MSR_DMF	MSR - DMF. Controller Status - Data Match Flag [0b0] Matching data not received [0b1] Matching data received [0b0] No effect [0b1] Clear the flag
MSR_STF	MSR - STF. Controller Status - Start Flag [0b0] Start condition not detected [0b1] Start condition detected [0b0] No effect [0b1] Clear the flag
MSR_MBF	MSR - MBF. Controller Status - Controller Busy Flag [0b0] Idle [0b1] Busy
MSR_BBF	MSR - BBF. Controller Status - Bus Busy Flag [0b0] Idle [0b1] Busy
MIER_TDIE	MIER - TDIE. Controller Interrupt Enable - Transmit Data Interrupt Enable [0b0] Disable [0b1] Enable
MIER_RDIE	MIER - RDIE. Controller Interrupt Enable - Receive Data Interrupt Enable [0b0] Disable [0b1] Enable
MIER_EPIE	MIER - EPIE. Controller Interrupt Enable - End Packet Interrupt Enable [0b0] Disable [0b1] Enable
MIER_SDIE	MIER - SDIE. Controller Interrupt Enable - Stop Detect Interrupt Enable [0b0] Disable [0b1] Enable
MIER_NDIE	MIER - NDIE. Controller Interrupt Enable - NACK Detect Interrupt Enable [0b0] Disable [0b1] Enable
MIER_ALIE	MIER - ALIE. Controller Interrupt Enable - Arbitration Lost Interrupt Enable [0b0] Disable [0b1] Enable
MIER_FEIE	MIER - FEIE. Controller Interrupt Enable - FIFO Error Interrupt Enable [0b0] Disable [0b1] Enable
MIER_PLTIE	MIER - PLTIE. Controller Interrupt Enable - Pin Low Timeout Interrupt Enable [0b0] Disable [0b1] Enable
MIER_DMIE	MIER - DMIE. Controller Interrupt Enable - Data Match Interrupt Enable [0b0] Disable [0b1] Enable
MIER_STIE	MIER - STIE. Controller Interrupt Enable - Start Interrupt Enable [0b0] Disable [0b1] Enable
MDER_TDDE	MDER - TDDE. Controller DMA Enable - Transmit Data DMA Enable [0b0] Disable [0b1] Enable
MDER_RDDE	MDER - RDDE. Controller DMA Enable - Receive Data DMA Enable [0b0] Disable [0b1] Enable
MCFGR0_HREN	MCFGR0 - HREN. Controller Configuration 0 - Host Request Enable [0b0] Disable [0b1] Enable
MCFGR0_HRPOL	MCFGR0 - HRPOL. Controller Configuration 0 - Host Request Polarity [0b0] Active low [0b1] Active high
MCFGR0_HRSEL	MCFGR0 - HRSEL. Controller Configuration 0 - Host Request Select [0b0] Host request input is pin HREQ [0b1] Host request input is input trigger
MCFGR0_HRDIR	MCFGR0 - HRDIR. Controller Configuration 0 - Host Request Direction [0b0] HREQ pin is input (for LPI2C controller) [0b1] HREQ pin is output (for LPI2C target)
MCFGR0_CIRFIFO	MCFGR0 - CIRFIFO. Controller Configuration 0 - Circular FIFO Enable [0b0] Disable [0b1] Enable
MCFGR0_RDMO	MCFGR0 - RDMO. Controller Configuration 0 - Receive Data Match Only [0b0] Received data is stored in the receive FIFO [0b1] Received data is discarded unless MSR[DMF] is set
MCFGR0_RELAX	MCFGR0 - RELAX. Controller Configuration 0 - Relaxed Mode [0b0] Normal transfer [0b1] Relaxed transfer
MCFGR0_ABORT	MCFGR0 - ABORT. Controller Configuration 0 - Abort Transfer [0b0] Normal transfer [0b1] Abort existing transfer and do not start a new one
MCFGR1_PRESCALE	MCFGR1 - PRESCALE. Controller Configuration 1 - Prescaler [0b000] Divide by 1 [0b001] Divide by 2 [0b010] Divide by 4 [0b011] Divide by 8 [0b100] Divide by 16 [0b101] Divide by 32 [0b110] Divide by 64 [0b111] Divide by 128
MCFGR1_AUTOSTOP	MCFGR1 - AUTOSTOP. Controller Configuration 1 - Automatic Stop Generation [0b0] No effect [0b1] Stop automatically generated
MCFGR1_IGNACK	MCFGR1 - IGNACK. Controller Configuration 1 - Ignore NACK [0b0] No effect [0b1] Treat a received NACK as an ACK
MCFGR1_TIMECFG	MCFGR1 - TIMECFG. Controller Configuration 1 - Timeout Configuration [0b0] SCL [0b1] SCL or SDA
MCFGR1_STOPCFG	MCFGR1 - STOPCFG. Controller Configuration 1 - Stop Configuration [0b0] Any Stop condition [0b1] Last Stop condition
MCFGR1_STARTCFG	MCFGR1 - STARTCFG. Controller Configuration 1 - Start Configuration [0b0] Sets when both I2C bus and LPI2C controller are idle [0b1] Sets when I2C bus is idle
MCFGR1_MATCFG	MCFGR1 - MATCFG. Controller Configuration 1 - Match Configuration [0b000] Match is disabled [0b001] Reserved [0b010] Match is enabled: first data word equals MDMR[MATCH0] OR MDMR[MATCH1] [0b011] Match is enabled: any data word equals MDMR[MATCH0] OR MDMR[MATCH1] [0b100] Match is enabled: (first data word equals MDMR[MATCH0]) AND (second data word equals MDMR[MATCH1) [0b101] Match is enabled: (any data word equals MDMR[MATCH0]) AND (next data word equals MDMR[MATCH1) [0b110] Match is enabled: (first data word AND MDMR[MATCH1]) equals (MDMR[MATCH0] AND MDMR[MATCH1]) [0b111] Match is enabled: (any data word AND MDMR[MATCH1]) equals (MDMR[MATCH0] AND MDMR[MATCH1])
MCFGR1_PINCFG	MCFGR1 - PINCFG. Controller Configuration 1 - Pin Configuration [0b000] Two-pin open drain mode [0b001] Two-pin output only mode (Ultra-Fast mode) [0b010] Two-pin push-pull mode [0b011] Four-pin push-pull mode [0b100] Two-pin open-drain mode with separate LPI2C target [0b101] Two-pin output only mode (Ultra-Fast mode) with separate LPI2C target [0b110] Two-pin push-pull mode with separate LPI2C target [0b111] Four-pin push-pull mode (inverted outputs)
MCFGR2_BUSIDLE	MCFGR2 - BUSIDLE. Controller Configuration 2 - Bus Idle Timeout
MCFGR2_FILTSCL	MCFGR2 - FILTSCL. Controller Configuration 2 - Glitch Filter SCL
MCFGR2_FILTSDA	MCFGR2 - FILTSDA. Controller Configuration 2 - Glitch Filter SDA
MCFGR3_PINLOW	MCFGR3 - PINLOW. Controller Configuration 3 - Pin Low Timeout
MDMR_MATCH0	MDMR - MATCH0. Controller Data Match - Match 0 Value
MDMR_MATCH1	MDMR - MATCH1. Controller Data Match - Match 1 Value
MCCR0_CLKLO	MCCR0 - CLKLO. Controller Clock Configuration 0 - Clock Low Period
MCCR0_CLKHI	MCCR0 - CLKHI. Controller Clock Configuration 0 - Clock High Period
MCCR0_SETHOLD	MCCR0 - SETHOLD. Controller Clock Configuration 0 - Setup Hold Delay
MCCR0_DATAVD	MCCR0 - DATAVD. Controller Clock Configuration 0 - Data Valid Delay
MCCR1_CLKLO	MCCR1 - CLKLO. Controller Clock Configuration 1 - Clock Low Period
MCCR1_CLKHI	MCCR1 - CLKHI. Controller Clock Configuration 1 - Clock High Period
MCCR1_SETHOLD	MCCR1 - SETHOLD. Controller Clock Configuration 1 - Setup Hold Delay
MCCR1_DATAVD	MCCR1 - DATAVD. Controller Clock Configuration 1 - Data Valid Delay
MFCR_TXWATER	MFCR - TXWATER. Controller FIFO Control - Transmit FIFO Watermark
MFCR_RXWATER	MFCR - RXWATER. Controller FIFO Control - Receive FIFO Watermark
MFSR_TXCOUNT	MFSR - TXCOUNT. Controller FIFO Status - Transmit FIFO Count
MFSR_RXCOUNT	MFSR - RXCOUNT. Controller FIFO Status - Receive FIFO Count
MTDR_DATA	MTDR - DATA. Controller Transmit Data - Transmit Data
MTDR_CMD	MTDR - CMD. Controller Transmit Data - Command Data [0b000] Transmit the value in DATA[7:0] [0b001] Receive (DATA[7:0] + 1) bytes [0b010] Generate Stop condition on I2C bus [0b011] Receive and discard (DATA[7:0] + 1) bytes [0b100] Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] [0b101] Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] (this transfer expects a NACK to be returned) [0b110] Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] using HS mode [0b111] Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] using HS mode (this transfer expects a NACK to be returned)
MRDR_DATA	MRDR - DATA. Controller Receive Data - Receive Data
MRDR_RXEMPTY	MRDR - RXEMPTY. Controller Receive Data - Receive Empty [0b0] Not empty [0b1] Empty
MRDROR_DATA	MRDROR - DATA. Controller Receive Data Read Only - Receive Data
MRDROR_RXEMPTY	MRDROR - RXEMPTY. Controller Receive Data Read Only - RX Empty [0b0] Not empty [0b1] Empty
SCR_SEN	SCR - SEN. Target Control - Target Enable [0b0] Disable [0b1] Enable
SCR_RST	SCR - RST. Target Control - Software Reset [0b0] Not reset [0b1] Reset
SCR_FILTEN	SCR - FILTEN. Target Control - Filter Enable [0b0] Disable [0b1] Enable
SCR_FILTDZ	SCR - FILTDZ. Target Control - Filter Doze Enable [0b0] Enable [0b1] Disable
SCR_RTF	SCR - RTF. Target Control - Reset Transmit FIFO [0b0] No effect [0b1] STDR is now empty
SCR_RRF	SCR - RRF. Target Control - Reset Receive FIFO [0b0] No effect [0b1] SRDR is now empty
SSR_TDF	SSR - TDF. Target Status - Transmit Data Flag [0b0] Transmit data not requested [0b1] Transmit data is requested
SSR_RDF	SSR - RDF. Target Status - Receive Data Flag [0b0] Not ready [0b1] Ready
SSR_AVF	SSR - AVF. Target Status - Address Valid Flag [0b0] Not valid [0b1] Valid
SSR_TAF	SSR - TAF. Target Status - Transmit ACK Flag [0b0] Not required [0b1] Required
SSR_RSF	SSR - RSF. Target Status - Repeated Start Flag [0b0] No repeated Start detected [0b1] Repeated Start detected [0b0] No effect [0b1] Clear the flag
SSR_SDF	SSR - SDF. Target Status - Stop Detect Flag [0b0] No Stop detected [0b1] Stop detected [0b0] No effect [0b1] Clear the flag
SSR_BEF	SSR - BEF. Target Status - Bit Error Flag [0b0] No bit error occurred [0b1] Bit error occurred [0b0] No effect [0b1] Clear the flag
SSR_FEF	SSR - FEF. Target Status - FIFO Error Flag [0b0] No FIFO error [0b1] FIFO error [0b0] No effect [0b1] Clear the flag
SSR_AM0F	SSR - AM0F. Target Status - Address Match 0 Flag [0b0] ADDR0 matching address not received [0b1] ADDR0 matching address received
SSR_AM1F	SSR - AM1F. Target Status - Address Match 1 Flag [0b0] Matching address not received [0b1] Matching address received
SSR_GCF	SSR - GCF. Target Status - General Call Flag [0b0] General call address disabled or not detected [0b1] General call address detected
SSR_SARF	SSR - SARF. Target Status - SMBus Alert Response Flag [0b0] Disabled or not detected [0b1] Enabled and detected
SSR_SBF	SSR - SBF. Target Status - Target Busy Flag [0b0] Idle [0b1] Busy
SSR_BBF	SSR - BBF. Target Status - Bus Busy Flag [0b0] Idle [0b1] Busy
SIER_TDIE	SIER - TDIE. Target Interrupt Enable - Transmit Data Interrupt Enable [0b0] Disable [0b1] Enable
SIER_RDIE	SIER - RDIE. Target Interrupt Enable - Receive Data Interrupt Enable [0b0] Disable [0b1] Enable
SIER_AVIE	SIER - AVIE. Target Interrupt Enable - Address Valid Interrupt Enable [0b0] Disable [0b1] Enable
SIER_TAIE	SIER - TAIE. Target Interrupt Enable - Transmit ACK Interrupt Enable [0b0] Disable [0b1] Enable
SIER_RSIE	SIER - RSIE. Target Interrupt Enable - Repeated Start Interrupt Enable [0b0] Disable [0b1] Enable
SIER_SDIE	SIER - SDIE. Target Interrupt Enable - Stop Detect Interrupt Enable [0b0] Disable [0b1] Enable
SIER_BEIE	SIER - BEIE. Target Interrupt Enable - Bit Error Interrupt Enable [0b0] Disable [0b1] Enable
SIER_FEIE	SIER - FEIE. Target Interrupt Enable - FIFO Error Interrupt Enable [0b0] Disable [0b1] Enable
SIER_AM0IE	SIER - AM0IE. Target Interrupt Enable - Address Match 0 Interrupt Enable [0b0] Disable [0b1] Enable
SIER_AM1IE	SIER - AM1IE. Target Interrupt Enable - Address Match 1 Interrupt Enable [0b0] Disable [0b1] Enable
SIER_GCIE	SIER - GCIE. Target Interrupt Enable - General Call Interrupt Enable [0b0] Disabled [0b1] Enabled
SIER_SARIE	SIER - SARIE. Target Interrupt Enable - SMBus Alert Response Interrupt Enable [0b0] Disable [0b1] Enable
SDER_TDDE	SDER - TDDE. Target DMA Enable - Transmit Data DMA Enable [0b0] Disable [0b1] Enable
SDER_RDDE	SDER - RDDE. Target DMA Enable - Receive Data DMA Enable [0b0] Disable DMA request [0b1] Enable DMA request
SDER_AVDE	SDER - AVDE. Target DMA Enable - Address Valid DMA Enable [0b0] Disable [0b1] Enable
SDER_RSDE	SDER - RSDE. Target DMA Enable - Repeated Start DMA Enable [0b0] Disable [0b1] Enable
SDER_SDDE	SDER - SDDE. Target DMA Enable - Stop Detect DMA Enable [0b0] Disable [0b1] Enable
SCFGR0_RDREQ	SCFGR0 - RDREQ. Target Configuration 0 - Read Request [0b0] Disable [0b1] Enable
SCFGR0_RDACK	SCFGR0 - RDACK. Target Configuration 0 - Read Acknowledge Flag [0b0] Read Request not acknowledged [0b1] Read Request acknowledged
SCFGR1_ADRSTALL	SCFGR1 - ADRSTALL. Target Configuration 1 - Address SCL Stall [0b0] Disable [0b1] Enable
SCFGR1_RXSTALL	SCFGR1 - RXSTALL. Target Configuration 1 - RX SCL Stall [0b0] Disable [0b1] Enable
SCFGR1_TXDSTALL	SCFGR1 - TXDSTALL. Target Configuration 1 - Transmit Data SCL Stall [0b0] Disable [0b1] Enable
SCFGR1_ACKSTALL	SCFGR1 - ACKSTALL. Target Configuration 1 - ACK SCL Stall [0b0] Disable [0b1] Enable
SCFGR1_RXNACK	SCFGR1 - RXNACK. Target Configuration 1 - Receive NACK [0b0] ACK or NACK always determined by STAR[TXNACK] [0b1] NACK always generated on address overrun or receive data overrun, otherwise ACK or NACK is determined by STAR[TXNACK]
SCFGR1_GCEN	SCFGR1 - GCEN. Target Configuration 1 - General Call Enable [0b0] Disable [0b1] Enable
SCFGR1_SAEN	SCFGR1 - SAEN. Target Configuration 1 - SMBus Alert Enable [0b0] Disable [0b1] Enable
SCFGR1_TXCFG	SCFGR1 - TXCFG. Target Configuration 1 - Transmit Flag Configuration [0b0] MSR[TDF] is set only during a target-transmit transfer when STDR is empty [0b1] MSR[TDF] is set whenever STDR is empty
SCFGR1_RXCFG	SCFGR1 - RXCFG. Target Configuration 1 - Receive Data Configuration [0b0] Return received data, clear MSR[RDF] [0b1] Return SASR and clear SSR[AVF] when SSR[AVF] is set, return received data and clear MSR[RDF] when SSR[AFV] is not set
SCFGR1_IGNACK	SCFGR1 - IGNACK. Target Configuration 1 - Ignore NACK [0b0] End transfer on NACK [0b1] Do not end transfer on NACK
SCFGR1_HSMEN	SCFGR1 - HSMEN. Target Configuration 1 - HS Mode Enable [0b0] Disable [0b1] Enable
SCFGR1_ADDRCFG	SCFGR1 - ADDRCFG. Target Configuration 1 - Address Configuration [0b000] Address match 0 (7-bit) [0b001] Address match 0 (10-bit) [0b010] Address match 0 (7-bit) or address match 1 (7-bit) [0b011] Address match 0 (10-bit) or address match 1 (10-bit) [0b100] Address match 0 (7-bit) or address match 1 (10-bit) [0b101] Address match 0 (10-bit) or address match 1 (7-bit) [0b110] From address match 0 (7-bit) to address match 1 (7-bit) [0b111] From address match 0 (10-bit) to address match 1 (10-bit)
SCFGR1_RXALL	SCFGR1 - RXALL. Target Configuration 1 - Receive All [0b0] Disable [0b1] Enable
SCFGR1_RSCFG	SCFGR1 - RSCFG. Target Configuration 1 - Repeated Start Configuration [0b0] Any repeated Start condition following an address match [0b1] Any repeated Start condition
SCFGR1_SDCFG	SCFGR1 - SDCFG. Target Configuration 1 - Stop Detect Configuration [0b0] Any Stop condition following an address match [0b1] Any Stop condition
SCFGR2_CLKHOLD	SCFGR2 - CLKHOLD. Target Configuration 2 - Clock Hold Time
SCFGR2_DATAVD	SCFGR2 - DATAVD. Target Configuration 2 - Data Valid Delay
SCFGR2_FILTSCL	SCFGR2 - FILTSCL. Target Configuration 2 - Glitch Filter SCL
SCFGR2_FILTSDA	SCFGR2 - FILTSDA. Target Configuration 2 - Glitch Filter SDA
SAMR_ADDR0	SAMR - ADDR0. Target Address Match - Address 0 Value
SAMR_ADDR1	SAMR - ADDR1. Target Address Match - Address 1 Value
SASR_RADDR	SASR -RADDR. Target Address Status - Received Address
SASR_ANV	SASR -ANV. Target Address Status - Address Not Valid [0b0] Valid [0b1] Not valid
STAR_TXNACK	STAR - TXNACK. Target Transmit ACK - Transmit NACK [0b0] Transmit ACK [0b1] Transmit NACK
STDR_DATA	STDR - DATA. Target Transmit Data - Transmit Data
SRDR_DATA	SRDR - DATA. Target Receive Data - Received Data
SRDR_RADDR	SRDR - RADDR. Target Receive Data - Received Address
SRDR_RXEMPTY	SRDR - RXEMPTY. Target Receive Data - Receive Empty [0b0] Not empty [0b1] Empty
SRDR_SOF	SRDR - SOF. Target Receive Data - Start of Frame [0b0] Not first [0b1] First
SRDROR_DATA	SRDROR - DATA. Target Receive Data Read Only - Receive Data
SRDROR_RADDR	SRDROR - RADDR. Target Receive Data Read Only - Received Address
SRDROR_RXEMPTY	SRDROR - RXEMPTY. Target Receive Data Read Only - Receive Empty [0b0] Not empty [0b1] Empty
SRDROR_SOF	SRDROR - SOF. Target Receive Data Read Only - Start of Frame [0b0] Not the first [0b1] First

◆ Shift

enum struct chip::lpi2c::Shift : unsigned int

strong

列舉值
VERID_FEATURE	VERID - FEATURE. Version ID - Feature Specification Number [0b0000000000000010] Controller only, with standard feature set [0b0000000000000011] Controller and target, with standard feature set
VERID_MINOR	VERID - MINOR. Version ID - Minor Version Number
VERID_MAJOR	VERID - MAJOR. Version ID - Major Version Number
PARAM_MTXFIFO	PARAM - MTXFIFO. Parameter - Controller Transmit FIFO Size
PARAM_MRXFIFO	PARAM - MRXFIFO. Parameter - Controller Receive FIFO Size
MCR_MEN	MCR - MEN. Controller Control - Controller Enable [0b0] Disable [0b1] Enable
MCR_RST	MCR - RST. Controller Control - Software Reset [0b0] No effect [0b1] Reset
MCR_DOZEN	MCR - DOZEN. Controller Control - Doze Mode Enable [0b0] Enable [0b1] Disable
MCR_DBGEN	MCR - DBGEN. Controller Control - Debug Enable [0b0] Disable [0b1] Enable
MCR_RTF	MCR - RTF. Controller Control - Reset Transmit FIFO [0b0] No effect [0b1] Reset transmit FIFO
MCR_RRF	MCR - RRF. Controller Control - Reset Receive FIFO [0b0] No effect [0b1] Reset receive FIFO
MSR_TDF	MSR - TDF. Controller Status - Transmit Data Flag [0b0] Transmit data not requested [0b1] Transmit data requested
MSR_RDF	MSR - RDF. Controller Status - Receive Data Flag [0b0] Receive data not ready [0b1] Receive data ready
MSR_EPF	MSR - EPF. Controller Status - End Packet Flag [0b0] No Stop or repeated Start generated [0b1] Stop or repeated Start generated [0b0] No effect [0b1] Clear the flag
MSR_SDF	MSR - SDF. Controller Status - Stop Detect Flag [0b0] No Stop condition generated [0b1] Stop condition generated [0b0] No effect [0b1] Clear the flag
MSR_NDF	MSR - NDF. Controller Status - NACK Detect Flag [0b0] No unexpected NACK detected [0b1] Unexpected NACK detected [0b0] No effect [0b1] Clear the flag
MSR_ALF	MSR - ALF. Controller Status - Arbitration Lost Flag [0b0] Controller did not lose arbitration [0b1] Controller lost arbitration [0b0] No effect [0b1] Clear the flag
MSR_FEF	MSR - FEF. Controller Status - FIFO Error Flag [0b0] No FIFO error [0b1] FIFO error [0b0] No effect [0b1] Clear the flag
MSR_PLTF	MSR - PLTF. Controller Status - Pin Low Timeout Flag [0b0] Pin low timeout did not occur [0b1] Pin low timeout occurred [0b0] No effect [0b1] Clear the flag
MSR_DMF	MSR - DMF. Controller Status - Data Match Flag [0b0] Matching data not received [0b1] Matching data received [0b0] No effect [0b1] Clear the flag
MSR_STF	MSR - STF. Controller Status - Start Flag [0b0] Start condition not detected [0b1] Start condition detected [0b0] No effect [0b1] Clear the flag
MSR_MBF	MSR - MBF. Controller Status - Controller Busy Flag [0b0] Idle [0b1] Busy
MSR_BBF	MSR - BBF. Controller Status - Bus Busy Flag [0b0] Idle [0b1] Busy
MIER_TDIE	MIER - TDIE. Controller Interrupt Enable - Transmit Data Interrupt Enable [0b0] Disable [0b1] Enable
MIER_RDIE	MIER - RDIE. Controller Interrupt Enable - Receive Data Interrupt Enable [0b0] Disable [0b1] Enable
MIER_EPIE	MIER - EPIE. Controller Interrupt Enable - End Packet Interrupt Enable [0b0] Disable [0b1] Enable
MIER_SDIE	MIER - SDIE. Controller Interrupt Enable - Stop Detect Interrupt Enable [0b0] Disable [0b1] Enable
MIER_NDIE	MIER - NDIE. Controller Interrupt Enable - NACK Detect Interrupt Enable [0b0] Disable [0b1] Enable
MIER_ALIE	MIER - ALIE. Controller Interrupt Enable - Arbitration Lost Interrupt Enable [0b0] Disable [0b1] Enable
MIER_FEIE	MIER - FEIE. Controller Interrupt Enable - FIFO Error Interrupt Enable [0b0] Disable [0b1] Enable
MIER_PLTIE	MIER - PLTIE. Controller Interrupt Enable - Pin Low Timeout Interrupt Enable [0b0] Disable [0b1] Enable
MIER_DMIE	MIER - DMIE. Controller Interrupt Enable - Data Match Interrupt Enable [0b0] Disable [0b1] Enable
MIER_STIE	MIER - STIE. Controller Interrupt Enable - Start Interrupt Enable [0b0] Disable [0b1] Enable
MDER_TDDE	MDER - TDDE. Controller DMA Enable - Transmit Data DMA Enable [0b0] Disable [0b1] Enable
MDER_RDDE	MDER - RDDE. Controller DMA Enable - Receive Data DMA Enable [0b0] Disable [0b1] Enable
MCFGR0_HREN	MCFGR0 - HREN. Controller Configuration 0 - Host Request Enable [0b0] Disable [0b1] Enable
MCFGR0_HRPOL	MCFGR0 - HRPOL. Controller Configuration 0 - Host Request Polarity [0b0] Active low [0b1] Active high
MCFGR0_HRSEL	MCFGR0 - HRSEL. Controller Configuration 0 - Host Request Select [0b0] Host request input is pin HREQ [0b1] Host request input is input trigger
MCFGR0_HRDIR	MCFGR0 - HRDIR. Controller Configuration 0 - Host Request Direction [0b0] HREQ pin is input (for LPI2C controller) [0b1] HREQ pin is output (for LPI2C target)
MCFGR0_CIRFIFO	MCFGR0 - CIRFIFO. Controller Configuration 0 - Circular FIFO Enable [0b0] Disable [0b1] Enable
MCFGR0_RDMO	MCFGR0 - RDMO. Controller Configuration 0 - Receive Data Match Only [0b0] Received data is stored in the receive FIFO [0b1] Received data is discarded unless MSR[DMF] is set
MCFGR0_RELAX	MCFGR0 - RELAX. Controller Configuration 0 - Relaxed Mode [0b0] Normal transfer [0b1] Relaxed transfer
MCFGR0_ABORT	MCFGR0 - ABORT. Controller Configuration 0 - Abort Transfer [0b0] Normal transfer [0b1] Abort existing transfer and do not start a new one
MCFGR1_PRESCALE	MCFGR1 - PRESCALE. Controller Configuration 1 - Prescaler [0b000] Divide by 1 [0b001] Divide by 2 [0b010] Divide by 4 [0b011] Divide by 8 [0b100] Divide by 16 [0b101] Divide by 32 [0b110] Divide by 64 [0b111] Divide by 128
MCFGR1_AUTOSTOP	MCFGR1 - AUTOSTOP. Controller Configuration 1 - Automatic Stop Generation [0b0] No effect [0b1] Stop automatically generated
MCFGR1_IGNACK	MCFGR1 - IGNACK. Controller Configuration 1 - Ignore NACK [0b0] No effect [0b1] Treat a received NACK as an ACK
MCFGR1_TIMECFG	MCFGR1 - TIMECFG. Controller Configuration 1 - Timeout Configuration [0b0] SCL [0b1] SCL or SDA
MCFGR1_STOPCFG	MCFGR1 - STOPCFG. Controller Configuration 1 - Stop Configuration [0b0] Any Stop condition [0b1] Last Stop condition
MCFGR1_STARTCFG	MCFGR1 - STARTCFG. Controller Configuration 1 - Start Configuration [0b0] Sets when both I2C bus and LPI2C controller are idle [0b1] Sets when I2C bus is idle
MCFGR1_MATCFG	MCFGR1 - MATCFG. Controller Configuration 1 - Match Configuration [0b000] Match is disabled [0b001] Reserved [0b010] Match is enabled: first data word equals MDMR[MATCH0] OR MDMR[MATCH1] [0b011] Match is enabled: any data word equals MDMR[MATCH0] OR MDMR[MATCH1] [0b100] Match is enabled: (first data word equals MDMR[MATCH0]) AND (second data word equals MDMR[MATCH1) [0b101] Match is enabled: (any data word equals MDMR[MATCH0]) AND (next data word equals MDMR[MATCH1) [0b110] Match is enabled: (first data word AND MDMR[MATCH1]) equals (MDMR[MATCH0] AND MDMR[MATCH1]) [0b111] Match is enabled: (any data word AND MDMR[MATCH1]) equals (MDMR[MATCH0] AND MDMR[MATCH1])
MCFGR1_PINCFG	MCFGR1 - PINCFG. Controller Configuration 1 - Pin Configuration [0b000] Two-pin open drain mode [0b001] Two-pin output only mode (Ultra-Fast mode) [0b010] Two-pin push-pull mode [0b011] Four-pin push-pull mode [0b100] Two-pin open-drain mode with separate LPI2C target [0b101] Two-pin output only mode (Ultra-Fast mode) with separate LPI2C target [0b110] Two-pin push-pull mode with separate LPI2C target [0b111] Four-pin push-pull mode (inverted outputs)
MCFGR2_BUSIDLE	MCFGR2 - BUSIDLE. Controller Configuration 2 - Bus Idle Timeout
MCFGR2_FILTSCL	MCFGR2 - FILTSCL. Controller Configuration 2 - Glitch Filter SCL
MCFGR2_FILTSDA	MCFGR2 - FILTSDA. Controller Configuration 2 - Glitch Filter SDA
MCFGR3_PINLOW	MCFGR3 - PINLOW. Controller Configuration 3 - Pin Low Timeout
MDMR_MATCH0	MDMR - MATCH0. Controller Data Match - Match 0 Value
MDMR_MATCH1	MDMR - MATCH1. Controller Data Match - Match 1 Value
MCCR0_CLKLO	MCCR0 - CLKLO. Controller Clock Configuration 0 - Clock Low Period
MCCR0_CLKHI	MCCR0 - CLKHI. Controller Clock Configuration 0 - Clock High Period
MCCR0_SETHOLD	MCCR0 - SETHOLD. Controller Clock Configuration 0 - Setup Hold Delay
MCCR0_DATAVD	MCCR0 - DATAVD. Controller Clock Configuration 0 - Data Valid Delay
MCCR1_CLKLO	MCCR1 - CLKLO. Controller Clock Configuration 1 - Clock Low Period
MCCR1_CLKHI	MCCR1 - CLKHI. Controller Clock Configuration 1 - Clock High Period
MCCR1_SETHOLD	MCCR1 - SETHOLD. Controller Clock Configuration 1 - Setup Hold Delay
MCCR1_DATAVD	MCCR1 - DATAVD. Controller Clock Configuration 1 - Data Valid Delay
MFCR_TXWATER	MFCR - TXWATER. Controller FIFO Control - Transmit FIFO Watermark
MFCR_RXWATER	MFCR - RXWATER. Controller FIFO Control - Receive FIFO Watermark
MFSR_TXCOUNT	MFSR - TXCOUNT. Controller FIFO Status - Transmit FIFO Count
MFSR_RXCOUNT	MFSR - RXCOUNT. Controller FIFO Status - Receive FIFO Count
MTDR_DATA	MTDR - DATA. Controller Transmit Data - Transmit Data
MTDR_CMD	MTDR - CMD. Controller Transmit Data - Command Data [0b000] Transmit the value in DATA[7:0] [0b001] Receive (DATA[7:0] + 1) bytes [0b010] Generate Stop condition on I2C bus [0b011] Receive and discard (DATA[7:0] + 1) bytes [0b100] Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] [0b101] Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] (this transfer expects a NACK to be returned) [0b110] Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] using HS mode [0b111] Generate (repeated) Start on the I2C bus and transmit the address in DATA[7:0] using HS mode (this transfer expects a NACK to be returned)
MRDR_DATA	MRDR - DATA. Controller Receive Data - Receive Data
MRDR_RXEMPTY	MRDR - RXEMPTY. Controller Receive Data - Receive Empty [0b0] Not empty [0b1] Empty
MRDROR_DATA	MRDROR - DATA. Controller Receive Data Read Only - Receive Data
MRDROR_RXEMPTY	MRDROR - RXEMPTY. Controller Receive Data Read Only - RX Empty [0b0] Not empty [0b1] Empty
SCR_SEN	SCR - SEN. Target Control - Target Enable [0b0] Disable [0b1] Enable
SCR_RST	SCR - RST. Target Control - Software Reset [0b0] Not reset [0b1] Reset
SCR_FILTEN	SCR - FILTEN. Target Control - Filter Enable [0b0] Disable [0b1] Enable
SCR_FILTDZ	SCR - FILTDZ. Target Control - Filter Doze Enable [0b0] Enable [0b1] Disable
SCR_RTF	SCR - RTF. Target Control - Reset Transmit FIFO [0b0] No effect [0b1] STDR is now empty
SCR_RRF	SCR - RRF. Target Control - Reset Receive FIFO [0b0] No effect [0b1] SRDR is now empty
SSR_TDF	SSR - TDF. Target Status - Transmit Data Flag [0b0] Transmit data not requested [0b1] Transmit data is requested
SSR_RDF	SSR - RDF. Target Status - Receive Data Flag [0b0] Not ready [0b1] Ready
SSR_AVF	SSR - AVF. Target Status - Address Valid Flag [0b0] Not valid [0b1] Valid
SSR_TAF	SSR - TAF. Target Status - Transmit ACK Flag [0b0] Not required [0b1] Required
SSR_RSF	SSR - RSF. Target Status - Repeated Start Flag [0b0] No repeated Start detected [0b1] Repeated Start detected [0b0] No effect [0b1] Clear the flag
SSR_SDF	SSR - SDF. Target Status - Stop Detect Flag [0b0] No Stop detected [0b1] Stop detected [0b0] No effect [0b1] Clear the flag
SSR_BEF	SSR - BEF. Target Status - Bit Error Flag [0b0] No bit error occurred [0b1] Bit error occurred [0b0] No effect [0b1] Clear the flag
SSR_FEF	SSR - FEF. Target Status - FIFO Error Flag [0b0] No FIFO error [0b1] FIFO error [0b0] No effect [0b1] Clear the flag
SSR_AM0F	SSR - AM0F. Target Status - Address Match 0 Flag [0b0] ADDR0 matching address not received [0b1] ADDR0 matching address received
SSR_AM1F	SSR - AM1F. Target Status - Address Match 1 Flag [0b0] Matching address not received [0b1] Matching address received
SSR_GCF	SSR - GCF. Target Status - General Call Flag [0b0] General call address disabled or not detected [0b1] General call address detected
SSR_SARF	SSR - SARF. Target Status - SMBus Alert Response Flag [0b0] Disabled or not detected [0b1] Enabled and detected
SSR_SBF	SSR - SBF. Target Status - Target Busy Flag [0b0] Idle [0b1] Busy
SSR_BBF	SSR - BBF. Target Status - Bus Busy Flag [0b0] Idle [0b1] Busy
SIER_TDIE	SIER - TDIE. Target Interrupt Enable - Transmit Data Interrupt Enable [0b0] Disable [0b1] Enable
SIER_RDIE	SIER - RDIE. Target Interrupt Enable - Receive Data Interrupt Enable [0b0] Disable [0b1] Enable
SIER_AVIE	SIER - AVIE. Target Interrupt Enable - Address Valid Interrupt Enable [0b0] Disable [0b1] Enable
SIER_TAIE	SIER - TAIE. Target Interrupt Enable - Transmit ACK Interrupt Enable [0b0] Disable [0b1] Enable
SIER_RSIE	SIER - RSIE. Target Interrupt Enable - Repeated Start Interrupt Enable [0b0] Disable [0b1] Enable
SIER_SDIE	SIER - SDIE. Target Interrupt Enable - Stop Detect Interrupt Enable [0b0] Disable [0b1] Enable
SIER_BEIE	SIER - BEIE. Target Interrupt Enable - Bit Error Interrupt Enable [0b0] Disable [0b1] Enable
SIER_FEIE	SIER - FEIE. Target Interrupt Enable - FIFO Error Interrupt Enable [0b0] Disable [0b1] Enable
SIER_AM0IE	SIER - AM0IE. Target Interrupt Enable - Address Match 0 Interrupt Enable [0b0] Disable [0b1] Enable
SIER_AM1IE	SIER - AM1IE. Target Interrupt Enable - Address Match 1 Interrupt Enable [0b0] Disable [0b1] Enable
SIER_GCIE	SIER - GCIE. Target Interrupt Enable - General Call Interrupt Enable [0b0] Disabled [0b1] Enabled
SIER_SARIE	SIER - SARIE. Target Interrupt Enable - SMBus Alert Response Interrupt Enable [0b0] Disable [0b1] Enable
SDER_TDDE	SDER - TDDE. Target DMA Enable - Transmit Data DMA Enable [0b0] Disable [0b1] Enable
SDER_RDDE	SDER - RDDE. Target DMA Enable - Receive Data DMA Enable [0b0] Disable DMA request [0b1] Enable DMA request
SDER_AVDE	SDER - AVDE. Target DMA Enable - Address Valid DMA Enable [0b0] Disable [0b1] Enable
SDER_RSDE	SDER - RSDE. Target DMA Enable - Repeated Start DMA Enable [0b0] Disable [0b1] Enable
SDER_SDDE	SDER - SDDE. Target DMA Enable - Stop Detect DMA Enable [0b0] Disable [0b1] Enable
SCFGR0_RDREQ	SCFGR0 - RDREQ. Target Configuration 0 - Read Request [0b0] Disable [0b1] Enable
SCFGR0_RDACK	SCFGR0 - RDACK. Target Configuration 0 - Read Acknowledge Flag [0b0] Read Request not acknowledged [0b1] Read Request acknowledged
SCFGR1_ADRSTALL	SCFGR1 - ADRSTALL. Target Configuration 1 - Address SCL Stall [0b0] Disable [0b1] Enable
SCFGR1_RXSTALL	SCFGR1 - RXSTALL. Target Configuration 1 - RX SCL Stall [0b0] Disable [0b1] Enable
SCFGR1_TXDSTALL	SCFGR1 - TXDSTALL. Target Configuration 1 - Transmit Data SCL Stall [0b0] Disable [0b1] Enable
SCFGR1_ACKSTALL	SCFGR1 - ACKSTALL. Target Configuration 1 - ACK SCL Stall [0b0] Disable [0b1] Enable
SCFGR1_RXNACK	SCFGR1 - RXNACK. Target Configuration 1 - Receive NACK [0b0] ACK or NACK always determined by STAR[TXNACK] [0b1] NACK always generated on address overrun or receive data overrun, otherwise ACK or NACK is determined by STAR[TXNACK]
SCFGR1_GCEN	SCFGR1 - GCEN. Target Configuration 1 - General Call Enable [0b0] Disable [0b1] Enable
SCFGR1_SAEN	SCFGR1 - SAEN. Target Configuration 1 - SMBus Alert Enable [0b0] Disable [0b1] Enable
SCFGR1_TXCFG	SCFGR1 - TXCFG. Target Configuration 1 - Transmit Flag Configuration [0b0] MSR[TDF] is set only during a target-transmit transfer when STDR is empty [0b1] MSR[TDF] is set whenever STDR is empty
SCFGR1_RXCFG	SCFGR1 - RXCFG. Target Configuration 1 - Receive Data Configuration [0b0] Return received data, clear MSR[RDF] [0b1] Return SASR and clear SSR[AVF] when SSR[AVF] is set, return received data and clear MSR[RDF] when SSR[AFV] is not set
SCFGR1_IGNACK	SCFGR1 - IGNACK. Target Configuration 1 - Ignore NACK [0b0] End transfer on NACK [0b1] Do not end transfer on NACK
SCFGR1_HSMEN	SCFGR1 - HSMEN. Target Configuration 1 - HS Mode Enable [0b0] Disable [0b1] Enable
SCFGR1_ADDRCFG	SCFGR1 - ADDRCFG. Target Configuration 1 - Address Configuration [0b000] Address match 0 (7-bit) [0b001] Address match 0 (10-bit) [0b010] Address match 0 (7-bit) or address match 1 (7-bit) [0b011] Address match 0 (10-bit) or address match 1 (10-bit) [0b100] Address match 0 (7-bit) or address match 1 (10-bit) [0b101] Address match 0 (10-bit) or address match 1 (7-bit) [0b110] From address match 0 (7-bit) to address match 1 (7-bit) [0b111] From address match 0 (10-bit) to address match 1 (10-bit)
SCFGR1_RXALL	SCFGR1 - RXALL. Target Configuration 1 - Receive All [0b0] Disable [0b1] Enable
SCFGR1_RSCFG	SCFGR1 - RSCFG. Target Configuration 1 - Repeated Start Configuration [0b0] Any repeated Start condition following an address match [0b1] Any repeated Start condition
SCFGR1_SDCFG	SCFGR1 - SDCFG. Target Configuration 1 - Stop Detect Configuration [0b0] Any Stop condition following an address match [0b1] Any Stop condition
SCFGR2_CLKHOLD	SCFGR2 - CLKHOLD. Target Configuration 2 - Clock Hold Time
SCFGR2_DATAVD	SCFGR2 - DATAVD. Target Configuration 2 - Data Valid Delay
SCFGR2_FILTSCL	SCFGR2 - FILTSCL. Target Configuration 2 - Glitch Filter SCL
SCFGR2_FILTSDA	SCFGR2 - FILTSDA. Target Configuration 2 - Glitch Filter SDA
SAMR_ADDR0	SAMR - ADDR0. Target Address Match - Address 0 Value
SAMR_ADDR1	SAMR - ADDR1. Target Address Match - Address 1 Value
SASR_RADDR	SASR -RADDR. Target Address Status - Received Address
SASR_ANV	SASR -ANV. Target Address Status - Address Not Valid [0b0] Valid [0b1] Not valid
STAR_TXNACK	STAR - TXNACK. Target Transmit ACK - Transmit NACK [0b0] Transmit ACK [0b1] Transmit NACK
STDR_DATA	STDR - DATA. Target Transmit Data - Transmit Data
SRDR_DATA	SRDR - DATA. Target Receive Data - Received Data
SRDR_RADDR	SRDR - RADDR. Target Receive Data - Received Address
SRDR_RXEMPTY	SRDR - RXEMPTY. Target Receive Data - Receive Empty [0b0] Not empty [0b1] Empty
SRDR_SOF	SRDR - SOF. Target Receive Data - Start of Frame [0b0] Not first [0b1] First
SRDROR_DATA	SRDROR - DATA. Target Receive Data Read Only - Receive Data
SRDROR_RADDR	SRDROR - RADDR. Target Receive Data Read Only - Received Address
SRDROR_RXEMPTY	SRDROR - RXEMPTY. Target Receive Data Read Only - Receive Empty [0b0] Not empty [0b1] Empty
SRDROR_SOF	SRDROR - SOF. Target Receive Data Read Only - Start of Frame [0b0] Not the first [0b1] First

複合項目

列舉型態

函式

變數

詳細描述

列舉型態說明文件

◆ Mask

◆ Shift