MCXA153 SYSCON (System Configuration Controller) Register Structure (SYSCON寄存器結構) 更多...

#include <Register.h>

公開屬性
uint8	reserved0 [512]
	Reserved space (保留空間)

union {

__IO uint32 remap
	REMAP[0x200] <RW> 更多...

struct {

__IO uint32 cpu0_sbus: 2
	RAMX0[0-1] <RW> 更多...

__IO uint32 dma0: 2
	RAMX0[2-3] <RW> 更多...

__IO uint32 usb0: 2
	RAMX0[4-5] <RW> 更多...

__I uint32 reserved0: 25
	Reserved[6-30]. 更多...

__IO uint32 lock: 1
	LOCK[31] <RW> 更多...

} remap_bit
	REMAP[0x200] <RW> 更多...

};

uint8	reserved1 [12]
	Reserved space (保留空間)

__IO uint32	ahbmatprio
	AHB Matrix Priority Control Register (AHB矩陣優先權控制寄存器)

uint8	reserved2 [40]
	Reserved space (保留空間)

__IO uint32	cpu0nstckcal
	Non-Secure CPU0 System Tick Calibration Register (非安全CPU0系統滴答校準寄存器)

uint8	reserved3 [8]
	Reserved space (保留空間)

__IO uint32	nmisrc
	NMI Source Select Register (NMI源選擇寄存器)

uint8	reserved4 [300]
	Reserved space (保留空間)

__IO uint32	slowclkdiv
	SLOW_CLK Clock Divider Register (慢速時鐘分頻寄存器)

uint8	reserved5 [4]
	Reserved space (保留空間)

__IO uint32	ahbclkdiv
	System Clock Divider Register (系統時鐘分頻寄存器)

uint8	reserved6 [120]
	Reserved space (保留空間)

union {

__IO uint32 clkunlock
	CLKUNLOCK[0x3FC] <RW> 更多...

struct {

__IO uint32 unlock: 1
	UNLOCK[0] <RW> 更多...

__I uint32 reserved: 31
	—[1-31] <RESV> 更多...

} clkunlock_bit
	CLKUNLOCK[0x3FC] <RW> 更多...

};

__IO uint32	nvm_ctrl
	NVM (Non-Volatile Memory) Control Register (非揮發性記憶體控制寄存器)

uint32	romcr
	ROM Wait State Register (ROM等待狀態寄存器)

uint8	reserved7 [1028]
	Reserved space (保留空間)

__I uint32	cpustat
	CPU Status Register (CPU狀態寄存器)

uint8	reserved8 [20]
	Reserved space (保留空間)

union {

__IO uint32 lpcac_ctrl
	LPCAC Control, offset: 0x824.

struct {

__IO uint32 dis_lpcac: 1
	DIS_LPCAC[0] <RW> 更多...

__IO uint32 clr_lpcac: 1
	CLR_LPCAC[1] <RW> 更多...

__IO uint32 frc_no_alloc: 1
	FRC_NO_ALLOC[2] <RW> 更多...

__I uint32 reserved0: 1
	Reserved[3] <RESD>

__IO uint32 dis_lpcac_wtbf: 1
	DIS_LPCAC_WTBF[4] <RW> 更多...

__IO uint32 lim_lpcac_wtbf: 1
	LIM_LPCAC_WTBF[5] <RW> 更多...

__I uint32 reserved1: 1
	Reserved[6] <RESV>

__IO uint32 lpcac_xom: 1
	LPCAC_XOM[7] <RW> 更多...

__IO uint32 lpcac_mem_req: 1
	LPCAC_MEM_REQ[8] <RW> 更多...

__I uint32 reserved2: 23
	reserved[9-31] <RESV>

} lpcac_ctrl_bit

};

uint8	reserved9 [272]
	Reserved space (保留空間)

__IO uint32	pwm0subctl
	PWM0 Submodule Control Register (PWM0子模組控制寄存器)

uint8	reserved10 [4]
	Reserved space (保留空間)

__IO uint32	ctimerglobalstarten
	CTIMER Global Start Enable Register (CTIMER全域啟動使能寄存器)

__IO uint32	ram_ctrl
	RAM Control Register (RAM控制寄存器)

uint8	reserved_11 [536]
	Reserved space (保留空間)

__IO uint32	gray_code_lsb
	Gray to Binary Converter Gray Code LSB Register (格雷碼轉二進制轉換器格雷碼LSB寄存器)

__IO uint32	gray_code_msb
	Gray to Binary Converter Gray Code MSB Register (格雷碼轉二進制轉換器格雷碼MSB寄存器)

__I uint32	binary_code_lsb
	Gray to Binary Converter Binary Code LSB Register (格雷碼轉二進制轉換器二進制碼LSB寄存器)

__I uint32	binary_code_msb
	Gray to Binary Converter Binary Code MSB Register (格雷碼轉二進制轉換器二進制碼MSB寄存器)

uint8	reserved_12 [720]
	Reserved space (保留空間)

__I uint32	ovp_pad_state
	OVP PAD State Register (過壓保護墊狀態寄存器)

__I uint32	probe_state
	Probe State Register (探測狀態寄存器)

__I uint32	ft_state_a
	Factory Test State A Register (工廠測試狀態A寄存器)

__I uint32	rop_state
	ROP (Root of Trust Protection) State Register (信任根保護狀態寄存器)

uint8	reserved_13 [8]
	Reserved space (保留空間)

__IO uint32	sram_xen
	SRAM XEN (eXecute Never) Control Register (SRAM執行從不控制寄存器)

__IO uint32	sram_xen_dp
	SRAM XEN Control Duplicate Register (SRAM執行從不控制複製寄存器)

uint8	reserved_14 [32]
	Reserved space (保留空間)

__I uint32	els_otp_lc_state
	ELS OTP Life Cycle State Register (ELS OTP生命週期狀態寄存器)

__I uint32	els_otp_lc_state_DP
	ELS OTP Life Cycle State Duplicate Register (ELS OTP生命週期狀態複製寄存器)

uint8	reserved_15 [280]
	Reserved space (保留空間)

__IO uint32	debug_lock_en
	Debug Lock Enable Register (除錯鎖定使能寄存器)

__IO uint32	debug_features
	Debug Features Control Register (除錯功能控制寄存器)

__IO uint32	debug_features_dp
	Debug Features Control Duplicate Register (除錯功能控制複製寄存器)

uint8	reserved_16 [8]
	Reserved space (保留空間)

__IO uint32	swd_access_cpu0
	CPU0 Software Debug Access Register (CPU0軟體除錯存取寄存器)

uint8	reserved_17 [8]
	Reserved space (保留空間)

__IO uint32	debug_auth_beacon
	Debug Authentication BEACON Register (除錯認證信標寄存器)

uint8	reserved_18 [44]
	Reserved space (保留空間)

__I uint32	jtag_id
	JTAG Chip ID Register (JTAG晶片ID寄存器)

__I uint32	device_type
	Device Type Register (裝置類型寄存器)

__I uint32	device_id0
	Device ID Register (裝置ID寄存器)

__I uint32	dieid
	Die ID Register (晶粒ID寄存器)

詳細描述

MCXA153 SYSCON (System Configuration Controller) Register Structure (SYSCON寄存器結構)

This structure provides access to all SYSCON peripheral registers, which control:

Memory remapping and AHB matrix configuration (記憶體重映射和AHB矩陣配置)
Clock control and divider settings (時鐘控制和分頻設定)
System power management controls (系統電源管理控制)
Debug and security features (除錯和安全功能)
Non-volatile memory control (非揮發性記憶體控制)
Cache and memory access control (快取和記憶體存取控制)
Device identification registers (裝置識別寄存器)

Base Address: 0x40000000 Memory Region: APB Bus Access: Privileged only

註: SYSCON寄存器控制晶片核心系統功能，錯誤配置可能導致系統故障

警告: Many registers have lock bits - once set, they cannot be modified until reset

注意: Some configurations require specific write sequences or unlock codes

資料成員說明文件

◆ ahbclkdiv

__IO uint32 mcxa153::chip::syscon::Register::ahbclkdiv

System Clock Divider Register (系統時鐘分頻寄存器)

Controls the AHB bus clock frequency by dividing the system clock. This directly affects CPU, memory, and high-speed peripheral timing.

Address: 0x380 Access: Read-Write (may require unlock sequence) Reset Value: 0x00000000 (divide by 1)

Divider Values:

0x00: Divide by 1 (full speed)
0x01: Divide by 2
0x02: Divide by 4
0xFF: Divide by 256

註: AHB時鐘影響CPU和記憶體存取速度，需謹慎設定

警告: Higher division ratios reduce system performance

注意: Some peripherals may have minimum clock requirements System Clock Divider, offset: 0x380

◆ ahbmatprio

__IO uint32 mcxa153::chip::syscon::Register::ahbmatprio

AHB Matrix Priority Control Register (AHB矩陣優先權控制寄存器)

Controls the priority levels for AHB matrix masters when accessing shared resources. Higher priority masters can preempt lower priority transactions.

Address: 0x210 Access: Read-Write Reset Value: Implementation defined

註: 配置AHB匯流排仲裁優先權，影響CPU、DMA等主控器的存取權限

警告: Incorrect priority settings may cause system performance degradation AHB Matrix Priority Control, offset: 0x210

◆ binary_code_lsb

__I uint32 mcxa153::chip::syscon::Register::binary_code_lsb

Gray to Binary Converter Binary Code LSB Register (格雷碼轉二進制轉換器二進制碼LSB寄存器)

Output register containing converted binary code bits [31:0]. Read this register after writing to GRAY_CODE registers.

Address: 0xB68 Access: Read-Only Reset Value: 0x00000000

註: 唯讀寄存器，包含轉換後的二進制碼低32位

警告: Conversion results are valid only after Gray code input is stable Gray to Binary Converter Binary Code [31:0], offset: 0xB68

◆ binary_code_msb

__I uint32 mcxa153::chip::syscon::Register::binary_code_msb

Gray to Binary Converter Binary Code MSB Register (格雷碼轉二進制轉換器二進制碼MSB寄存器)

Output register containing converted binary code bits [41:32]. Contains the upper 10 bits of the 42-bit conversion result.

Address: 0xB6C Access: Read-Only Reset Value: 0x00000000

註: 包含42位元轉換結果的高10位 Gray to Binary Converter Binary Code [41:32], offset: 0xB6C

◆ clkunlock

__IO uint32 mcxa153::chip::syscon::Register::clkunlock

CLKUNLOCK[0x3FC] <RW>

This register controls access to the clock select and divider configuration registers.

◆ [struct]

struct { ... } mcxa153::chip::syscon::Register::clkunlock_bit

CLKUNLOCK[0x3FC] <RW>

This register controls access to the clock select and divider configuration registers.

◆ clr_lpcac

__IO uint32 mcxa153::chip::syscon::Register::clr_lpcac

CLR_LPCAC[1] <RW>

Clears the cache function.

[0b]Unclears the cache
[1b]Clears the cache

◆ cpu0_sbus

__IO uint32 mcxa153::chip::syscon::Register::cpu0_sbus

RAMX0[0-1] <RW>

address remap for CPU System bus

[00b]RAMX0: 0x04000000 - 0x04001ff
[01b]RAMX0: 0x20006000 - 0x20007fff

◆ cpu0nstckcal

__IO uint32 mcxa153::chip::syscon::Register::cpu0nstckcal

Non-Secure CPU0 System Tick Calibration Register (非安全CPU0系統滴答校準寄存器)

Provides calibration value for the ARM Cortex-M33 SysTick timer. This register contains a pre-calculated value representing the exact number of clock cycles per 10ms period for accurate timing.

Address: 0x23C Access: Read-Write Reset Value: Calculated based on system clock

Bit Fields:

[23:0] TENMS: Calibration value for 10ms timing
[30] SKEW: Clock skew flag
[31] NOREF: No reference clock flag

註: 用於校準SysTick定時器，確保精確的10ms時基

警告: Modifying this value may affect system timing accuracy Non-Secure CPU0 System Tick Calibration, offset: 0x23C

◆ cpustat

__I uint32 mcxa153::chip::syscon::Register::cpustat

CPU Status Register (CPU狀態寄存器)

Provides current CPU operational status including:

Sleep/wake status
Debug halt status
Security state information
Lock status indicators

Address: 0x80C Access: Read-Only Reset Value: 0x00000000

註: 唯讀寄存器，提供CPU當前運行狀態資訊

警告: Status may change asynchronously with system events CPU Status, offset: 0x80C

◆ ctimerglobalstarten

__IO uint32 mcxa153::chip::syscon::Register::ctimerglobalstarten

CTIMER Global Start Enable Register (CTIMER全域啟動使能寄存器)

Provides synchronized start control for multiple CTIMER instances. When enabled, all configured CTIMERs start counting simultaneously.

Address: 0x940 Access: Read-Write Reset Value: 0x00000000

Features:

Multi-timer synchronization
Global start/stop control
Precise timing alignment

註: 用於多個定時器的同步啟動控制

警告: All enabled timers will start simultaneously when triggered CTIMER Global Start Enable, offset: 0x940

◆ debug_auth_beacon

__IO uint32 mcxa153::chip::syscon::Register::debug_auth_beacon

Debug Authentication BEACON Register (除錯認證信標寄存器)

Provides authentication beacon for secure debug access. Contains cryptographic challenge/response data for debug authentication.

Address: 0xFC0 Access: Read-Write Reset Value: 0x00000000

註: 用於安全除錯存取的加密認證信標

警告: Authentication failures may trigger security responses

注意: Critical for secure debug access control Debug Authentication BEACON, offset: 0xFC0

◆ debug_features

__IO uint32 mcxa153::chip::syscon::Register::debug_features

Debug Features Control Register (除錯功能控制寄存器)

Controls availability of ARM Cortex-M33 debug features including:

Invasive debug enable/disable
Non-invasive debug control
Trace functionality
Debug authentication requirements

Address: 0xFA4 Access: Read-Write Reset Value: Security policy dependent

註: 控制ARM Cortex-M33的除錯功能可用性

警告: Disabling debug features may prevent development and troubleshooting

注意: Settings may be restricted by security policy Cortex Debug Features Control, offset: 0xFA4

◆ debug_features_dp

__IO uint32 mcxa153::chip::syscon::Register::debug_features_dp

Debug Features Control Duplicate Register (除錯功能控制複製寄存器)

Duplicate copy of debug features control for redundancy. Both registers must match for debug settings to take effect.

Address: 0xFA8 Access: Read-Write Reset Value: Security policy dependent

註: 冗餘機制確保除錯設定的可靠性

警告: Mismatch may disable debug functionality Cortex Debug Features Control (Duplicate), offset: 0xFA8

◆ debug_lock_en

__IO uint32 mcxa153::chip::syscon::Register::debug_lock_en

Debug Lock Enable Register (除錯鎖定使能寄存器)

Controls write access to security-related registers and debug features. When locked, prevents modification of critical security settings.

Address: 0xFA0 Access: Read-Write (write-once when locked) Reset Value: 0x00000000

註: 控制安全相關寄存器的寫入權限

警告: Once locked, settings cannot be changed until reset

注意: Critical for preventing unauthorized security configuration changes Control Write Access to Security, offset: 0xFA0

◆ device_id0

__I uint32 mcxa153::chip::syscon::Register::device_id0

Device ID Register (裝置ID寄存器)

Contains unique device identification information including:

Silicon revision
Device family
Manufacturing information

Address: 0xFF8 Access: Read-Only Reset Value: Device specific

註: 包含唯一的裝置識別資訊

注意: Critical for device-specific software adaptation Device ID, offset: 0xFF8

◆ device_type

__I uint32 mcxa153::chip::syscon::Register::device_type

Device Type Register (裝置類型寄存器)

Identifies the specific device variant and configuration. Contains information about memory size, peripheral set, and package type.

Address: 0xFF4 Access: Read-Only Reset Value: Device specific

註: 識別具體的裝置變體和配置資訊

注意: Used by software to determine device capabilities Device Type, offset: 0xFF4

◆ dieid

__I uint32 mcxa153::chip::syscon::Register::dieid

Die ID Register (晶粒ID寄存器)

Contains chip revision ID and manufacturing lot information. Provides traceability for silicon revision and production data.

Address: 0xFFC Access: Read-Only Reset Value: Factory programmed

Information includes:

Silicon revision number
Manufacturing date code
Production lot identification
Wafer position data

註: 晶片版本和製造批次資訊，用於品質追蹤

注意: Useful for identifying silicon errata and compatibility Chip Revision ID and Number, offset: 0xFFC

◆ dis_lpcac

__IO uint32 mcxa153::chip::syscon::Register::dis_lpcac

DIS_LPCAC[0] <RW>

Disables/enables the cache function.

[0b]Enabled
[1b]Disabled

◆ dis_lpcac_wtbf

__IO uint32 mcxa153::chip::syscon::Register::dis_lpcac_wtbf

DIS_LPCAC_WTBF[4] <RW>

Disable LPCAC Write Through Buffer.

[0b]Enables write through buffer
[1b]Disables write through buffer

◆ dma0

__IO uint32 mcxa153::chip::syscon::Register::dma0

RAMX0[2-3] <RW>

address remap for DMA0

[00b]RAMX0: 0x04000000 - 0x04001fff
[01b]RAMX0: same alias space as CPU0_SBUS

◆ els_otp_lc_state

__I uint32 mcxa153::chip::syscon::Register::els_otp_lc_state

ELS OTP Life Cycle State Register (ELS OTP生命週期狀態寄存器)

Provides current life cycle state information from One-Time Programmable (OTP) memory. Indicates device provisioning and security configuration status.

Address: 0xE80 Access: Read-Only Reset Value: OTP programmed value

Life Cycle States:

Virgin: Unprogrammed device
In Field Return: RMA state
OEM Production: Manufacturing state
Deployed: Normal operation state
Secure: High security mode

註: 顯示裝置的生命週期狀態，影響安全策略

警告: Life cycle transitions are typically irreversible

注意: Critical for security policy enforcement Life Cycle State Register, offset: 0xE80

◆ els_otp_lc_state_DP

__I uint32 mcxa153::chip::syscon::Register::els_otp_lc_state_DP

ELS OTP Life Cycle State Duplicate Register (ELS OTP生命週期狀態複製寄存器)

Duplicate copy of life cycle state for redundancy and fault detection. Both registers should contain identical values.

Address: 0xE84 Access: Read-Only Reset Value: OTP programmed value

註: 冗餘機制確保生命週期狀態的可靠讀取

警告: Mismatch may indicate OTP corruption or fault injection Life Cycle State Register (Duplicate), offset: 0xE84

◆ frc_no_alloc

__IO uint32 mcxa153::chip::syscon::Register::frc_no_alloc

FRC_NO_ALLOC[2] <RW>

Forces no allocation.

[0b]Forces allocation
[1b]Forces no allocation

◆ ft_state_a

__I uint32 mcxa153::chip::syscon::Register::ft_state_a

Factory Test State A Register (工廠測試狀態A寄存器)

Contains factory test status and configuration information. Used during manufacturing test and quality assurance processes.

Address: 0xE48 Access: Read-Only Reset Value: Factory programmed

註: 包含工廠測試狀態，通常在製造過程中設定

注意: Factory test information should not be modified in application code FT_STATE_A, offset: 0xE48

◆ gray_code_lsb

__IO uint32 mcxa153::chip::syscon::Register::gray_code_lsb

Gray to Binary Converter Gray Code LSB Register (格雷碼轉二進制轉換器格雷碼LSB寄存器)

Input register for Gray code bits [31:0] to be converted to binary format. This hardware converter provides efficient Gray-to-Binary conversion.

Address: 0xB60 Access: Read-Write Reset Value: 0x00000000

註: 硬體格雷碼轉換器，用於高效率的編碼轉換

警告: Write to this register triggers the conversion process Gray to Binary Converter Gray Code [31:0], offset: 0xB60

◆ gray_code_msb

__IO uint32 mcxa153::chip::syscon::Register::gray_code_msb

Gray to Binary Converter Gray Code MSB Register (格雷碼轉二進制轉換器格雷碼MSB寄存器)

Input register for Gray code bits [41:32] to be converted to binary format. Used together with GRAY_CODE_LSB for 42-bit Gray code conversion.

Address: 0xB64 Access: Read-Write Reset Value: 0x00000000

註: 與LSB寄存器配合使用，支援42位元格雷碼轉換 Gray to Binary Converter Gray Code [41:32], offset: 0xB64

◆ jtag_id

__I uint32 mcxa153::chip::syscon::Register::jtag_id

JTAG Chip ID Register (JTAG晶片ID寄存器)

Contains the JTAG Device Identification Register value. Used by debug tools to identify the device type and capabilities.

Address: 0xFF0 Access: Read-Only Reset Value: Factory programmed (0x0BC11477 for MCXA153)

Format (IEEE 1149.1 standard):

[31:28] Version
[27:12] Part Number
[11:1] Manufacturer ID
[0] Always 1

註: 標準JTAG裝置識別碼，用於除錯工具識別

注意: Fixed value, should not be modified JTAG Chip ID, offset: 0xFF0

◆ lim_lpcac_wtbf

__IO uint32 mcxa153::chip::syscon::Register::lim_lpcac_wtbf

LIM_LPCAC_WTBF[5] <RW>

Limit LPCAC Write Through Buffer.

[0b]Write buffer enabled when transaction is bufferable.
[1b]Write buffer enabled when transaction is cacheable and bufferable

◆ lock

__IO uint32 mcxa153::chip::syscon::Register::lock

LOCK[31] <RW>

This 1-bit field provides a mechanism to limit writes to the this register to protect its contents. Once set,this bit remains asserted until a system reset.

[0b]This register is not locked and can be altered.
[1b]This register is locked and cannot be altered until a system reset.

◆ lpcac_mem_req

__IO uint32 mcxa153::chip::syscon::Register::lpcac_mem_req

LPCAC_MEM_REQ[8] <RW>

Request LPCAC memories.

[0b]Configure shared memories RAMX1 as general memories.
[1b]Configure shared memories RAMX1 as LPCAC memories, write one lock until a systemreset.

◆ lpcac_xom

__IO uint32 mcxa153::chip::syscon::Register::lpcac_xom

LPCAC_XOM[7] <RW>

LPCAC XOM(eXecute-Only-Memory) attribute control

Controls if the instruction fetch attribute is used as part of the address input to the LPCAC. When XOM regions in the internal flash are not configured at the MBC, then this option should be disabled so that instructions and data can be stored within the same cache line. This provides the best cache efficiency for non-XOM applications. When XOM areas in the internal flash are configured at the MBC, then this bit must be set so that instructions and data are cached using separate lines within the LPCAC.

[0b]Disabled.
[1b]Enabled.

◆ nmisrc

__IO uint32 mcxa153::chip::syscon::Register::nmisrc

NMI Source Select Register (NMI源選擇寄存器)

Configures the source for Non-Maskable Interrupt (NMI) generation. Multiple internal and external sources can be selected to trigger NMI.

Address: 0x248 Access: Read-Write Reset Value: 0x00000000

Supported NMI Sources:

WWDT timeout
BOD (Brown-out Detection)
External NMI pin
System configuration errors
Security violations

註: NMI是不可遮罩中斷，用於處理系統重要錯誤情況

警告: NMI handlers should be kept minimal and fast

注意: NMI can interrupt any other interrupt service routine NMI Source Select, offset: 0x248

◆ nvm_ctrl

__IO uint32 mcxa153::chip::syscon::Register::nvm_ctrl

NVM (Non-Volatile Memory) Control Register (非揮發性記憶體控制寄存器)

Controls flash memory operation parameters including wait states, prefetch buffer configuration, and cache behavior.

Address: 0x400 Access: Read-Write Reset Value: Implementation defined

Features:

Flash wait state control
Prefetch buffer enable/disable
Cache mode selection
Power optimization settings

註: 配置Flash存取參數，影響程式執行效能

警告: Incorrect settings may cause flash read failures

注意: Wait states must match system clock frequency NVM Control, offset: 0x400

◆ ovp_pad_state

__I uint32 mcxa153::chip::syscon::Register::ovp_pad_state

OVP PAD State Register (過壓保護墊狀態寄存器)

Provides status information about over-voltage protection (OVP) for I/O pads. Indicates which pads have experienced over-voltage conditions.

Address: 0xE40 Access: Read-Only Reset Value: 0x00000000

註: 唯讀寄存器，顯示I/O墊的過壓保護狀態

警告: Over-voltage conditions may indicate hardware issues OVP_PAD_STATE, offset: 0xE40

◆ probe_state

__I uint32 mcxa153::chip::syscon::Register::probe_state

Probe State Register (探測狀態寄存器)

Contains status information about debug probe connections and access states. Used for debugging and development tool interface monitoring.

Address: 0xE44 Access: Read-Only Reset Value: Implementation defined

註: 提供除錯探測器連接和存取狀態資訊

警告: Status changes may affect debug capabilities PROBE_STATE, offset: 0xE44

◆ pwm0subctl

__IO uint32 mcxa153::chip::syscon::Register::pwm0subctl

PWM0 Submodule Control Register (PWM0子模組控制寄存器)

Controls PWM0 submodule operation including:

Submodule enable/disable
Synchronization settings
Force output control
Dead time configuration

Address: 0x938 Access: Read-Write Reset Value: 0x00000000

註: 控制PWM0所有子模組的全域設定

警告: Changes take effect immediately and may affect ongoing PWM operation PWM0 Submodule Control, offset: 0x938

◆ ram_ctrl

__IO uint32 mcxa153::chip::syscon::Register::ram_ctrl

RAM Control Register (RAM控制寄存器)

Controls SRAM memory operation parameters including:

Power mode settings
Wait state configuration
Error correction enable
Retention control

Address: 0x944 Access: Read-Write Reset Value: Safe default settings

註: 配置SRAM的電源和存取參數

警告: Incorrect settings may cause memory access failures

注意: Changes may affect system performance and power consumption RAM Control, offset: 0x944

◆ remap

__IO uint32 mcxa153::chip::syscon::Register::remap

REMAP[0x200] <RW>

AHB Matrix Remap Control

The Multilayer AHB Matrix remap for all masters, when they attempt to access the matrix slave port.

◆ [struct]

struct { ... } mcxa153::chip::syscon::Register::remap_bit

REMAP[0x200] <RW>

AHB Matrix Remap Control

The Multilayer AHB Matrix remap for all masters, when they attempt to access the matrix slave port.

◆ reserved

__I uint32 mcxa153::chip::syscon::Register::reserved

—[1-31] <RESV>

Reserved

◆ reserved0 [1/2]

uint8 mcxa153::chip::syscon::Register::reserved0[512]

Reserved space (保留空間)

Reserved memory region from 0x000 to 0x1FF 512 bytes reserved for future use

◆ reserved0 [2/2]

__I uint32 mcxa153::chip::syscon::Register::reserved0

Reserved[6-30].

Reserved[3] <RESD>

Reserved Read value is undefined, only zero should be written.

◆ reserved1

uint8 mcxa153::chip::syscon::Register::reserved1[12]

Reserved space (保留空間)

Reserved memory region for alignment 12 bytes padding after REMAP register

◆ reserved10

uint8 mcxa153::chip::syscon::Register::reserved10[4]

Reserved space (保留空間)

Reserved memory region for alignment 4 bytes padding after PWM0SUBCTL register

◆ reserved2

uint8 mcxa153::chip::syscon::Register::reserved2[40]

Reserved space (保留空間)

Reserved memory region for alignment 40 bytes padding after AHBMATPRIO register

◆ reserved3

uint8 mcxa153::chip::syscon::Register::reserved3[8]

Reserved space (保留空間)

Reserved memory region for alignment 8 bytes padding after CPU0NSTCKCAL register

◆ reserved4

uint8 mcxa153::chip::syscon::Register::reserved4[300]

Reserved space (保留空間)

Reserved memory region for alignment 300 bytes padding after NMISRC register

◆ reserved5

uint8 mcxa153::chip::syscon::Register::reserved5[4]

Reserved space (保留空間)

Reserved memory region for alignment 4 bytes padding after SLOWCLKDIV register

◆ reserved6

uint8 mcxa153::chip::syscon::Register::reserved6[120]

Reserved space (保留空間)

Reserved memory region for alignment 120 bytes padding after AHBCLKDIV register

◆ reserved7

uint8 mcxa153::chip::syscon::Register::reserved7[1028]

Reserved space (保留空間)

Reserved memory region for alignment 1028 bytes padding after ROMCR register

◆ reserved8

uint8 mcxa153::chip::syscon::Register::reserved8[20]

Reserved space (保留空間)

Reserved memory region for alignment 20 bytes padding after CPUSTAT register

◆ reserved9

uint8 mcxa153::chip::syscon::Register::reserved9[272]

Reserved space (保留空間)

Reserved memory region for alignment 272 bytes padding after LPCAC_CTRL register

◆ reserved_11

uint8 mcxa153::chip::syscon::Register::reserved_11[536]

Reserved space (保留空間)

Reserved memory region for alignment 536 bytes padding after RAM_CTRL register

◆ reserved_12

uint8 mcxa153::chip::syscon::Register::reserved_12[720]

Reserved space (保留空間)

Reserved memory region for alignment 720 bytes padding after Binary Code MSB register

◆ reserved_13

uint8 mcxa153::chip::syscon::Register::reserved_13[8]

Reserved space (保留空間)

Reserved memory region for alignment 8 bytes padding after ROP_STATE register

◆ reserved_14

uint8 mcxa153::chip::syscon::Register::reserved_14[32]

Reserved space (保留空間)

Reserved memory region for alignment 32 bytes padding after SRAM_XEN_DP register

◆ reserved_15

uint8 mcxa153::chip::syscon::Register::reserved_15[280]

Reserved space (保留空間)

Reserved memory region for alignment 280 bytes padding after ELS_OTP_LC_STATE_DP register

◆ reserved_16

uint8 mcxa153::chip::syscon::Register::reserved_16[8]

Reserved space (保留空間)

Reserved memory region for alignment 8 bytes padding after DEBUG_FEATURES_DP register

◆ reserved_17

uint8 mcxa153::chip::syscon::Register::reserved_17[8]

Reserved space (保留空間)

Reserved memory region for alignment 8 bytes padding after SWD_ACCESS_CPU0 register

◆ reserved_18

uint8 mcxa153::chip::syscon::Register::reserved_18[44]

Reserved space (保留空間)

Reserved memory region for alignment 44 bytes padding after DEBUG_AUTH_BEACON register

◆ romcr

uint32 mcxa153::chip::syscon::Register::romcr

ROM Wait State Register (ROM等待狀態寄存器)

Configures wait states for ROM memory access to ensure reliable operation at different system clock frequencies.

Address: 0x404 Access: Read-Write Reset Value: Safe default for maximum frequency

註: ROM等待狀態確保高頻率下的可靠存取

警告: Too few wait states may cause data corruption ROM Wait State, offset: 0x404

◆ rop_state

__I uint32 mcxa153::chip::syscon::Register::rop_state

ROP (Root of Trust Protection) State Register (信任根保護狀態寄存器)

Provides status of Root of Trust Protection mechanisms including:

Secure boot status
Tamper detection state
Security violation indicators
Trust anchor validation results

Address: 0xE4C Access: Read-Only Reset Value: Security dependent

註: 顯示系統安全和信任根保護的狀態

警告: Security violations may trigger system protection responses

注意: Critical for secure boot and anti-tamper functionality ROP State Register, offset: 0xE4C

◆ slowclkdiv

__IO uint32 mcxa153::chip::syscon::Register::slowclkdiv

SLOW_CLK Clock Divider Register (慢速時鐘分頻寄存器)

Controls the division ratio for the SLOW_CLK domain, which is used for low-power peripheral operations and wake-up timing.

Address: 0x378 Access: Read-Write Reset Value: 0x00000000

Divider Range: 1-256 (8-bit divider) Input Clock: Typically 32kHz internal oscillator

註: 慢速時鐘用於低功耗週邊和喚醒時序控制

警告: Changing this divider affects all SLOW_CLK dependent functions SLOW_CLK Clock Divider, offset: 0x378

◆ sram_xen

__IO uint32 mcxa153::chip::syscon::Register::sram_xen

SRAM XEN (eXecute Never) Control Register (SRAM執行從不控制寄存器)

Controls execute-never attributes for SRAM regions to prevent code execution from data memory areas. Enhances security by preventing certain types of exploits.

Address: 0xE58 Access: Read-Write Reset Value: 0x00000000

Features:

Per-region XN control
Code injection protection
Data execution prevention

註: 防止從資料記憶體區域執行程式碼，提高系統安全性

警告: Enabling XN on regions containing executable code will cause faults

注意: Critical for preventing code injection attacks RAM XEN Control, offset: 0xE58

◆ sram_xen_dp

__IO uint32 mcxa153::chip::syscon::Register::sram_xen_dp

SRAM XEN Control Duplicate Register (SRAM執行從不控制複製寄存器)

Duplicate copy of SRAM_XEN register for redundancy and fault tolerance. Both registers must match for XEN settings to take effect.

Address: 0xE5C Access: Read-Write Reset Value: 0x00000000

註: 冗餘安全機制，與SRAM_XEN必須一致才能生效

警告: Mismatch between registers may trigger security fault RAM XEN Control (Duplicate), offset: 0xE5C

◆ swd_access_cpu0

__IO uint32 mcxa153::chip::syscon::Register::swd_access_cpu0

CPU0 Software Debug Access Register (CPU0軟體除錯存取寄存器)

Controls software-based debug access permissions for CPU0. Manages debug halt, single-step, and breakpoint capabilities.

Address: 0xFB4 Access: Read-Write Reset Value: Security policy dependent

註: 控制CPU0的軟體除錯存取權限

警告: Incorrect settings may prevent or compromise debugging CPU0 Software Debug Access, offset: 0xFB4

◆ unlock

__IO uint32 mcxa153::chip::syscon::Register::unlock

UNLOCK[0] <RW>

Controls clock configuration registers access (for example, MRCC_xxx_CLKDIV, MRCC_xxx_CLKSEL, MRCC_GLB_xxx)

-[0b]Updates are allowed to all clock configuration registers

-[1b]Freezes all clock configuration registers update

◆ usb0

__IO uint32 mcxa153::chip::syscon::Register::usb0

RAMX0[4-5] <RW>

address remap for USB0

[00b]RAMX0: 0x04000000 - 0x04001fff
[01b]RAMX0: same alias space as CPU0_SBUS

此結構(structure) 文件是由下列檔案中產生:

syscon/Register.h

公開屬性

詳細描述

資料成員說明文件

◆ ahbclkdiv

◆ ahbmatprio

◆ binary_code_lsb

◆ binary_code_msb

◆ clkunlock

◆ [struct]

◆ clr_lpcac

◆ cpu0_sbus

◆ cpu0nstckcal

◆ cpustat

◆ ctimerglobalstarten

◆ debug_auth_beacon

◆ debug_features

◆ debug_features_dp

◆ debug_lock_en

◆ device_id0

◆ device_type

◆ dieid

◆ dis_lpcac

◆ dis_lpcac_wtbf

◆ dma0

◆ els_otp_lc_state

◆ els_otp_lc_state_DP

◆ frc_no_alloc

◆ ft_state_a

◆ gray_code_lsb

◆ gray_code_msb

◆ jtag_id

◆ lim_lpcac_wtbf

◆ lock

◆ lpcac_mem_req

◆ lpcac_xom

◆ nmisrc

◆ nvm_ctrl

◆ ovp_pad_state

◆ probe_state

◆ pwm0subctl

◆ ram_ctrl

◆ remap

◆ [struct]

◆ reserved

◆ reserved0 [1/2]

◆ reserved0 [2/2]

◆ reserved1

◆ reserved10

◆ reserved2

◆ reserved3

◆ reserved4

◆ reserved5

◆ reserved6

◆ reserved7

◆ reserved8

◆ reserved9

◆ reserved_11

◆ reserved_12

◆ reserved_13

◆ reserved_14

◆ reserved_15

◆ reserved_16

◆ reserved_17

◆ reserved_18

◆ romcr

◆ rop_state

◆ slowclkdiv

◆ sram_xen

◆ sram_xen_dp

◆ swd_access_cpu0

◆ unlock

◆ usb0