syscon/Register.h

 
#ifndef MCXA153_CD9117FB_B933_4D45_964D_52C0E091814C
#define MCXA153_CD9117FB_B933_4D45_964D_52C0E091814C
 
/* ***************************************************************************************
 * Include
 */
#include "mframe.h"
 
//----------------------------------------------------------------------------------------
 
//----------------------------------------------------------------------------------------
 
/* ***************************************************************************************
 * Namespace
 */
namespace mcxa153::chip::syscon {
  struct Register;
}  // namespace mcxa153::chip::syscon
 
/* ***************************************************************************************
 * Class/Interface/Struct/Enum
 */
 
struct mcxa153::chip::syscon::Register {
  uint8 reserved0[512];
 
  union {
    __IO uint32 remap;
 
    struct {
      __IO uint32 cpu0_sbus : 2;
 
      __IO uint32 dma0 : 2;
 
      __IO uint32 usb0 : 2;
 
      __I uint32 reserved0 : 25;
 
      __IO uint32 lock : 1;
    } remap_bit;
  };
 
  uint8 reserved1[12];
 
  __IO uint32 ahbmatprio; 
  uint8 reserved2[40];
 
  __IO uint32 cpu0nstckcal; 
  uint8 reserved3[8];
 
  __IO uint32 nmisrc; 
  uint8 reserved4[300];
 
  __IO uint32 slowclkdiv; 
  uint8 reserved5[4];
 
  __IO uint32 ahbclkdiv; 
  uint8 reserved6[120];
  union {
    __IO uint32 clkunlock;
 
    struct {
      __IO uint32 unlock : 1;
 
      __I uint32 reserved : 31;
    } clkunlock_bit;
  };
 
  __IO uint32 nvm_ctrl; 
  uint32 romcr; 
  uint8 reserved7[1028];
 
  __I uint32 cpustat; 
  uint8 reserved8[20];
 
  union {
    __IO uint32 lpcac_ctrl;
 
    struct {
      __IO uint32 dis_lpcac : 1;
 
      __IO uint32 clr_lpcac : 1;
 
      __IO uint32 frc_no_alloc : 1;
 
      __I uint32 reserved0 : 1;
 
      __IO uint32 dis_lpcac_wtbf : 1;
 
      __IO uint32 lim_lpcac_wtbf : 1;
 
      __I uint32 reserved1 : 1;
 
      __IO uint32 lpcac_xom : 1;
 
      __IO uint32 lpcac_mem_req : 1;
 
      __I uint32 reserved2 : 23;
    } lpcac_ctrl_bit;
  };
 
  uint8 reserved9[272];
 
  __IO uint32 pwm0subctl; 
  uint8 reserved10[4];
 
  __IO uint32 ctimerglobalstarten; 
  __IO uint32 ram_ctrl; 
  uint8 reserved_11[536];
 
  __IO uint32
      gray_code_lsb; 
  __IO uint32
      gray_code_msb; 
  __I uint32
      binary_code_lsb; 
  __I uint32
      binary_code_msb; 
  uint8 reserved_12[720];
  __I uint32 ovp_pad_state; 
  __I uint32 probe_state; 
  __I uint32 ft_state_a; 
  __I uint32 rop_state; 
  uint8 reserved_13[8];
 
  __IO uint32 sram_xen; 
  __IO uint32 sram_xen_dp; 
  uint8 reserved_14[32];
 
  __I uint32 els_otp_lc_state; 
  __I uint32
      els_otp_lc_state_DP; 
  uint8 reserved_15[280];
 
  __IO uint32 debug_lock_en; 
  __IO uint32 debug_features; 
  __IO uint32
      debug_features_dp; 
  uint8 reserved_16[8];
 
  __IO uint32 swd_access_cpu0; 
  uint8 reserved_17[8];
 
  __IO uint32 debug_auth_beacon; 
  uint8 reserved_18[44];
 
  __I uint32 jtag_id; 
  __I uint32 device_type; 
  __I uint32 device_id0; 
  __I uint32 dieid; 
};
 
/* ***************************************************************************************
 * End of file
 */
 
#endif /* MCXA153_CD9117FB_B933_4D45_964D_52C0E091814C */