命名空間(Namespaces)
namespace	mask

複合項目
struct	Register
	MCXA153 SYSCON (System Configuration Controller) Register Structure (SYSCON寄存器結構) 更多...

class	SYSCON
	MCXA153 系統控制器 (SYSCON) 管理介面更多...

列舉型態
enum struct	Count : unsigned int { Usage , WAKEUP_WAKEUPA = 2U }
	SYSCON Resource Count Enumeration. 更多...

enum struct	Mask : unsigned int { REMAP_CPU0_SBUS = 0x000000003U , REMAP_DMA0 = 0x00000000CU , REMAP_USB0 = 0x00000030U , REMAP_LOCK = 0x80000000U , AHBMATPRIO_CPU0_CBUS = 0x00000003U , AHBMATPRIO_CPU0_SBUS = 0x0000000CU , AHBMATPRIO_DMA0 = 0x00000300U , AHBMATPRIO_USB_FS_ENET = 0x03000000U , CPU0NSTCKCAL_TENMS = 0x00FFFFFFU , CPU0NSTCKCAL_SKEW = 0x01000000U , CPU0NSTCKCAL_NOREF = 0x02000000U , NMISRC_IRQCPU0 = 0x000000FFU , NMISRC_NMIENCPU0 = 0x80000000U , SLOWCLKDIV_RESET = 0x20000000U , SLOWCLKDIV_HALT = 0x40000000U , SLOWCLKDIV_UNSTAB = 0x80000000U , AHBCLKDIV_DIV = 0x000000FFU , AHBCLKDIV_UNSTAB = 0x80000000U , CLKUNLOCK_UNLOCK = 0x00000001U , NVM_CTRL_DIS_FLASH_SPEC = 0x00000001U , NVM_CTRL_DIS_DATA_SPEC = 0x00000002U , NVM_CTRL_FLASH_STALL_EN = 0x00000400U , NVM_CTRL_DIS_MBECC_ERR_INST = 0x00010000U , NVM_CTRL_DIS_MBECC_ERR_DATA = 0x00020000U , CPUSTAT_CPU0SLEEPING = 0x000000001U , CPUSTAT_CPU0LOCKUP = 0x00000004U , LPCAC_CTRL_DIS_LPCAC = 0x00000001U , LPCAC_CTRL_CLR_LPCAC = 0x00000002U , LPCAC_CTRL_FRC_NO_ALLOC = 0x00000004U , LPCAC_CTRL_DIS_LPCAC_WTBF = 0x00000010U , LPCAC_CTRL_LIM_LPCAC_WTBF = 0x00000020U , LPCAC_CTRL_LPCAC_XOM = 0x00000080U , LPCAC_CTRL_LPCAC_MEM_REQ = 0x00000100U , PWM0SUBCTL_CLK0_EN = 0x00000001U , PWM0SUBCTL_CLK1_EN = 0x00000002U , PWM0SUBCTL_CLK2_EN = 0x00000004U , PWM0SUBCTL_CLK3_EN = 0x00000008U , PWM1SUBCTL_CLK0_EN = 0x00000001U , PWM1SUBCTL_CLK1_EN = 0x00000002U , PWM1SUBCTL_CLK2_EN = 0x00000004U , PWM1SUBCTL_CLK3_EN = 0x00000008U , CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN = 0x00000001U , CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN = 0x00000002U , CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN = 0x00000004U , CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN = 0x00000008U , CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN = 0x00000010U , RAM_CTRL_RAMA_ECC_ENABLE = 0x0000001U , RAM_CTRL_RAMA_CG_OVERRIDE = 0x00010000U , RAM_CTRL_RAMX_CG_OVERRIDE = 0x00020000U , RAM_CTRL_RAMB_CG_OVERRIDE = 0x00040000U , GRAY_CODE_LSB_code_gray_31_0 = 0xFFFFFFFFU , GRAY_CODE_MSB_code_gray_41_32 = 0x000003FFU , BINARY_CODE_LSB_code_bin_31_0 = 0xFFFFFFFFU , BINARY_CODE_MSB_code_bin_41_32 = 0x000003FFU , ROP_STATE_ROP_STATE = 0xFFFFFFFFU , OVP_PAD_STATE_OVP_PAD_STATE = 0xFFFFFFFFU , PROBE_STATE_PROBE_STATE = 0xFFFFFFFFU , FT_STATE_A_FT_STATE_A = 0xFFFFFFFFU , FT_STATE_B_FT_STATE_B = 0xFFFFFFFFU , SRAM_XEN_RAMX0_XEN = 0x00000001U , SRAM_XEN_RAMX1_XEN = 0x00000002U , SRAM_XEN_RAMA0_XEN = 0x00000004U , SRAM_XEN_RAMA1_XEN = 0x00000008U , SRAM_XEN_RAMB_XEN = 0x00000010U , SRAM_XEN_LOCK = 0x80000000U , SRAM_XEN_DP_RAMX0_XEN = 0x00000001U , SRAM_XEN_DP_RAMX1_XEN = 0x00000002U , SRAM_XEN_DP_RAMA0_XEN = 0x00000004U , SRAM_XEN_DP_RAMA1_XEN = 0x00000008U , SRAM_XEN_DP_RAMB_XEN = 0x00000010U , ELS_OTP_LC_STATE_OTP_LC_STATE = 0x000000FFU , ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP = 0x000000FFU , DEBUG_LOCK_EN_LOCK_ALL = 0x0000000FU , DEBUG_FEATURES_CPU0_DBGEN = 0x00000003U , DEBUG_FEATURES_CPU0_NIDEN = 0x0000000CU , DEBUG_FEATURES_DP_CPU0_DBGEN = 0x00000003U , DEBUG_FEATURES_DP_CPU0_NIDEN = 0x0000000CU , SWD_ACCESS_CPU0_SEC_CODE = 0xFFFFFFFFU , DEBUG_AUTH_BEACON_BEACON = 0xFFFFFFFFU , JTAG_ID_JTAG_ID = 0xFFFFFFFFU , DEVICE_TYPE_DEVICE_TYPE = 0xFFFFFFFFU , DEVICE_ID0_RAM_SIZE = 0x0000000FU , DEVICE_ID0_FLASH_SIZE = 0x000000F0U , DEVICE_ID0_SECURITY = 0x0F000000U , DIEID_MINOR_REVISION = 0x0000000FU , DIEID_MAJOR_REVISION = 0x000000F0U , DIEID_MCO_NUM_IN_DIE_ID = 0x0FFFFF00U }
	SYSCON Register Bit Mask Enumeration. 更多...

enum struct	Shift : unsigned int { REMAP_CPU0_SBUS = 0U , REMAP_DMA0 = 2U , REMAP_USB0 = 4U , REMAP_LOCK = 31U , AHBMATPRIO_CPU0_CBUS = 0U , AHBMATPRIO_CPU0_SBUS = 2U , AHBMATPRIO_DMA0 = 8U , AHBMATPRIO_USB_FS_ENET = 24U , CPU0NSTCKCAL_TENMS = 0U , CPU0NSTCKCAL_SKEW = 24U , CPU0NSTCKCAL_NOREF = 25U , NMISRC_IRQCPU0 = 0U , NMISRC_NMIENCPU0 = 31U , SLOWCLKDIV_RESET = 29U , SLOWCLKDIV_HALT = 30U , SLOWCLKDIV_UNSTAB = 31U , AHBCLKDIV_DIV = 0U , AHBCLKDIV_UNSTAB = 31U , CLKUNLOCK_UNLOCK = 0U , NVM_CTRL_DIS_FLASH_SPEC = 0U , NVM_CTRL_DIS_DATA_SPEC = 1U , NVM_CTRL_FLASH_STALL_EN = 10U , NVM_CTRL_DIS_MBECC_ERR_INST = 16U , NVM_CTRL_DIS_MBECC_ERR_DATA = 17U , CPUSTAT_CPU0SLEEPING = 0U , CPUSTAT_CPU0LOCKUP = 2U , LPCAC_CTRL_DIS_LPCAC = 0U , LPCAC_CTRL_CLR_LPCAC = 1U , LPCAC_CTRL_FRC_NO_ALLOC = 2U , LPCAC_CTRL_DIS_LPCAC_WTBF = 4U , LPCAC_CTRL_LIM_LPCAC_WTBF = 5U , LPCAC_CTRL_LPCAC_XOM = 7U , LPCAC_CTRL_LPCAC_MEM_REQ = 8U , PWM0SUBCTL_CLK0_EN = 0U , PWM0SUBCTL_CLK1_EN = 1U , PWM0SUBCTL_CLK2_EN = 2U , PWM0SUBCTL_CLK3_EN = 3U , PWM1SUBCTL_CLK0_EN = 0U , PWM1SUBCTL_CLK1_EN = 1U , PWM1SUBCTL_CLK2_EN = 2U , PWM1SUBCTL_CLK3_EN = 3U , CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN = 0U , CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN = 1U , CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN = 2U , CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN = 3U , CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN = 4U , RAM_CTRL_RAMA_ECC_ENABLE = 0U , RAM_CTRL_RAMA_CG_OVERRIDE = 16U , RAM_CTRL_RAMX_CG_OVERRIDE = 17U , RAM_CTRL_RAMB_CG_OVERRIDE = 18U , GRAY_CODE_LSB_code_gray_31_0 = 0U , GRAY_CODE_MSB_code_gray_41_32 = 0U , BINARY_CODE_LSB_code_bin_31_0 = 0U , BINARY_CODE_MSB_code_bin_41_32 = 0U , ROP_STATE_ROP_STATE = 0U , OVP_PAD_STATE_OVP_PAD_STATE = 0U , PROBE_STATE_PROBE_STATE = 0U , FT_STATE_A_FT_STATE_A = 0U , FT_STATE_B_FT_STATE_B = 0U , SRAM_XEN_RAMX0_XEN = 0U , SRAM_XEN_RAMX1_XEN = 1U , SRAM_XEN_RAMA0_XEN = 2U , SRAM_XEN_RAMA1_XEN = 3U , SRAM_XEN_RAMB_XEN = 4U , SRAM_XEN_LOCK = 31U , SRAM_XEN_DP_RAMX0_XEN = 0U , SRAM_XEN_DP_RAMX1_XEN = 1U , SRAM_XEN_DP_RAMA0_XEN = 2U , SRAM_XEN_DP_RAMA1_XEN = 3U , SRAM_XEN_DP_RAMB_XEN = 4U , ELS_OTP_LC_STATE_OTP_LC_STATE = 0U , ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP = 0U , DEBUG_LOCK_EN_LOCK_ALL = 0U , DEBUG_FEATURES_CPU0_DBGEN = 0U , DEBUG_FEATURES_CPU0_NIDEN = 2U , DEBUG_FEATURES_DP_CPU0_DBGEN = 0U , DEBUG_FEATURES_DP_CPU0_NIDEN = 2U , SWD_ACCESS_CPU0_SEC_CODE = 0U , DEBUG_AUTH_BEACON_BEACON = 0U , JTAG_ID_JTAG_ID = 0U , DEVICE_TYPE_DEVICE_TYPE = 0U , DEVICE_ID0_RAM_SIZE = 0U , DEVICE_ID0_FLASH_SIZE = 4U , DEVICE_ID0_SECURITY = 24U , DIEID_MINOR_REVISION = 0U , DIEID_MAJOR_REVISION = 4U , DIEID_MCO_NUM_IN_DIE_ID = 8U }
	MCXA153 SYSCON Bit Shift Positions Enumeration (SYSCON位元偏移位置枚舉) 更多...

函式
constexpr unsigned int	operator+ (Count e)
	Operator Overload - Convert Count enum to unsigned int.

constexpr unsigned int	operator+ (Mask e)
	Operator Overload - Convert Mask enum to unsigned int.

constexpr unsigned int	operator+ (Shift e)

變數
Register &	SYSCON0

詳細描述

SPDX-License-Identifier: MIT

列舉型態說明文件

◆ Count

enum struct mcxa153::chip::syscon::Count : unsigned int

strong

SYSCON Resource Count Enumeration.

Hardware resource count definitions for the MCXA153 System Configuration Controller. These values specify the number of available hardware resources for various system peripherals and wake-up sources.

SYSCON 資源計數枚舉，定義 MCXA153 系統配置控制器的硬體資源數量

Resource Count Features:

Hardware resource availability information
Wake-up source count definitions
System peripheral resource enumeration
Support for dynamic resource allocation and management

註

Usage Applications:

Array allocation for hardware resource management
Loop iteration bounds for resource initialization
Dynamic resource discovery and configuration
System capability determination and validation

警告

Device Compatibility:

Resource counts are device-specific and may vary between chip variants
Always verify actual hardware availability before using resource counts
Some resources may be multiplexed or have usage restrictions
Refer to device datasheet for complete resource specifications

參閱: MCXA153 datasheet for complete hardware resource specifications; Wake-up system documentation for wake-up source details; System peripheral documentation for resource usage guidelines

列舉值

Usage

VBAT Wake-up Source A Count.

Defines the number of available VBAT_WAKEUP_WAKEUPA wake-up sources in the MCXA153 system. These wake-up sources can bring the system out of deep power-down modes and VBAT-powered sleep states.

VBAT 喚醒源 A 的數量，定義系統中可用的 VBAT_WAKEUP_WAKEUPA 喚醒源數目

Wake-up Source Characteristics:

Count: 2 wake-up sources available
VBAT-powered wake-up capability for ultra-low power modes
Can wake system from deepest sleep states
Independent of main system power supply
Configurable trigger conditions and polarity

註

Wake-up Source Applications:

External wake-up signals from buttons or switches
RTC alarm and periodic wake-up events
Communication interface wake-up triggers
Battery-powered system activation sources
Emergency wake-up and system recovery mechanisms

警告

Wake-up Configuration Considerations:

Proper signal conditioning required for reliable wake-up
Debouncing may be necessary for mechanical switch inputs
Wake-up sources consume VBAT power even in deep sleep
Incorrect configuration may prevent system wake-up or cause false triggers

參閱: Wake-up system configuration registers for setup procedures; VBAT power domain documentation for power management details; External interrupt configuration for wake-up source setup

for wake-up source iteration:

for (unsigned int i = 0; i < +Count::WAKEUP_WAKEUPA; ++i) {
    configureWakeupSource(i);
}

◆ Mask

enum struct mcxa153::chip::syscon::Mask : unsigned int

strong

SYSCON Register Bit Mask Enumeration.

Comprehensive bit mask definitions for the MCXA153 System Configuration Controller (SYSCON) registers. This enumeration provides all necessary bit masks for configuring and controlling various system-level functions including memory remapping, clock management, power control, and peripheral configuration.

SYSCON 寄存器位掩碼枚舉，提供 MCXA153 系統配置控制器的完整位掩碼定義

SYSCON Functionality Coverage:

Memory Remapping Control (REMAP) - AHB matrix memory address remapping
AHB Matrix Priority Control (AHBMATPRIO) - Bus master priority levels
System Tick Calibration (CPU0NSTCKCAL) - SysTick timing configuration
NMI Source Configuration (NMISRC) - Non-maskable interrupt control
Clock Divider Control (SLOWCLKDIV, AHBCLKDIV) - System clock management
Non-volatile Memory Control (NVM_CTRL) - Flash memory configuration
CPU Status Monitoring (CPUSTAT) - Processor state information
Cache Control (LPCAC_CTRL) - Low power cache configuration
PWM Submodule Control (PWM0SUBCTL, PWM1SUBCTL) - PWM clock enables
Timer Global Control (CTIMERGLOBALSTARTEN) - CTIMER clock enables
RAM Control (RAM_CTRL) - Memory ECC and clock gating
Code Conversion (GRAY_CODE, BINARY_CODE) - Gray to binary conversion
Security Features (SRAM_XEN, DEBUG_FEATURES) - Execute permissions and debug
Device Identification (DEVICE_ID0, DIEID) - Chip identification and revision

註

Bit Mask Usage Patterns:

Use masks for safe read-modify-write operations on registers
Combine multiple masks with bitwise OR for multi-field operations
Clear fields using bitwise AND with inverted masks before setting new values
Check field values using bitwise AND with appropriate masks

警告

Important Safety Considerations:

Some register fields have lock mechanisms that prevent modification
Incorrect configuration may cause system instability or malfunction
Clock and power-related settings require careful sequencing
Security-related fields may be write-once or require special unlock sequences
Always verify register access permissions before attempting modifications

參閱: MCXA153 Reference Manual for complete register descriptions; Individual register documentation for field-specific usage guidelines; System initialization code for proper configuration sequences

列舉值
REMAP_CPU0_SBUS	REMAP - CPU0_SBUS. AHB Matrix Remap Control - RAMX0 address remap for CPU System bus [0b00]RAMX0: 0x04000000 - 0x04001fff [0b01]RAMX0: 0x2001e000 - 0x2001ffff(for 128KB RAM chip) / 0x20016000 - 0x20017fff(for 96KB RAM chip) / 0x2000e000 - 0x2000ffff(for 64KB RAM chip)
REMAP_DMA0	REMAP - DMA0. AHB Matrix Remap Control - RAMX0 address remap for DMA0 [0b00]RAMX0: 0x04000000 - 0x04001fff [0b01]RAMX0: same alias space as CPU0_SBUS
REMAP_USB0	REMAP - USB0. AHB Matrix Remap Control - RAMX0 address remap for USB0 [0b00]RAMX0: 0x04000000 - 0x04001fff [0b01]RAMX0: same alias space as CPU0_SBUS
REMAP_LOCK	REMAP - LOCK. AHB Matrix Remap Control - This 1-bit field provides a mechanism to limit writes to the this register to protect its contents. Once set, this bit remains asserted until a system reset. [0b0]This register is not locked and can be altered. [0b1]This register is locked and cannot be altered until a system reset.
AHBMATPRIO_CPU0_CBUS	AHBMATPRIO - CPU0_CBUS. AHB Matrix Priority Control - CPU0 C-AHB bus master priority level [0b00]level 0 [0b01]level 1 [0b10]level 2 [0b11]level 3
AHBMATPRIO_CPU0_SBUS	AHBMATPRIO - CPU0_SBUS. AHB Matrix Priority Control - CPU0 S-AHB bus master priority level [0b00]level 0 [0b01]level 1 [0b10]level 2 [0b11]level 3
AHBMATPRIO_DMA0	AHBMATPRIO - DMA0. AHB Matrix Priority Control - DMA0 controller bus master priority level [0b00]level 0 [0b01]level 1 [0b10]level 2 [0b11]level 3
AHBMATPRIO_USB_FS_ENET	AHBMATPRIO - USB_FS_ENET. AHB Matrix Priority Control - USB-FS bus master priority level [0b00]level 0 [0b01]level 1 [0b10]level 2 [0b11]level 3
CPU0NSTCKCAL_TENMS	CPU0NSTCKCAL - TENMS. Non-Secure CPU0 System Tick Calibration - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the value reads as zero, the calibration value is not known.
CPU0NSTCKCAL_SKEW	CPU0NSTCKCAL - SKEW. Non-Secure CPU0 System Tick Calibration - Indicates whether the TENMS value is exact. [0b0]TENMS value is exact [0b1]TENMS value is not exact or not given
CPU0NSTCKCAL_NOREF	CPU0NSTCKCAL - NOREF. Non-Secure CPU0 System Tick Calibration - Indicates whether the device provides a reference clock to the processor. [0b0]Reference clock is provided [0b1]No reference clock is provided
NMISRC_IRQCPU0	NMISRC - IRQCPU0. NMI Source Select - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for CPU0, if enabled by NMIENCPU0.
NMISRC_NMIENCPU0	NMISRC - NMIENCPU0. NMI Source Select - Enables the Non-Maskable Interrupt (NMI) source selected by IRQCPU0. [0b1][Enable. [0b0]Disable.
SLOWCLKDIV_RESET	SLOWCLKDIV - RESET. SLOW_CLK Clock Divider - Resets the divider counter [0b1]Divider is reset [0b0]Divider is not reset
SLOWCLKDIV_HALT	SLOWCLKDIV - HALT. SLOW_CLK Clock Divider - Halts the divider counter [0b1]Divider clock is stopped [0b0]Divider clock is running
SLOWCLKDIV_UNSTAB	SLOWCLKDIV - UNSTAB. SLOW_CLK Clock Divider - Divider status flag [0b1]Clock frequency is not stable [0b0]Divider clock is stable
AHBCLKDIV_DIV	AHBCLKDIV - DIV. System Clock Divider - Clock divider value
AHBCLKDIV_UNSTAB	AHBCLKDIV - UNSTAB. System Clock Divider - Divider status flag [0b1]Clock frequency is not stable [0b0]Divider clock is stable
CLKUNLOCK_UNLOCK	CLKUNLOCK - UNLOCK. Clock Configuration Unlock - Controls clock configuration registers access (for example, MRCC_xxx_CLKDIV, MRCC_xxx_CLKSEL, MRCC_GLB_xxx) [0b1]Freezes all clock configuration registers update. [0b0]Updates are allowed to all clock configuration registers
NVM_CTRL_DIS_FLASH_SPEC	NVM_CTRL - DIS_FLASH_SPEC. NVM Control - Flash speculation control [0b0]Enables flash speculation [0b1]Disables flash speculation
NVM_CTRL_DIS_DATA_SPEC	NVM_CTRL - DIS_DATA_SPEC. NVM Control -Flash data speculation control [0b0]Enables data speculation [0b1]Disables data speculation
NVM_CTRL_FLASH_STALL_EN	NVM_CTRL - FLASH_STALL_EN. NVM Control - FLASH stall on busy control [0b0]No stall on FLASH busy [0b1]Stall on FLASH busy
NVM_CTRL_DIS_MBECC_ERR_INST	NVM_CTRL - DIS_MBECC_ERR_INST. NVM Control [0b0]Enables bus error on multi-bit ECC error for instruction [0b1]Disables bus error on multi-bit ECC error for instruction
NVM_CTRL_DIS_MBECC_ERR_DATA	NVM_CTRL - DIS_MBECC_ERR_DATA. NVM Control [0b0]Enables bus error on multi-bit ECC error for data [0b1]Disables bus error on multi-bit ECC error for data
CPUSTAT_CPU0SLEEPING	CPUSTAT - CPU0SLEEPING. CPU Status - CPU0 sleeping state [0b1]CPU is sleeping [0b0]CPU is not sleeping
CPUSTAT_CPU0LOCKUP	CPUSTAT - CPU0LOCKUP. CPU Status - CPU0 lockup state [0b1]CPU is in lockup [0b0]CPU is not in lockup
LPCAC_CTRL_DIS_LPCAC	LPCAC_CTRL - DIS_LPCAC. LPCAC Control - Disables/enables the cache function. [0b0]Enabled [0b1]Disabled
LPCAC_CTRL_CLR_LPCAC	LPCAC_CTRL - CLR_LPCAC. LPCAC Control - Clears the cache function. [0b0]Unclears the cache [0b1]Clears the cache
LPCAC_CTRL_FRC_NO_ALLOC	LPCAC_CTRL - FRC_NO_ALLOC. LPCAC Control - Forces no allocation. [0b0]Forces allocation [0b1]Forces no allocation
LPCAC_CTRL_DIS_LPCAC_WTBF	LPCAC_CTRL - DIS_LPCAC_WTBF. LPCAC Control - Disable LPCAC Write Through Buffer. [0b1]Disables write through buffer [0b0]Enables write through buffer
LPCAC_CTRL_LIM_LPCAC_WTBF	LPCAC_CTRL - LIM_LPCAC_WTBF. LPCAC Control - Limit LPCAC Write Through Buffer. [0b1]Write buffer enabled when transaction is cacheable and bufferable [0b0]Write buffer enabled when transaction is bufferable.
LPCAC_CTRL_LPCAC_XOM	LPCAC_CTRL - LPCAC_XOM. LPCAC Control - LPCAC XOM(eXecute-Only-Memory) attribute control [0b1]Enabled. [0b0]Disabled.
LPCAC_CTRL_LPCAC_MEM_REQ	LPCAC_CTRL - LPCAC_MEM_REQ. LPCAC Control - Request LPCAC memories. [0b1]Configure shared memories RAMX1 as LPCAC memories, write one lock until a system reset. [0b0]Configure shared memories RAMX1 as general memories.
PWM0SUBCTL_CLK0_EN	PWM0SUBCTL - CLK0_EN. PWM0 Submodule Control - Enables PWM0 SUB Clock0 [0b1]Enable [0b0]Disable
PWM0SUBCTL_CLK1_EN	PWM0SUBCTL - CLK1_EN. PWM0 Submodule Control - Enables PWM0 SUB Clock1 [0b1]Enable [0b0]Disable
PWM0SUBCTL_CLK2_EN	PWM0SUBCTL - CLK2_EN. PWM0 Submodule Control - Enables PWM0 SUB Clock2 [0b1]Enable [0b0]Disable
PWM0SUBCTL_CLK3_EN	PWM0SUBCTL - CLK3_EN. PWM0 Submodule Control - Enables PWM0 SUB Clock3 [0b1]Enable [0b0]Disable
PWM1SUBCTL_CLK0_EN	PWM1SUBCTL - CLK0_EN. PWM1 Submodule Control - Enables PWM1 SUB Clock0 [0b1]Enable [0b0]Disable
PWM1SUBCTL_CLK1_EN	PWM1SUBCTL - CLK1_EN. PWM1 Submodule Control - Enables PWM1 SUB Clock1 [0b1]Enable [0b0]Disable
PWM1SUBCTL_CLK2_EN	PWM1SUBCTL - CLK2_EN. PWM1 Submodule Control - Enables PWM1 SUB Clock2 [0b1]Enable [0b0]Disable
PWM1SUBCTL_CLK3_EN	PWM1SUBCTL - CLK3_EN. PWM1 Submodule Control - Enables PWM1 SUB Clock3 [0b1]Enable [0b0]Disable
CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN	CTIMERGLOBALSTARTEN - CTIMER0_CLK_EN. CTIMER Global Start Enable - Enables the CTIMER0 function clock [0b1]Enable [0b0]Disable
CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN	CTIMERGLOBALSTARTEN - CTIMER1_CLK_EN. CTIMER Global Start Enable - Enables the CTIMER1 function clock [0b1]Enable [0b0]Disable
CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN	CTIMERGLOBALSTARTEN - CTIMER2_CLK_EN. CTIMER Global Start Enable - Enables the CTIMER2 function clock [0b1]Enable [0b0]Disable
CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN	CTIMERGLOBALSTARTEN - CTIMER3_CLK_EN. CTIMER Global Start Enable - Enables the CTIMER3 function clock [0b1]Enable [0b0]Disable
CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN	CTIMERGLOBALSTARTEN - CTIMER4_CLK_EN. CTIMER Global Start Enable - Enables the CTIMER4 function clock [0b1]Enable [0b0]Disable
RAM_CTRL_RAMA_ECC_ENABLE	RAM_CTRL - RAMA_ECC_ENABLE. RAM Control - RAMA0 ECC enable [0b1]ECC is enabled [0b0]ECC is disabled
RAM_CTRL_RAMA_CG_OVERRIDE	RAM_CTRL - RAMA_CG_OVERRIDE. RAM Control - RAMA bank clock gating control, only avaiable when RAMA_ECC_ENABLE = 0. [0b1]Auto clock gating feature is disabled [0b0]Memory bank clock is gated automatically if no access more than 16 clock cycles
RAM_CTRL_RAMX_CG_OVERRIDE	RAM_CTRL - RAMX_CG_OVERRIDE. RAM Control - RAMX bank clock gating control [0b1]Auto clock gating feature is disabled [0b0]Memory bank clock is gated automatically if no access more than 16 clock cycles
RAM_CTRL_RAMB_CG_OVERRIDE	RAM_CTRL - RAMB_CG_OVERRIDE. RAM Control - RAMB bank clock gating control [0b1]Auto clock gating feature is disabled [0b0]Memory bank clock is gated automatically if no access more than 16 clock cycles
GRAY_CODE_LSB_code_gray_31_0	GRAY_CODE_LSB - code_gray_31_0. Gray to Binary Converter Gray Code [31:0] - Gray code [31:0]
GRAY_CODE_MSB_code_gray_41_32	GRAY_CODE_MSB - code_gray_41_32. Gray to Binary Converter Gray Code [41:32] - Gray code [41:32]
BINARY_CODE_LSB_code_bin_31_0	BINARY_CODE_LSB - code_bin_31_0. Gray to Binary Converter Binary Code [31:0] - Binary code [31:0]
BINARY_CODE_MSB_code_bin_41_32	BINARY_CODE_MSB - code_bin_41_32. Gray to Binary Converter Binary Code [41:32] - Binary code [41:32]
ROP_STATE_ROP_STATE	ROP_STATE - ROP_STATE. ROP State Register - ROP state
OVP_PAD_STATE_OVP_PAD_STATE	OVP_PAD_STATE - OVP_PAD_STATE. OVP_PAD_STATE - OVP_PAD_STATE
PROBE_STATE_PROBE_STATE	PROBE_STATE - PROBE_STATE. PROBE_STATE - PROBE_STATE
FT_STATE_A_FT_STATE_A	FT_STATE_A - FT_STATE_A. FT_STATE_A - FT_STATE_A
FT_STATE_B_FT_STATE_B	FT_STATE_B - FT_STATE_B. FT_STATE_B - FT_STATE_B
SRAM_XEN_RAMX0_XEN	SRAM_XEN - RAMX0_XEN. RAM XEN Control - RAMX0 Execute permission control. [0b1]Execute permission is enabled, R/W/X are enabled. [0b0]Execute permission is disabled, R/W are enabled.
SRAM_XEN_RAMX1_XEN	SRAM_XEN - RAMX1_XEN. RAM XEN Control - RAMX1 Execute permission control. [0b1]Execute permission is enabled, R/W/X are enabled. [0b0]Execute permission is disabled, R/W are enabled.
SRAM_XEN_RAMA0_XEN	SRAM_XEN - RAMA0_XEN. RAM XEN Control - RAMA0 Execute permission control. [0b1]Execute permission is enabled, R/W/X are enabled. [0b0]Execute permission is disabled, R/W are enabled.
SRAM_XEN_RAMA1_XEN	SRAM_XEN - RAMA1_XEN. RAM XEN Control - RAMAx (excepts RAMA0) Execute permission control. [0b1]Execute permission is enabled, R/W/X are enabled. [0b0]Execute permission is disabled, R/W are enabled.
SRAM_XEN_RAMB_XEN	SRAM_XEN - RAMB_XEN. RAM XEN Control - RAMBx Execute permission control. [0b1]Execute permission is enabled, R/W/X are enabled. [0b0]Execute permission is disabled, R/W are enabled.
SRAM_XEN_LOCK	SRAM_XEN - LOCK. RAM XEN Control - This 1-bit field provides a mechanism to limit writes to the this register (and SRAM_XEN_DP) to protect its contents. Once set, this bit remains asserted until a system reset. [0b0]This register is not locked and can be altered. [0b1]This register is locked and cannot be altered.
SRAM_XEN_DP_RAMX0_XEN	SRAM_XEN_DP - RAMX0_XEN. RAM XEN Control (Duplicate) - Refer to SRAM_XEN for more details.
SRAM_XEN_DP_RAMX1_XEN	SRAM_XEN_DP - RAMX1_XEN. RAM XEN Control (Duplicate) - Refer to SRAM_XEN for more details.
SRAM_XEN_DP_RAMA0_XEN	SRAM_XEN_DP - RAMA0_XEN. RAM XEN Control (Duplicate) - Refer to SRAM_XEN for more details.
SRAM_XEN_DP_RAMA1_XEN	SRAM_XEN_DP - RAMA1_XEN. RAM XEN Control (Duplicate) - Refer to SRAM_XEN for more details.
SRAM_XEN_DP_RAMB_XEN	SRAM_XEN_DP - RAMB_XEN. RAM XEN Control (Duplicate) - Refer to SRAM_XEN for more details.
ELS_OTP_LC_STATE_OTP_LC_STATE	ELS_OTP_LC_STATE - OTP_LC_STATE. Life Cycle State Register - OTP life cycle state
ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP	ELS_OTP_LC_STATE_DP - OTP_LC_STATE_DP. Life Cycle State Register (Duplicate) - OTP life cycle state
DEBUG_LOCK_EN_LOCK_ALL	DEBUG_LOCK_EN - LOCK_ALL. Control Write Access to Security - Controls write access to the security registers [0b1010]Enables write access to all registers [0b0000]Any other value than b1010: disables write access to all registers
DEBUG_FEATURES_CPU0_DBGEN	DEBUG_FEATURES - CPU0_DBGEN. Cortex Debug Features Control - CPU0 invasive debug control [0b01]Disables debug [0b10]Enables debug
DEBUG_FEATURES_CPU0_NIDEN	DEBUG_FEATURES - CPU0_NIDEN. Cortex Debug Features Control - CPU0 non-invasive debug control [0b01]Disables debug [0b10]Enables debug
DEBUG_FEATURES_DP_CPU0_DBGEN	DEBUG_FEATURES_DP - CPU0_DBGEN. Cortex Debug Features Control (Duplicate) - CPU0 invasive debug control [0b01]Disables debug [0b10]Enables debug
DEBUG_FEATURES_DP_CPU0_NIDEN	DEBUG_FEATURES_DP - CPU0_NIDEN. Cortex Debug Features Control (Duplicate) - CPU0 non-invasive debug control [0b01]Disables debug [0b10]Enables debug
SWD_ACCESS_CPU0_SEC_CODE	SWD_ACCESS_CPU0 - SEC_CODE. CPU0 Software Debug Access - CPU0 SWD-AP 0x12345678 [0b00010010001101000101011001111000]Value to write to enable CPU0 SWD access. Reading back register is read as 0xA. [0b00000000000000000000000000000000]CPU0 DAP is not allowed. Reading back register is read as 0x5.
DEBUG_AUTH_BEACON_BEACON	DEBUG_AUTH_BEACON - BEACON. Debug Authentication BEACON - Sets by the debug authentication code in ROM to pass the debug beacons (Credential Beacon and Authentication Beacon) to the application code.
JTAG_ID_JTAG_ID	JTAG_ID - JTAG_ID. JTAG Chip ID - Indicates the device ID
DEVICE_TYPE_DEVICE_TYPE	DEVICE_TYPE - DEVICE_TYPE. Device Type - Indicates DEVICE TYPE.
DEVICE_ID0_RAM_SIZE	DEVICE_ID0 - RAM_SIZE. Device ID - Chip RAM Size [0b0000]8KB. [0b0001]16KB. [0b0010]32KB. [0b0011]64KB. [0b0100]96KB. [0b0101]128KB. [0b0110]160KB. [0b0111]192KB. [0b1000]256KB. [0b1001]288KB. [0b1010]352KB. [0b1011]512KB.
DEVICE_ID0_FLASH_SIZE	DEVICE_ID0 - FLASH_SIZE. Device ID - Chip FLASH Size [0b0000]32KB. [0b0001]64KB. [0b0010]128KB. [0b0011]256KB. [0b0100]512KB. [0b0101]768KB. [0b0110]1MB. [0b0111]1.5MB. [0b1000]2MB.
DEVICE_ID0_SECURITY	DEVICE_ID0 - SECURITY. Device ID [0b1010]Non secure version. [0b0101]Secure version.
DIEID_MINOR_REVISION	DIEID - MINOR_REVISION. Chip Revision ID and Number - Chip minor revision
DIEID_MAJOR_REVISION	DIEID - MAJOR_REVISION. Chip Revision ID and Number - Chip major revision
DIEID_MCO_NUM_IN_DIE_ID	DIEID - MCO_NUM_IN_DIE_ID. Chip Revision ID and Number - Chip number

◆ Shift

enum struct mcxa153::chip::syscon::Shift : unsigned int

strong

MCXA153 SYSCON Bit Shift Positions Enumeration (SYSCON位元偏移位置枚舉)

This enumeration defines bit field shift positions for SYSCON registers, enabling precise bit manipulation and register field access operations. 這個枚舉定義了SYSCON寄存器的位元欄位偏移位置，支援精確的位元操作和寄存器欄位存取。

Register Categories (寄存器分類):

Memory Remapping Control (記憶體重映射控制) - REMAP_*
AHB Matrix Priority Control (AHB矩陣優先權控制) - AHBMATPRIO_*
System Tick Calibration (系統滴答校準) - CPU0NSTCKCAL_*
NMI Source Configuration (NMI源配置) - NMISRC_*
Clock Divider Control (時鐘分頻控制) - SLOWCLKDIV_*, AHBCLKDIV_*
Clock Configuration Lock (時鐘配置鎖定) - CLKUNLOCK_*
Non-Volatile Memory Control (非揮發性記憶體控制) - NVM_CTRL_*
CPU Status Monitoring (CPU狀態監控) - CPUSTAT_*
Cache Control (快取控制) - LPCAC_CTRL_*
PWM Submodule Control (PWM子模組控制) - PWM0SUBCTL_*, PWM1SUBCTL_*
Timer Global Start Control (定時器全域啟動控制) - CTIMERGLOBALSTARTEN_*
RAM Control (RAM控制) - RAM_CTRL_*
Gray-to-Binary Converter (格雷碼轉二進制轉換器) - GRAY_CODE_*, BINARY_CODE_*
Security and Debug Control (安全和除錯控制) - ROP_STATE_*, DEBUG_*
Memory Execute Permission (記憶體執行權限) - SRAM_XEN_*
Life Cycle Management (生命週期管理) - ELS_OTP_LC_STATE_*
Device Identification (裝置識別) - JTAG_ID_*, DEVICE_*, DIEID_*

Usage Pattern (使用模式):

// Set specific bit field
register_value |= (field_value << +Shift::REGISTER_FIELD);
 
// Get specific bit field
field_value = (register_value >> +Shift::REGISTER_FIELD) & field_mask;
 
// Clear and set bit field
register_value = (register_value & ~(mask << +Shift::REGISTER_FIELD)) |
                 (new_value << +Shift::REGISTER_FIELD);

註: 使用 +Shift::ENUM_VALUE 語法將枚舉轉換為數值進行位元操作

警告: 確保位元偏移值與對應寄存器規格匹配，錯誤偏移可能導致系統故障

注意: 部分寄存器具有鎖定位元，設定後需要系統重置才能修改

參閱: Register.h 對應的寄存器結構定義和詳細說明

列舉值
REMAP_CPU0_SBUS	REMAP - CPU0_SBUS. AHB Matrix Remap Control - RAMX0 address remap for CPU System bus [0b00]RAMX0: 0x04000000 - 0x04001fff [0b01]RAMX0: 0x2001e000 - 0x2001ffff(for 128KB RAM chip) / 0x20016000 - 0x20017fff(for 96KB RAM chip) / 0x2000e000 - 0x2000ffff(for 64KB RAM chip)
REMAP_DMA0	REMAP - DMA0. AHB Matrix Remap Control - RAMX0 address remap for DMA0 [0b00]RAMX0: 0x04000000 - 0x04001fff [0b01]RAMX0: same alias space as CPU0_SBUS
REMAP_USB0	REMAP - USB0. AHB Matrix Remap Control - RAMX0 address remap for USB0 [0b00]RAMX0: 0x04000000 - 0x04001fff [0b01]RAMX0: same alias space as CPU0_SBUS
REMAP_LOCK	REMAP - LOCK. AHB Matrix Remap Control - This 1-bit field provides a mechanism to limit writes to the this register to protect its contents. Once set, this bit remains asserted until a system reset. [0b0]This register is not locked and can be altered. [0b1]This register is locked and cannot be altered until a system reset.
AHBMATPRIO_CPU0_CBUS	AHBMATPRIO - CPU0_CBUS. AHB Matrix Priority Control - CPU0 C-AHB bus master priority level [0b00]level 0 [0b01]level 1 [0b10]level 2 [0b11]level 3
AHBMATPRIO_CPU0_SBUS	AHBMATPRIO - CPU0_SBUS. AHB Matrix Priority Control - CPU0 S-AHB bus master priority level [0b00]level 0 [0b01]level 1 [0b10]level 2 [0b11]level 3
AHBMATPRIO_DMA0	AHBMATPRIO - DMA0. AHB Matrix Priority Control - DMA0 controller bus master priority level [0b00]level 0 [0b01]level 1 [0b10]level 2 [0b11]level 3
AHBMATPRIO_USB_FS_ENET	AHBMATPRIO - USB_FS_ENET. AHB Matrix Priority Control - USB-FS bus master priority level [0b00]level 0 [0b01]level 1 [0b10]level 2 [0b11]level 3
CPU0NSTCKCAL_TENMS	CPU0NSTCKCAL - TENMS. Non-Secure CPU0 System Tick Calibration - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the value reads as zero, the calibration value is not known.
CPU0NSTCKCAL_SKEW	CPU0NSTCKCAL - SKEW. Non-Secure CPU0 System Tick Calibration - Indicates whether the TENMS value is exact. [0b0]TENMS value is exact [0b1]TENMS value is not exact or not given
CPU0NSTCKCAL_NOREF	CPU0NSTCKCAL - NOREF. Non-Secure CPU0 System Tick Calibration - Indicates whether the device provides a reference clock to the processor. [0b0]Reference clock is provided [0b1]No reference clock is provided
NMISRC_IRQCPU0	NMISRC - IRQCPU0. NMI Source Select - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for CPU0, if enabled by NMIENCPU0.
NMISRC_NMIENCPU0	NMISRC - NMIENCPU0. NMI Source Select - Enables the Non-Maskable Interrupt (NMI) source selected by IRQCPU0. [0b1][Enable. [0b0]Disable.
SLOWCLKDIV_RESET	SLOWCLKDIV - RESET. SLOW_CLK Clock Divider - Resets the divider counter [0b1]Divider is reset [0b0]Divider is not reset
SLOWCLKDIV_HALT	SLOWCLKDIV - HALT. SLOW_CLK Clock Divider - Halts the divider counter [0b1]Divider clock is stopped [0b0]Divider clock is running
SLOWCLKDIV_UNSTAB	SLOWCLKDIV - UNSTAB. SLOW_CLK Clock Divider - Divider status flag [0b1]Clock frequency is not stable [0b0]Divider clock is stable
AHBCLKDIV_DIV	AHBCLKDIV - DIV. System Clock Divider - Clock divider value
AHBCLKDIV_UNSTAB	AHBCLKDIV - UNSTAB. System Clock Divider - Divider status flag [0b1]Clock frequency is not stable [0b0]Divider clock is stable
CLKUNLOCK_UNLOCK	CLKUNLOCK - UNLOCK. Clock Configuration Unlock - Controls clock configuration registers access (for example, MRCC_xxx_CLKDIV, MRCC_xxx_CLKSEL, MRCC_GLB_xxx) [0b1]Freezes all clock configuration registers update. [0b0]Updates are allowed to all clock configuration registers
NVM_CTRL_DIS_FLASH_SPEC	NVM_CTRL - DIS_FLASH_SPEC. NVM Control - Flash speculation control [0b0]Enables flash speculation [0b1]Disables flash speculation
NVM_CTRL_DIS_DATA_SPEC	NVM_CTRL - DIS_DATA_SPEC. NVM Control -Flash data speculation control [0b0]Enables data speculation [0b1]Disables data speculation
NVM_CTRL_FLASH_STALL_EN	NVM_CTRL - FLASH_STALL_EN. NVM Control - FLASH stall on busy control [0b0]No stall on FLASH busy [0b1]Stall on FLASH busy
NVM_CTRL_DIS_MBECC_ERR_INST	NVM_CTRL - DIS_MBECC_ERR_INST. NVM Control [0b0]Enables bus error on multi-bit ECC error for instruction [0b1]Disables bus error on multi-bit ECC error for instruction
NVM_CTRL_DIS_MBECC_ERR_DATA	NVM_CTRL - DIS_MBECC_ERR_DATA. NVM Control [0b0]Enables bus error on multi-bit ECC error for data [0b1]Disables bus error on multi-bit ECC error for data
CPUSTAT_CPU0SLEEPING	CPUSTAT - CPU0SLEEPING. CPU Status - CPU0 sleeping state [0b1]CPU is sleeping [0b0]CPU is not sleeping
CPUSTAT_CPU0LOCKUP	CPUSTAT - CPU0LOCKUP. CPU Status - CPU0 lockup state [0b1]CPU is in lockup [0b0]CPU is not in lockup
LPCAC_CTRL_DIS_LPCAC	LPCAC_CTRL - DIS_LPCAC. LPCAC Control - Disables/enables the cache function. [0b0]Enabled [0b1]Disabled
LPCAC_CTRL_CLR_LPCAC	LPCAC_CTRL - CLR_LPCAC. LPCAC Control - Clears the cache function. [0b0]Unclears the cache [0b1]Clears the cache
LPCAC_CTRL_FRC_NO_ALLOC	LPCAC_CTRL - FRC_NO_ALLOC. LPCAC Control - Forces no allocation. [0b0]Forces allocation [0b1]Forces no allocation
LPCAC_CTRL_DIS_LPCAC_WTBF	LPCAC_CTRL - DIS_LPCAC_WTBF. LPCAC Control - Disable LPCAC Write Through Buffer. [0b1]Disables write through buffer [0b0]Enables write through buffer
LPCAC_CTRL_LIM_LPCAC_WTBF	LPCAC_CTRL - LIM_LPCAC_WTBF. LPCAC Control - Limit LPCAC Write Through Buffer. [0b1]Write buffer enabled when transaction is cacheable and bufferable [0b0]Write buffer enabled when transaction is bufferable.
LPCAC_CTRL_LPCAC_XOM	LPCAC_CTRL - LPCAC_XOM. LPCAC Control - LPCAC XOM(eXecute-Only-Memory) attribute control [0b1]Enabled. [0b0]Disabled.
LPCAC_CTRL_LPCAC_MEM_REQ	LPCAC_CTRL - LPCAC_MEM_REQ. LPCAC Control - Request LPCAC memories. [0b1]Configure shared memories RAMX1 as LPCAC memories, write one lock until a system reset. [0b0]Configure shared memories RAMX1 as general memories.
PWM0SUBCTL_CLK0_EN	PWM0SUBCTL - CLK0_EN. PWM0 Submodule Control - Enables PWM0 SUB Clock0 [0b1]Enable [0b0]Disable
PWM0SUBCTL_CLK1_EN	PWM0SUBCTL - CLK1_EN. PWM0 Submodule Control - Enables PWM0 SUB Clock1 [0b1]Enable [0b0]Disable
PWM0SUBCTL_CLK2_EN	PWM0SUBCTL - CLK2_EN. PWM0 Submodule Control - Enables PWM0 SUB Clock2 [0b1]Enable [0b0]Disable
PWM0SUBCTL_CLK3_EN	PWM0SUBCTL - CLK3_EN. PWM0 Submodule Control - Enables PWM0 SUB Clock3 [0b1]Enable [0b0]Disable
PWM1SUBCTL_CLK0_EN	PWM1SUBCTL - CLK0_EN. PWM1 Submodule Control - Enables PWM1 SUB Clock0 [0b1]Enable [0b0]Disable
PWM1SUBCTL_CLK1_EN	PWM1SUBCTL - CLK1_EN. PWM1 Submodule Control - Enables PWM1 SUB Clock1 [0b1]Enable [0b0]Disable
PWM1SUBCTL_CLK2_EN	PWM1SUBCTL - CLK2_EN. PWM1 Submodule Control - Enables PWM1 SUB Clock2 [0b1]Enable [0b0]Disable
PWM1SUBCTL_CLK3_EN	PWM1SUBCTL - CLK3_EN. PWM1 Submodule Control - Enables PWM1 SUB Clock3 [0b1]Enable [0b0]Disable
CTIMERGLOBALSTARTEN_CTIMER0_CLK_EN	CTIMERGLOBALSTARTEN - CTIMER0_CLK_EN. CTIMER Global Start Enable - Enables the CTIMER0 function clock [0b1]Enable [0b0]Disable
CTIMERGLOBALSTARTEN_CTIMER1_CLK_EN	CTIMERGLOBALSTARTEN - CTIMER1_CLK_EN. CTIMER Global Start Enable - Enables the CTIMER1 function clock [0b1]Enable [0b0]Disable
CTIMERGLOBALSTARTEN_CTIMER2_CLK_EN	CTIMERGLOBALSTARTEN - CTIMER2_CLK_EN. CTIMER Global Start Enable - Enables the CTIMER2 function clock [0b1]Enable [0b0]Disable
CTIMERGLOBALSTARTEN_CTIMER3_CLK_EN	CTIMERGLOBALSTARTEN - CTIMER3_CLK_EN. CTIMER Global Start Enable - Enables the CTIMER3 function clock [0b1]Enable [0b0]Disable
CTIMERGLOBALSTARTEN_CTIMER4_CLK_EN	CTIMERGLOBALSTARTEN - CTIMER4_CLK_EN. CTIMER Global Start Enable - Enables the CTIMER4 function clock [0b1]Enable [0b0]Disable
RAM_CTRL_RAMA_ECC_ENABLE	RAM_CTRL - RAMA_ECC_ENABLE. RAM Control - RAMA0 ECC enable [0b1]ECC is enabled [0b0]ECC is disabled
RAM_CTRL_RAMA_CG_OVERRIDE	RAM_CTRL - RAMA_CG_OVERRIDE. RAM Control - RAMA bank clock gating control, only avaiable when RAMA_ECC_ENABLE = 0. [0b1]Auto clock gating feature is disabled [0b0]Memory bank clock is gated automatically if no access more than 16 clock cycles
RAM_CTRL_RAMX_CG_OVERRIDE	RAM_CTRL - RAMX_CG_OVERRIDE. RAM Control - RAMX bank clock gating control [0b1]Auto clock gating feature is disabled [0b0]Memory bank clock is gated automatically if no access more than 16 clock cycles
RAM_CTRL_RAMB_CG_OVERRIDE	RAM_CTRL - RAMB_CG_OVERRIDE. RAM Control - RAMB bank clock gating control [0b1]Auto clock gating feature is disabled [0b0]Memory bank clock is gated automatically if no access more than 16 clock cycles
GRAY_CODE_LSB_code_gray_31_0	GRAY_CODE_LSB - code_gray_31_0. Gray to Binary Converter Gray Code [31:0] - Gray code [31:0]
GRAY_CODE_MSB_code_gray_41_32	GRAY_CODE_MSB - code_gray_41_32. Gray to Binary Converter Gray Code [41:32] - Gray code [41:32]
BINARY_CODE_LSB_code_bin_31_0	BINARY_CODE_LSB - code_bin_31_0. Gray to Binary Converter Binary Code [31:0] - Binary code [31:0]
BINARY_CODE_MSB_code_bin_41_32	BINARY_CODE_MSB - code_bin_41_32. Gray to Binary Converter Binary Code [41:32] - Binary code [41:32]
ROP_STATE_ROP_STATE	ROP_STATE - ROP_STATE. ROP State Register - ROP state
OVP_PAD_STATE_OVP_PAD_STATE	OVP_PAD_STATE - OVP_PAD_STATE. OVP_PAD_STATE - OVP_PAD_STATE
PROBE_STATE_PROBE_STATE	PROBE_STATE - PROBE_STATE. PROBE_STATE - PROBE_STATE
FT_STATE_A_FT_STATE_A	FT_STATE_A - FT_STATE_A. FT_STATE_A - FT_STATE_A
FT_STATE_B_FT_STATE_B	FT_STATE_B - FT_STATE_B. FT_STATE_B - FT_STATE_B
SRAM_XEN_RAMX0_XEN	SRAM_XEN - RAMX0_XEN. RAM XEN Control - RAMX0 Execute permission control. [0b1]Execute permission is enabled, R/W/X are enabled. [0b0]Execute permission is disabled, R/W are enabled.
SRAM_XEN_RAMX1_XEN	SRAM_XEN - RAMX1_XEN. RAM XEN Control - RAMX1 Execute permission control. [0b1]Execute permission is enabled, R/W/X are enabled. [0b0]Execute permission is disabled, R/W are enabled.
SRAM_XEN_RAMA0_XEN	SRAM_XEN - RAMA0_XEN. RAM XEN Control - RAMA0 Execute permission control. [0b1]Execute permission is enabled, R/W/X are enabled. [0b0]Execute permission is disabled, R/W are enabled.
SRAM_XEN_RAMA1_XEN	SRAM_XEN - RAMA1_XEN. RAM XEN Control - RAMAx (excepts RAMA0) Execute permission control. [0b1]Execute permission is enabled, R/W/X are enabled. [0b0]Execute permission is disabled, R/W are enabled.
SRAM_XEN_RAMB_XEN	SRAM_XEN - RAMB_XEN. RAM XEN Control - RAMBx Execute permission control. [0b1]Execute permission is enabled, R/W/X are enabled. [0b0]Execute permission is disabled, R/W are enabled.
SRAM_XEN_LOCK	SRAM_XEN - LOCK. RAM XEN Control - This 1-bit field provides a mechanism to limit writes to the this register (and SRAM_XEN_DP) to protect its contents. Once set, this bit remains asserted until a system reset. [0b0]This register is not locked and can be altered. [0b1]This register is locked and cannot be altered.
SRAM_XEN_DP_RAMX0_XEN	SRAM_XEN_DP - RAMX0_XEN. RAM XEN Control (Duplicate) - Refer to SRAM_XEN for more details.
SRAM_XEN_DP_RAMX1_XEN	SRAM_XEN_DP - RAMX1_XEN. RAM XEN Control (Duplicate) - Refer to SRAM_XEN for more details.
SRAM_XEN_DP_RAMA0_XEN	SRAM_XEN_DP - RAMA0_XEN. RAM XEN Control (Duplicate) - Refer to SRAM_XEN for more details.
SRAM_XEN_DP_RAMA1_XEN	SRAM_XEN_DP - RAMA1_XEN. RAM XEN Control (Duplicate) - Refer to SRAM_XEN for more details.
SRAM_XEN_DP_RAMB_XEN	SRAM_XEN_DP - RAMB_XEN. RAM XEN Control (Duplicate) - Refer to SRAM_XEN for more details.
ELS_OTP_LC_STATE_OTP_LC_STATE	ELS_OTP_LC_STATE - OTP_LC_STATE. Life Cycle State Register - OTP life cycle state
ELS_OTP_LC_STATE_DP_OTP_LC_STATE_DP	ELS_OTP_LC_STATE_DP - OTP_LC_STATE_DP. Life Cycle State Register (Duplicate) - OTP life cycle state
DEBUG_LOCK_EN_LOCK_ALL	DEBUG_LOCK_EN - LOCK_ALL. Control Write Access to Security - Controls write access to the security registers [0b1010]Enables write access to all registers [0b0000]Any other value than b1010: disables write access to all registers
DEBUG_FEATURES_CPU0_DBGEN	DEBUG_FEATURES - CPU0_DBGEN. Cortex Debug Features Control - CPU0 invasive debug control [0b01]Disables debug [0b10]Enables debug
DEBUG_FEATURES_CPU0_NIDEN	DEBUG_FEATURES - CPU0_NIDEN. Cortex Debug Features Control - CPU0 non-invasive debug control [0b01]Disables debug [0b10]Enables debug
DEBUG_FEATURES_DP_CPU0_DBGEN	DEBUG_FEATURES_DP - CPU0_DBGEN. Cortex Debug Features Control (Duplicate) - CPU0 invasive debug control [0b01]Disables debug [0b10]Enables debug
DEBUG_FEATURES_DP_CPU0_NIDEN	DEBUG_FEATURES_DP - CPU0_NIDEN. Cortex Debug Features Control (Duplicate) - CPU0 non-invasive debug control [0b01]Disables debug [0b10]Enables debug
SWD_ACCESS_CPU0_SEC_CODE	SWD_ACCESS_CPU0 - SEC_CODE. CPU0 Software Debug Access - CPU0 SWD-AP: 0x12345678 [0b00010010001101000101011001111000]Value to write to enable CPU0 SWD access. Reading back register is read as 0xA. [0b00000000000000000000000000000000]CPU0 DAP is not allowed. Reading back register is read as 0x5.
DEBUG_AUTH_BEACON_BEACON	DEBUG_AUTH_BEACON - BEACON. Debug Authentication BEACON - Sets by the debug authentication code in ROM to pass the debug beacons (Credential Beacon and Authentication Beacon) to the application code.
JTAG_ID_JTAG_ID	JTAG_ID - JTAG_ID. JTAG Chip ID - Indicates the device ID
DEVICE_TYPE_DEVICE_TYPE	DEVICE_TYPE - DEVICE_TYPE. Device Type - Indicates DEVICE TYPE.
DEVICE_ID0_RAM_SIZE	DEVICE_ID0 - RAM_SIZE. Device ID - Chip RAM Size [0b0000]8KB. [0b0001]16KB. [0b0010]32KB. [0b0011]64KB. [0b0100]96KB. [0b0101]128KB. [0b0110]160KB. [0b0111]192KB. [0b1000]256KB. [0b1001]288KB. [0b1010]352KB. [0b1011]512KB.
DEVICE_ID0_FLASH_SIZE	DEVICE_ID0 - FLASH_SIZE. Device ID - Chip FLASH Size [0b0000]32KB. [0b0001]64KB. [0b0010]128KB. [0b0011]256KB. [0b0100]512KB. [0b0101]768KB. [0b0110]1MB. [0b0111]1.5MB. [0b1000]2MB.
DEVICE_ID0_SECURITY	DEVICE_ID0 - SECURITY. Device ID [0b1010]Non secure version. [0b0101]Secure version.
DIEID_MINOR_REVISION	DIEID - MINOR_REVISION. Chip Revision ID and Number - Chip minor revision
DIEID_MAJOR_REVISION	DIEID - MAJOR_REVISION. Chip Revision ID and Number - Chip major revision
DIEID_MCO_NUM_IN_DIE_ID	DIEID - MCO_NUM_IN_DIE_ID. Chip Revision ID and Number - Chip number

函式說明文件

◆ operator+() [1/2]

unsigned int mcxa153::chip::syscon::operator+ ( Count e )

constexpr

Operator Overload - Convert Count enum to unsigned int.

Converts Count enumeration value to unsigned integer for easy numeric operations and array indexing. Useful for loop iterations and resource allocation based on hardware resource counts.

將Count列舉值轉換為無號整數，便於數值運算和陣列索引操作

參數

e	Count enumeration value 計數列舉值

傳回值: constexpr unsigned int Unsigned integer representation 無號整數表示

◆ operator+() [2/2]

unsigned int mcxa153::chip::syscon::operator+ ( Mask e )

constexpr

Operator Overload - Convert Mask enum to unsigned int.

Converts Mask enumeration value to unsigned integer for easy bitwise operations. Useful for manipulating SYSCON register fields in conditional statements.

將Mask列舉值轉換為無號整數，便於位元操作

參數

e	Mask enumeration value 列舉值

傳回值: constexpr unsigned int Unsigned integer representation 無號整數表示

命名空間(Namespaces)

複合項目

列舉型態

函式

變數

詳細描述

列舉型態說明文件

◆ Count

◆ Mask

◆ Shift

函式說明文件

◆ operator+() [1/2]

◆ operator+() [2/2]