SPC.h

 
#ifndef CHIP_2E3411A1_6370_44BE_84E2_32D911539D8F
#define CHIP_2E3411A1_6370_44BE_84E2_32D911539D8F
 
/* ***************************************************************************************
 * Include
 */
 
//----------------------------------------------------------------------------------------
#include "mframe.h"
 
//----------------------------------------------------------------------------------------
#include "./ActiveModeCoreLdoOption.h"
#include "./ActiveModeRegulatorsConfig.h"
#include "./AnalogModuleControl.h"
#include "./BandgapMode.h"
#include "./CoreLdoDriveStrength.h"
#include "./CoreLdoVoltageLevel.h"
#include "./CoreVoltageDetectConfig.h"
#include "./Count.h"
#include "./LowPowerModeCoreLdoOption.h"
#include "./LowPowerModeRegulatorsConfig.h"
#include "./LowPowerRequestConfig.h"
#include "./LowPowerRequestOutputOverride.h"
#include "./LowPowerRequestPinPolarity.h"
#include "./LowVoltageLevelSelect.h"
#include "./Mask.h"
#include "./PowerDomainID.h"
#include "./PowerDomainLowPowerMode.h"
#include "./PowerDomains.h"
#include "./Register.h"
#include "./Shift.h"
#include "./SramOperateVoltage.h"
#include "./SramVoltageConfig.h"
#include "./Status.h"
#include "./SystemVoltageDetectConfig.h"
#include "./VoltageDetectFlag.h"
#include "./VoltageDetectOption.h"
 
/* ***************************************************************************************
 * Namespace
 */
namespace chip::spc {
  class SPC;
  extern Register& SPC0;
}  // namespace chip::spc
 
/* ***************************************************************************************
 * Class/Interface/Struct/Enum
 */
class chip::spc::SPC final : public mframe::lang::Object {
  /* *************************************************************************************
   * Variable
   */
 
  /* *************************************************************************************
   * Abstract Method
   */
 
  /* *************************************************************************************
   * Construct Method
   */
 private:
  SPC(void);
 
 public:
  virtual ~SPC(void) override;
 
  /* *************************************************************************************
   * Operator Method
   */
 
  /* *************************************************************************************
   * Public Method <Override>
   */
 
  /* *************************************************************************************
   * Public Method
   */
 
  /* *************************************************************************************
   * Protected Method
   */
 
  /* *************************************************************************************
   * Private Method
   */
 
  /* *************************************************************************************
   * Static Variable
   */
 
  /* *************************************************************************************
   * Static Method
   */
 public:
  static uint8 getPeriphIOIsolationStatus(Register& base);
 
  static inline void clearPeriphIOIsolationFlag(Register& base) {
    base.sc |= +chip::spc::Mask::SC_ISO_CLR;
  }
 
  static inline bool getBusyStatusFlag(Register& base) {
    return ((base.sc & +chip::spc::Mask::SC_BUSY) != 0UL);
  }
 
  static inline bool checkLowPowerReqest(Register& base) {
    return ((base.sc & +chip::spc::Mask::SC_SPC_LP_REQ) == +chip::spc::Mask::SC_SPC_LP_REQ);
  }
 
  static inline void clearLowPowerRequest(Register& base) {
    base.sc |= +chip::spc::Mask::SC_SPC_LP_REQ;
  }
 
  static inline bool checkSwitchState(Register& base) {
    return ((base.sc & +chip::spc::Mask::SC_SWITCH_STATE) != 0UL);
  }
 
  static PowerDomainLowPowerMode getPowerDomainLowPowerMode(Register& base, PowerDomainID powerDomainId);
 
  static inline bool checkPowerDomainLowPowerRequest(Register& base, PowerDomainID powerDomainId) {
    return ((base.pd_status[+powerDomainId] & +chip::spc::Mask::PD_STATUS_PWR_REQ_STATUS) ==
            +chip::spc::Mask::PD_STATUS_PWR_REQ_STATUS);
  }
 
  static inline void clearPowerDomainLowPowerRequestFlag(Register& base, PowerDomainID powerDomainId) {
    base.pd_status[+powerDomainId] |= +chip::spc::Mask::PD_STATUS_PD_LP_REQ;
  }
 
  static inline void trimSRAMLdoRefVoltage(Register& base, uint8 trimValue) {
    base.sramretldo_reftrim =
        ((base.sramretldo_reftrim & ~+chip::spc::Mask::SRAMRETLDO_REFTRIM_REFTRIM) | SPC::SRAMRETLDO_REFTRIM_REFTRIM(trimValue));
  }
 
  static inline void enableSRAMLdo(Register& base, bool enable) {
    if (enable) {
      base.sramretldo_cntrl |= +chip::spc::Mask::SRAMRETLDO_CNTRL_SRAMLDO_ON;
    } else {
      base.sramretldo_cntrl &= ~+chip::spc::Mask::SRAMRETLDO_CNTRL_SRAMLDO_ON;
    }
  }
 
  static inline void retainSRAMArray(Register& base, uint8 mask) {
    base.sramretldo_cntrl |= SPC::SRAMRETLDO_CNTRL_SRAM_RET_EN(mask);
  }
 
  static void setLowPowerRequestConfig(Register& base, const LowPowerRequestConfig& config);
 
  static inline void enableIntegratedPowerSwitchManually(Register& base, bool enable) {
    if (enable) {
      base.cfg |= (+Mask::CFG_INTG_PWSWTCH_SLEEP_ACTIVE_EN | +Mask::CFG_INTG_PWSWTCH_WKUP_ACTIVE_EN);
    } else {
      base.cfg &= ~(+Mask::CFG_INTG_PWSWTCH_SLEEP_ACTIVE_EN | +Mask::CFG_INTG_PWSWTCH_WKUP_ACTIVE_EN);
    }
  }
 
  static inline void enableIntegratedPowerSwitchAutomatically(Register& base, bool sleepGate, bool wakeupUngate) {
    uint32 tmp32 = ((base.cfg) & ~(+Mask::CFG_INTG_PWSWTCH_SLEEP_EN | +Mask::CFG_INTG_PWSWTCH_WKUP_EN));
 
    tmp32 |= SPC::CFG_INTG_PWSWTCH_SLEEP_EN(sleepGate) | SPC::CFG_INTG_PWSWTCH_WKUP_EN(wakeupUngate);
 
    base.cfg = tmp32;
  }
 
  static void setSRAMOperateVoltage(Register& base, const SramVoltageConfig& config);
 
  static inline BandgapMode getActiveModeBandgapMode(Register& base) {
    return static_cast<chip::spc::BandgapMode>(
        (base.active_cfg & +Mask::ACTIVE_CFG_BGMODE) >> +Shift::ACTIVE_CFG_BGMODE);
  }
 
  static inline uint32 getActiveModeVoltageDetectStatus(Register& base) {
    uint32 state;
    state = base.active_cfg &
        (+Mask::ACTIVE_CFG_SYS_HVDE |
         +Mask::ACTIVE_CFG_SYS_LVDE |
         +Mask::ACTIVE_CFG_CORE_LVDE);
    return state;
  }
 
  static chip::spc::Status setActiveModeBandgapModeConfig(Register& base, chip::spc::BandgapMode mode);
 
  static inline void setActiveModeVoltageTrimDelay(Register& base, uint16 delay) {
    base.active_vdelay = SPC::ACTIVE_VDELAY_ACTIVE_VDELAY(delay);
  }
 
  static chip::spc::Status setActiveModeRegulatorsConfig(Register& base, const ActiveModeRegulatorsConfig& config);
 
  static inline void enableActiveModeAnalogModules(Register& base, uint32 maskValue) {
    base.active_cfg1 |= SPC::ACTIVE_CFG1_SOC_CNTRL(maskValue);
  }
 
  static inline void disableActiveModeAnalogModules(Register& base, uint32 maskValue) {
    base.active_cfg1 &= ~SPC::ACTIVE_CFG1_SOC_CNTRL(maskValue);
  }
 
  static inline uint32 getActiveModeEnabledAnalogModules(Register& base) {
    return base.active_cfg1;
  }
 
  static inline chip::spc::BandgapMode getLowPowerModeBandgapMode(Register& base) {
    return static_cast<chip::spc::BandgapMode>((base.lp_cfg & +Mask::LP_CFG_BGMODE) >> +Shift::LP_CFG_BGMODE);
  }
 
  static inline uint32 getLowPowerModeVoltageDetectStatus(Register& base) {
    uint32 state;
    state = base.lp_cfg & (+Mask::LP_CFG_SYS_HVDE | +Mask::LP_CFG_SYS_LVDE | +Mask::LP_CFG_CORE_LVDE);
    return state;
  }
 
  static inline void enableLowPowerModeLowPowerIREF(Register& base, bool enable) {
    if (enable) {
      base.lp_cfg |= +Mask::LP_CFG_LP_IREFEN;
    } else {
      base.lp_cfg &= ~+Mask::LP_CFG_LP_IREFEN;
    }
  }
 
  static chip::spc::Status setLowPowerModeBandgapmodeConfig(Register& base, chip::spc::BandgapMode mode);
 
  static inline void enableSRAMLdOLowPowerModeIREF(Register& base, bool enable) {
    if (enable) {
      base.lp_cfg |= +Mask::LP_CFG_SRAMLDO_DPD_ON;
    } else {
      base.lp_cfg &= ~+Mask::LP_CFG_SRAMLDO_DPD_ON;
    }
  }
 
  static inline void setLowPowerWakeUpDelay(Register& base, uint16 delay) {
    base.lpwkup_delay = SPC::LPWKUP_DELAY_LPWKUP_DELAY(delay);
  }
 
  static chip::spc::Status setLowPowerModeRegulatorsConfig(Register& base, const LowPowerModeRegulatorsConfig* config);
 
  static inline void enableLowPowerModeAnalogModules(Register& base, uint32 maskValue) {
    base.lp_cfg1 |= SPC::LP_CFG1_SOC_CNTRL(maskValue);
  }
 
  static inline void disableLowPowerModeAnalogModules(Register& base, uint32 maskValue) {
    base.lp_cfg1 &= ~SPC::LP_CFG1_SOC_CNTRL(maskValue);
  }
 
  static inline uint32 getLowPowerModeEnabledAnalogModules(Register& base) {
    return base.lp_cfg1;
  }
 
  static inline uint8 getVoltageDetectStatusFlag(Register& base) {
    return static_cast<uint8>(base.vd_stat);
  }
 
  static inline void clearVoltageDetectStatusFlag(Register& base, uint8 mask) {
    base.vd_stat |= mask;
  }
 
  static void setCoreVoltageDetectConfig(Register& base, const CoreVoltageDetectConfig& config);
 
  static inline void lockCoreVoltageDetectResetSetting(Register& base) {
    base.vd_core_cfg |= +Mask::VD_CORE_CFG_LOCK;
  }
 
  static inline void unlockCoreVoltageDetectResetSetting(Register& base) {
    base.vd_core_cfg &= ~+Mask::VD_CORE_CFG_LOCK;
  }
 
  static chip::spc::Status enableActiveModeCoreLowVoltageDetect(Register& base, bool enable);
 
  static chip::spc::Status enableLowPowerModeCoreLowVoltageDetect(Register& base, bool enable);
 
  static void setSystemVDDLowVoltageLevel(Register& base, LowVoltageLevelSelect level);
 
  static void setSystemVoltageDetectConfig(Register& base, const SystemVoltageDetectConfig& config);
 
  static inline void lockSystemVoltageDetectResetSetting(Register& base) {
    base.vd_sys_cfg |= +Mask::VD_SYS_CFG_LOCK;
  }
 
  static inline void unlockSystemVoltageDetectResetSetting(Register& base) {
    base.vd_sys_cfg &= ~+Mask::VD_SYS_CFG_LOCK;
  }
 
  static chip::spc::Status enableActiveModeSystemHighVoltageDetect(Register& base, bool enable);
 
  static chip::spc::Status enableActiveModeSystemLowVoltageDetect(Register& base, bool enable);
 
  static chip::spc::Status enableLowPowerModeSystemHighVoltageDetect(Register& base, bool enable);
 
  static chip::spc::Status enableLowPowerModeSystemLowVoltageDetect(Register& base, bool enable);
 
  static void setExternalVoltageDomainsConfig(Register& base, uint8 lowPowerIsoMask, uint8 IsoMask);
 
  static inline uint8 getExternalDomainsStatus(Register& base) {
    return static_cast<uint8>(base.evd_cfg >> +Shift::EVD_CFG_REG_EVDSTAT);
  }
 
  static chip::spc::Status setActiveModeCoreLDORegulatorConfig(Register& base, const ActiveModeCoreLdoOption& option);
 
  static chip::spc::Status setActiveModeCoreLDORegulatorVoltageLevel(Register& base, CoreLdoVoltageLevel voltageLevel);
 
  static inline CoreLdoVoltageLevel getActiveModeCoreLDOVDDVoltageLevel(Register& base) {
    return static_cast<CoreLdoVoltageLevel>((base.active_cfg & +Mask::ACTIVE_CFG_CORELDO_VDD_LVL) >>
                                            +Shift::ACTIVE_CFG_CORELDO_VDD_LVL);
  }
 
  static chip::spc::Status setActiveModeCoreLDORegulatorDriveStrength(Register& base, CoreLdoDriveStrength driveStrength);
 
  static inline CoreLdoDriveStrength getActiveModeCoreLDODriveStrength(Register& base) {
    return static_cast<CoreLdoDriveStrength>((base.active_cfg & +Mask::ACTIVE_CFG_CORELDO_VDD_DS) >>
                                             +Shift::ACTIVE_CFG_CORELDO_VDD_DS);
  }
 
  static chip::spc::Status setLowPowerModeCoreLDORegulatorConfig(Register& base, const LowPowerModeCoreLdoOption& option);
 
  static chip::spc::Status setLowPowerModeCoreLDORegulatorVoltageLevel(Register& base, CoreLdoVoltageLevel voltageLevel);
 
  static inline CoreLdoVoltageLevel getLowPowerCoreLDOVDDVoltageLevel(Register& base) {
    return static_cast<CoreLdoVoltageLevel>(((base.lp_cfg & +Mask::LP_CFG_CORELDO_VDD_LVL) >>
                                             +Mask::LP_CFG_CORELDO_VDD_LVL));
  }
 
  static chip::spc::Status setLowPowerModeCoreLDORegulatorDriveStrength(Register& base, CoreLdoDriveStrength driveStrength);
 
  static inline CoreLdoDriveStrength getLowPowerCoreLDOVDDDriveStrength(Register& base) {
    return static_cast<CoreLdoDriveStrength>((base.lp_cfg & +Mask::LP_CFG_CORELDO_VDD_DS) >>
                                             +Shift::LP_CFG_CORELDO_VDD_DS);
  }
 
  static inline constexpr uint32 VERID_FEATURE(uint32 value) {
    return ((value << +chip::spc::Shift::VERID_FEATURE) &
            +chip::spc::Mask::VERID_FEATURE);
  }
 
  static inline constexpr uint32 VERID_MINOR(uint32 value) {
    return ((value << +chip::spc::Shift::VERID_MINOR) &
            +chip::spc::Mask::VERID_MINOR);
  }
 
  static inline constexpr uint32 VERID_MAJOR(uint32 value) {
    return ((value << +chip::spc::Shift::VERID_MAJOR) &
            +chip::spc::Mask::VERID_MAJOR);
  }
 
  static inline constexpr uint32 SC_BUSY(uint32 value) {
    return ((value << +chip::spc::Shift::SC_BUSY) &
            +chip::spc::Mask::SC_BUSY);
  }
 
  static inline constexpr uint32 SC_SPC_LP_REQ(uint32 value) {
    return ((value << +chip::spc::Shift::SC_SPC_LP_REQ) &
            +chip::spc::Mask::SC_SPC_LP_REQ);
  }
 
  static inline constexpr uint32 SC_SPC_LP_MODE(uint32 value) {
    return ((value << +chip::spc::Shift::SC_SPC_LP_MODE) &
            +chip::spc::Mask::SC_SPC_LP_MODE);
  }
 
  static inline constexpr uint32 SC_ISO_CLR(uint32 value) {
    return ((value << +chip::spc::Shift::SC_ISO_CLR) &
            +chip::spc::Mask::SC_ISO_CLR);
  }
 
  static inline constexpr uint32 SC_SWITCH_STATE(uint32 value) {
    return ((value << +chip::spc::Shift::SC_SWITCH_STATE) &
            +chip::spc::Mask::SC_SWITCH_STATE);
  }
 
  static inline constexpr uint32 LPREQ_CFG_LPREQOE(uint32 value) {
    return ((value << +chip::spc::Shift::LPREQ_CFG_LPREQOE) &
            +chip::spc::Mask::LPREQ_CFG_LPREQOE);
  }
 
  static inline constexpr uint32 LPREQ_CFG_LPREQPOL(uint32 value) {
    return ((value << +chip::spc::Shift::LPREQ_CFG_LPREQPOL) &
            +chip::spc::Mask::LPREQ_CFG_LPREQPOL);
  }
 
  static inline constexpr uint32 LPREQ_CFG_LPREQOV(uint32 value) {
    return ((value << +chip::spc::Shift::LPREQ_CFG_LPREQOV) &
            +chip::spc::Mask::LPREQ_CFG_LPREQOV);
  }
 
  static inline constexpr uint32 CFG_INTG_PWSWTCH_SLEEP_EN(uint32 value) {
    return ((value << +chip::spc::Shift::CFG_INTG_PWSWTCH_SLEEP_EN) &
            +chip::spc::Mask::CFG_INTG_PWSWTCH_SLEEP_EN);
  }
 
  static inline constexpr uint32 CFG_INTG_PWSWTCH_WKUP_EN(uint32 value) {
    return ((value << +chip::spc::Shift::CFG_INTG_PWSWTCH_WKUP_EN) &
            +chip::spc::Mask::CFG_INTG_PWSWTCH_WKUP_EN);
  }
 
  static inline constexpr uint32 CFG_INTG_PWSWTCH_SLEEP_ACTIVE_EN(uint32 value) {
    return ((value << +chip::spc::Shift::CFG_INTG_PWSWTCH_SLEEP_ACTIVE_EN) &
            +chip::spc::Mask::CFG_INTG_PWSWTCH_SLEEP_ACTIVE_EN);
  }
 
  static inline constexpr uint32 CFG_INTG_PWSWTCH_WKUP_ACTIVE_EN(uint32 value) {
    return ((value << +chip::spc::Shift::CFG_INTG_PWSWTCH_WKUP_ACTIVE_EN) &
            +chip::spc::Mask::CFG_INTG_PWSWTCH_WKUP_ACTIVE_EN);
  }
 
  static inline constexpr uint32 PD_STATUS_PWR_REQ_STATUS(uint32 value) {
    return ((value << +chip::spc::Shift::PD_STATUS_PWR_REQ_STATUS) &
            +chip::spc::Mask::PD_STATUS_PWR_REQ_STATUS);
  }
 
  static inline constexpr uint32 PD_STATUS_PD_LP_REQ(uint32 value) {
    return ((value << +chip::spc::Shift::PD_STATUS_PD_LP_REQ) &
            +chip::spc::Mask::PD_STATUS_PD_LP_REQ);
  }
 
  static inline constexpr uint32 PD_STATUS_LP_MODE(uint32 value) {
    return ((value << +chip::spc::Shift::PD_STATUS_LP_MODE) &
            +chip::spc::Mask::PD_STATUS_LP_MODE);
  }
 
  static inline constexpr uint32 SRAMCTL_VSM(uint32 value) {
    return ((value << +chip::spc::Shift::SRAMCTL_VSM) &
            +chip::spc::Mask::SRAMCTL_VSM);
  }
 
  static inline constexpr uint32 SRAMCTL_REQ(uint32 value) {
    return ((value << +chip::spc::Shift::SRAMCTL_REQ) &
            +chip::spc::Mask::SRAMCTL_REQ);
  }
 
  static inline constexpr uint32 SRAMCTL_ACK(uint32 value) {
    return ((value << +chip::spc::Shift::SRAMCTL_ACK) &
            +chip::spc::Mask::SRAMCTL_ACK);
  }
 
  static inline constexpr uint32 SRAMRETLDO_REFTRIM_REFTRIM(uint32 value) {
    return ((value << +chip::spc::Shift::SRAMRETLDO_REFTRIM_REFTRIM) &
            +chip::spc::Mask::SRAMRETLDO_REFTRIM_REFTRIM);
  }
 
  static inline constexpr uint32 SRAMRETLDO_CNTRL_SRAMLDO_ON(uint32 value) {
    return ((value << +chip::spc::Shift::SRAMRETLDO_CNTRL_SRAMLDO_ON) &
            +chip::spc::Mask::SRAMRETLDO_CNTRL_SRAMLDO_ON);
  }
 
  static inline constexpr uint32 SRAMRETLDO_CNTRL_SRAM_RET_EN(uint32 value) {
    return ((value << +chip::spc::Shift::SRAMRETLDO_CNTRL_SRAM_RET_EN) &
            +chip::spc::Mask::SRAMRETLDO_CNTRL_SRAM_RET_EN);
  }
 
  static inline constexpr uint32 ACTIVE_CFG_CORELDO_VDD_DS(uint32 value) {
    return ((value << +chip::spc::Shift::ACTIVE_CFG_CORELDO_VDD_DS) &
            +chip::spc::Mask::ACTIVE_CFG_CORELDO_VDD_DS);
  }
 
  static inline constexpr uint32 ACTIVE_CFG_CORELDO_VDD_LVL(uint32 value) {
    return ((value << +chip::spc::Shift::ACTIVE_CFG_CORELDO_VDD_LVL) &
            +chip::spc::Mask::ACTIVE_CFG_CORELDO_VDD_LVL);
  }
 
  static inline constexpr uint32 ACTIVE_CFG_BGMODE(uint32 value) {
    return ((value << +chip::spc::Shift::ACTIVE_CFG_BGMODE) &
            +chip::spc::Mask::ACTIVE_CFG_BGMODE);
  }
 
  static inline constexpr uint32 ACTIVE_CFG_VDD_VD_DISABLE(uint32 value) {
    return ((value << +chip::spc::Shift::ACTIVE_CFG_VDD_VD_DISABLE) &
            +chip::spc::Mask::ACTIVE_CFG_VDD_VD_DISABLE);
  }
 
  static inline constexpr uint32 ACTIVE_CFG_CORE_LVDE(uint32 value) {
    return ((value << +chip::spc::Shift::ACTIVE_CFG_CORE_LVDE) &
            +chip::spc::Mask::ACTIVE_CFG_CORE_LVDE);
  }
 
  static inline constexpr uint32 ACTIVE_CFG_SYS_LVDE(uint32 value) {
    return ((value << +chip::spc::Shift::ACTIVE_CFG_SYS_LVDE) &
            +chip::spc::Mask::ACTIVE_CFG_SYS_LVDE);
  }
 
  static inline constexpr uint32 ACTIVE_CFG_SYS_HVDE(uint32 value) {
    return ((value << +chip::spc::Shift::ACTIVE_CFG_SYS_HVDE) &
            +chip::spc::Mask::ACTIVE_CFG_SYS_HVDE);
  }
 
  static inline constexpr uint32 ACTIVE_CFG1_SOC_CNTRL(uint32 value) {
    return ((value << +chip::spc::Shift::ACTIVE_CFG1_SOC_CNTRL) &
            +chip::spc::Mask::ACTIVE_CFG1_SOC_CNTRL);
  }
 
  static inline constexpr uint32 LP_CFG_CORELDO_VDD_DS(uint32 value) {
    return ((value << +chip::spc::Shift::LP_CFG_CORELDO_VDD_DS) &
            +chip::spc::Mask::LP_CFG_CORELDO_VDD_DS);
  }
 
  static inline constexpr uint32 LP_CFG_CORELDO_VDD_LVL(uint32 value) {
    return ((value << +chip::spc::Shift::LP_CFG_CORELDO_VDD_LVL) &
            +chip::spc::Mask::LP_CFG_CORELDO_VDD_LVL);
  }
 
  static inline constexpr uint32 LP_CFG_SRAMLDO_DPD_ON(uint32 value) {
    return ((value << +chip::spc::Shift::LP_CFG_SRAMLDO_DPD_ON) &
            +chip::spc::Mask::LP_CFG_SRAMLDO_DPD_ON);
  }
 
  static inline constexpr uint32 LP_CFG_BGMODE(uint32 value) {
    return ((value << +chip::spc::Shift::LP_CFG_BGMODE) &
            +chip::spc::Mask::LP_CFG_BGMODE);
  }
 
  static inline constexpr uint32 LP_CFG_LP_IREFEN(uint32 value) {
    return ((value << +chip::spc::Shift::LP_CFG_LP_IREFEN) &
            +chip::spc::Mask::LP_CFG_LP_IREFEN);
  }
 
  static inline constexpr uint32 LP_CFG_CORE_LVDE(uint32 value) {
    return ((value << +chip::spc::Shift::LP_CFG_CORE_LVDE) &
            +chip::spc::Mask::LP_CFG_CORE_LVDE);
  }
 
  static inline constexpr uint32 LP_CFG_SYS_LVDE(uint32 value) {
    return ((value << +chip::spc::Shift::LP_CFG_SYS_LVDE) &
            +chip::spc::Mask::LP_CFG_SYS_LVDE);
  }
 
  static inline constexpr uint32 LP_CFG_SYS_HVDE(uint32 value) {
    return ((value << +chip::spc::Shift::LP_CFG_SYS_HVDE) &
            +chip::spc::Mask::LP_CFG_SYS_HVDE);
  }
 
  static inline constexpr uint32 LP_CFG1_SOC_CNTRL(uint32 value) {
    return ((value << +chip::spc::Shift::LP_CFG1_SOC_CNTRL) &
            +chip::spc::Mask::LP_CFG1_SOC_CNTRL);
  }
 
  static inline constexpr uint32 LPWKUP_DELAY_LPWKUP_DELAY(uint32 value) {
    return ((value << +chip::spc::Shift::LPWKUP_DELAY_LPWKUP_DELAY) &
            +chip::spc::Mask::LPWKUP_DELAY_LPWKUP_DELAY);
  }
 
  static inline constexpr uint32 ACTIVE_VDELAY_ACTIVE_VDELAY(uint32 value) {
    return ((value << +chip::spc::Shift::ACTIVE_VDELAY_ACTIVE_VDELAY) &
            +chip::spc::Mask::ACTIVE_VDELAY_ACTIVE_VDELAY);
  }
 
  static inline constexpr uint32 VD_STAT_COREVDD_LVDF(uint32 value) {
    return ((value << +chip::spc::Shift::VD_STAT_COREVDD_LVDF) &
            +chip::spc::Mask::VD_STAT_COREVDD_LVDF);
  }
 
  static inline constexpr uint32 VD_STAT_SYSVDD_LVDF(uint32 value) {
    return ((value << +chip::spc::Shift::VD_STAT_SYSVDD_LVDF) &
            +chip::spc::Mask::VD_STAT_SYSVDD_LVDF);
  }
 
  static inline constexpr uint32 VD_STAT_SYSVDD_HVDF(uint32 value) {
    return ((value << +chip::spc::Shift::VD_STAT_SYSVDD_HVDF) &
            +chip::spc::Mask::VD_STAT_SYSVDD_HVDF);
  }
 
  static inline constexpr uint32 VD_CORE_CFG_LVDRE(uint32 value) {
    return ((value << +chip::spc::Shift::VD_CORE_CFG_LVDRE) &
            +chip::spc::Mask::VD_CORE_CFG_LVDRE);
  }
 
  static inline constexpr uint32 VD_CORE_CFG_LVDIE(uint32 value) {
    return ((value << +chip::spc::Shift::VD_CORE_CFG_LVDIE) &
            +chip::spc::Mask::VD_CORE_CFG_LVDIE);
  }
 
  static inline constexpr uint32 VD_CORE_CFG_LOCK(uint32 value) {
    return ((value << +chip::spc::Shift::VD_CORE_CFG_LOCK) &
            +chip::spc::Mask::VD_CORE_CFG_LOCK);
  }
 
  static inline constexpr uint32 VD_SYS_CFG_LVDRE(uint32 value) {
    return ((value << +chip::spc::Shift::VD_SYS_CFG_LVDRE) &
            +chip::spc::Mask::VD_SYS_CFG_LVDRE);
  }
 
  static inline constexpr uint32 VD_SYS_CFG_LVDIE(uint32 value) {
    return ((value << +chip::spc::Shift::VD_SYS_CFG_LVDIE) &
            +chip::spc::Mask::VD_SYS_CFG_LVDIE);
  }
 
  static inline constexpr uint32 VD_SYS_CFG_HVDRE(uint32 value) {
    return ((value << +chip::spc::Shift::VD_SYS_CFG_HVDRE) &
            +chip::spc::Mask::VD_SYS_CFG_HVDRE);
  }
 
  static inline constexpr uint32 VD_SYS_CFG_HVDIE(uint32 value) {
    return ((value << +chip::spc::Shift::VD_SYS_CFG_HVDIE) &
            +chip::spc::Mask::VD_SYS_CFG_HVDIE);
  }
 
  static inline constexpr uint32 VD_SYS_CFG_LVSEL(uint32 value) {
    return ((value << +chip::spc::Shift::VD_SYS_CFG_LVSEL) &
            +chip::spc::Mask::VD_SYS_CFG_LVSEL);
  }
 
  static inline constexpr uint32 VD_SYS_CFG_LOCK(uint32 value) {
    return ((value << +chip::spc::Shift::VD_SYS_CFG_LOCK) &
            +chip::spc::Mask::VD_SYS_CFG_LOCK);
  }
 
  static inline constexpr uint32 EVD_CFG_EVDISO(uint32 value) {
    return ((value << +chip::spc::Shift::EVD_CFG_EVDISO) &
            +chip::spc::Mask::EVD_CFG_EVDISO);
  }
 
  static inline constexpr uint32 EVD_CFG_EVDLPISO(uint32 value) {
    return ((value << +chip::spc::Shift::EVD_CFG_EVDLPISO) &
            +chip::spc::Mask::EVD_CFG_EVDLPISO);
  }
 
  static inline constexpr uint32 EVD_CFG_EVDSTAT(uint32 value) {
    return ((value << +chip::spc::Shift::EVD_CFG_EVDSTAT) &
            +chip::spc::Mask::EVD_CFG_EVDSTAT);
  }
 
  static inline constexpr uint32 EVD_CFG_REG_EVDISO(uint32 value) {
    return value << +Shift::EVD_CFG_REG_EVDISO;
  }
 
  static inline constexpr uint32 EVD_CFG_REG_EVDLPISO(uint32 value) {
    return value << +Shift::EVD_CFG_REG_EVDLPISO;
  }
 
  static inline constexpr uint32 EVD_CFG_REG_EVDSTAT(uint32 value) {
    return value << +Shift::EVD_CFG_REG_EVDSTAT;
  }
};
 
/* ***************************************************************************************
 * End of file
 */
 
#endif /* CHIP_2E3411A1_6370_44BE_84E2_32D911539D8F */