chip::fmu::Register 結構 參考文件

公開屬性
__IO uint32	fstat
__IO uint32	fcnfg
__IO uint32	fctrl
__I uint32	ftest
__IO uint32	fccob0
__IO uint32	fccob1
__IO uint32	fccob2
__IO uint32	fccob3
__IO uint32	fccob4
__IO uint32	fccob5
__IO uint32	fccob6
__IO uint32	fccob7
uint8	reserved_0 [208]
__IO uint32	reset_status
__IO uint32	mctl
__I uint32	bsel_gen
__IO uint32	pwr_opt
__I uint32	cmd_check
uint8	reserved_1 [12]
__IO uint32	bsel
__IO uint32	msize
__IO uint32	flash_rd_add
uint8	reserved_2 [4]
__IO uint32	flash_stop_add
__IO uint32	flash_rd_ctrl
__IO uint32	mm_addr
uint8	reserved_3 [4]
__IO uint32	mm_wdata
__IO uint32	mm_ctl
__IO uint32	uint_ctl
__IO uint32	rd_data0
__IO uint32	rd_data1
__IO uint32	rd_data2
__IO uint32	rd_data3
__IO uint32	parity
__IO uint32	rd_path_ctrl_status
__IO uint32	smw_din0
__IO uint32	smw_din1
__IO uint32	smw_din2
__IO uint32	smw_din3
__IO uint32	smw_addr
__IO uint32	smw_cmd_wait
__I uint32	smw_status
__IO uint32	soctrim0_0
__IO uint32	soctrim0_1
__IO uint32	soctrim0_2
__IO uint32	soctrim0_3
__IO uint32	soctrim1_0
__IO uint32	soctrim1_1
__IO uint32	soctrim1_2
__IO uint32	soctrim1_3
__IO uint32	soctrim2_0
__IO uint32	soctrim2_1
__IO uint32	soctrim2_2
__IO uint32	soctrim2_3
__IO uint32	soctrim3_0
__IO uint32	soctrim3_1
__IO uint32	soctrim3_2
__IO uint32	soctrim3_3
__IO uint32	soctrim4_0
__IO uint32	soctrim4_1
__IO uint32	soctrim4_2
__IO uint32	soctrim4_3
__IO uint32	soctrim5_0
__IO uint32	soctrim5_1
__IO uint32	soctrim5_2
__IO uint32	soctrim5_3
__IO uint32	soctrim6_0
__IO uint32	soctrim6_1
__IO uint32	soctrim6_2
__IO uint32	soctrim6_3
__IO uint32	soctrim7_0
__IO uint32	soctrim7_1
__IO uint32	soctrim7_2
__IO uint32	soctrim7_3
uint8	reserved_4 [4]
__IO uint32	r_ip_config
__IO uint32	r_testcode
__IO uint32	r_dft_ctrl
__IO uint32	r_adr_ctrl
__IO uint32	r_data_ctrl0
__IO uint32	r_pin_ctrl
__IO uint32	r_cnt_loop_ctrl
__IO uint32	r_timer_ctrl
__IO uint32	r_test_ctrl
__O uint32	r_abort_loop
__I uint32	r_adr_query
__I uint32	r_dout_query0
uint8	reserved_5 [8]
__I uint32	r_smw_query
__IO uint32	r_smw_setting0
__IO uint32	r_smw_setting1
__IO uint32	r_smp_whv0
__IO uint32	r_smp_whv1
__IO uint32	r_sme_whv0
__IO uint32	r_sme_whv1
__IO uint32	r_smw_setting2
__I uint32	r_d_misr0
__I uint32	r_a_misr0
__I uint32	r_c_misr0
__IO uint32	r_smw_setting3
__IO uint32	r_data_ctrl1
__IO uint32	r_data_ctrl2
__IO uint32	r_data_ctrl3
uint8	reserved_6 [8]
__I uint32	r_repair0_0
__I uint32	r_repair0_1
__I uint32	r_repair1_0
__I uint32	r_repair1_1
uint8	reserved_7 [132]
__IO uint32	r_data_ctrl0_ex
uint8	reserved_8 [8]
__IO uint32	r_timer_ctrl_ex
uint8	reserved_9 [12]
__I uint32	r_dout_query1
uint8	reserved_10 [40]
__I uint32	r_d_misr1
__I uint32	r_a_misr1
__I uint32	r_c_misr1
uint8	reserved_11 [4]
__IO uint32	r_data_ctrl1_ex
__IO uint32	r_data_ctrl2_ex
__IO uint32	r_data_ctrl3_ex
uint8	reserved_12 [136]
__IO uint32	smw_timer_option
__IO uint32	smw_setting_option0
__IO uint32	smw_setting_option2
__IO uint32	smw_setting_option3
__IO uint32	smw_smp_whv_option0
__IO uint32	smw_sme_whv_option0
__IO uint32	smw_setting_option1
__IO uint32	smw_smp_whv_option1
__IO uint32	smw_sme_whv_option1
uint8	reserved_13 [220]
__IO uint32	repair0_0
__IO uint32	repair0_1
__IO uint32	repair1_0
__IO uint32	repair1_1
uint8	reserved_14 [240]
__IO uint32	smw_hb_signals
__IO uint32	bist_dump_ctrl
uint8	reserved_15 [4]
__IO uint32	atx_pin_ctrl
__IO uint32	failcnt
__IO uint32	pgm_pulse_cnt0
__IO uint32	pgm_pulse_cnt1
__IO uint32	ers_pulse_cnt
__IO uint32	max_pulse_cnt
__IO uint32	port_ctrl

資料成員說明文件

atx_pin_ctrl

__IO uint32 chip::fmu::Register::atx_pin_ctrl

ATX Pin Control Register, offset: 0x60C

bist_dump_ctrl

__IO uint32 chip::fmu::Register::bist_dump_ctrl

BIST Datadump Control Register, offset: 0x604

bsel

__IO uint32 chip::fmu::Register::bsel

FMU Block Select Register, offset: 0x120

bsel_gen

__I uint32 chip::fmu::Register::bsel_gen

FMU Block Select Generation Register, offset: 0x108

cmd_check

__I uint32 chip::fmu::Register::cmd_check

FMU Command Check Register, offset: 0x110

ers_pulse_cnt

__IO uint32 chip::fmu::Register::ers_pulse_cnt

Erase Pulse Count Register, offset: 0x61C

failcnt

__IO uint32 chip::fmu::Register::failcnt

Fail Count Register, offset: 0x610

fccob0

__IO uint32 chip::fmu::Register::fccob0

Flash Command Control 0 Register, offset: 0x10

fccob1

__IO uint32 chip::fmu::Register::fccob1

Flash Command Control 1 Register, offset: 0x14

fccob2

__IO uint32 chip::fmu::Register::fccob2

Flash Command Control 2 Register, offset: 0x18

fccob3

__IO uint32 chip::fmu::Register::fccob3

Flash Command Control 3 Register, offset: 0x1C

fccob4

__IO uint32 chip::fmu::Register::fccob4

Flash Command Control 4 Register, offset: 0x20

fccob5

__IO uint32 chip::fmu::Register::fccob5

Flash Command Control 5 Register, offset: 0x24

fccob6

__IO uint32 chip::fmu::Register::fccob6

Flash Command Control 6 Register, offset: 0x28

fccob7

__IO uint32 chip::fmu::Register::fccob7

Flash Command Control 7 Register, offset: 0x2C

fcnfg

__IO uint32 chip::fmu::Register::fcnfg

Flash Configuration Register, offset: 0x4

fctrl

__IO uint32 chip::fmu::Register::fctrl

Flash Control Register, offset: 0x8

flash_rd_add

__IO uint32 chip::fmu::Register::flash_rd_add

Flash Read Address Register, offset: 0x128

flash_rd_ctrl

__IO uint32 chip::fmu::Register::flash_rd_ctrl

Flash Read Control Register, offset: 0x134

flash_stop_add

__IO uint32 chip::fmu::Register::flash_stop_add

Flash Stop Address Register, offset: 0x130

fstat

__IO uint32 chip::fmu::Register::fstat

Flash Status Register, offset: 0x0

ftest

__I uint32 chip::fmu::Register::ftest

Flash Test Register, offset: 0xC

max_pulse_cnt

__IO uint32 chip::fmu::Register::max_pulse_cnt

Maximum Pulse Count Register, offset: 0x620

mctl

__IO uint32 chip::fmu::Register::mctl

FMU Control Register, offset: 0x104

mm_addr

__IO uint32 chip::fmu::Register::mm_addr

Memory Map Address Register, offset: 0x138

mm_ctl

__IO uint32 chip::fmu::Register::mm_ctl

Memory Map Control Register, offset: 0x144

mm_wdata

__IO uint32 chip::fmu::Register::mm_wdata

Memory Map Write Data Register, offset: 0x140

msize

__IO uint32 chip::fmu::Register::msize

FMU Memory Size Register, offset: 0x124

parity

__IO uint32 chip::fmu::Register::parity

Parity Register, offset: 0x15C

pgm_pulse_cnt0

__IO uint32 chip::fmu::Register::pgm_pulse_cnt0

Block 0 Program Pulse Count Register, offset: 0x614

pgm_pulse_cnt1

__IO uint32 chip::fmu::Register::pgm_pulse_cnt1

Block 1 Program Pulse Count Register, offset: 0x618

port_ctrl

__IO uint32 chip::fmu::Register::port_ctrl

Port Control Register, offset: 0x624

pwr_opt

__IO uint32 chip::fmu::Register::pwr_opt

Power Mode Options Register, offset: 0x10C

r_a_misr0

__I uint32 chip::fmu::Register::r_a_misr0

BIST Address MISR 0 Register, offset: 0x260

r_a_misr1

__I uint32 chip::fmu::Register::r_a_misr1

BIST Address MISR 1 Register, offset: 0x360

r_abort_loop

__O uint32 chip::fmu::Register::r_abort_loop

BIST Abort Loop Register, offset: 0x228

r_adr_ctrl

__IO uint32 chip::fmu::Register::r_adr_ctrl

BIST Address Control Register, offset: 0x210

r_adr_query

__I uint32 chip::fmu::Register::r_adr_query

BIST Address Query Register, offset: 0x22C

r_c_misr0

__I uint32 chip::fmu::Register::r_c_misr0

BIST Control MISR 0 Register, offset: 0x264

r_c_misr1

__I uint32 chip::fmu::Register::r_c_misr1

BIST Control MISR 1 Register, offset: 0x364

r_cnt_loop_ctrl

__IO uint32 chip::fmu::Register::r_cnt_loop_ctrl

BIST Loop Count Control Register, offset: 0x21C

r_d_misr0

__I uint32 chip::fmu::Register::r_d_misr0

BIST DIN MISR 0 Register, offset: 0x25C

r_d_misr1

__I uint32 chip::fmu::Register::r_d_misr1

BIST DIN MISR 1 Register, offset: 0x35C

r_data_ctrl0

__IO uint32 chip::fmu::Register::r_data_ctrl0

BIST Data Control 0 Register, offset: 0x214

r_data_ctrl0_ex

__IO uint32 chip::fmu::Register::r_data_ctrl0_ex

BIST Data Control 0 Extension Register, offset: 0x314

r_data_ctrl1

__IO uint32 chip::fmu::Register::r_data_ctrl1

BIST Data Control 1 Register, offset: 0x26C

r_data_ctrl1_ex

__IO uint32 chip::fmu::Register::r_data_ctrl1_ex

BIST Data Control 1 Extension Register, offset: 0x36C

r_data_ctrl2

__IO uint32 chip::fmu::Register::r_data_ctrl2

BIST Data Control 2 Register, offset: 0x270

r_data_ctrl2_ex

__IO uint32 chip::fmu::Register::r_data_ctrl2_ex

BIST Data Control 2 Extension Register, offset: 0x370

r_data_ctrl3

__IO uint32 chip::fmu::Register::r_data_ctrl3

BIST Data Control 3 Register, offset: 0x274

r_data_ctrl3_ex

__IO uint32 chip::fmu::Register::r_data_ctrl3_ex

BIST Data Control 3 Extension Register, offset: 0x374

r_dft_ctrl

__IO uint32 chip::fmu::Register::r_dft_ctrl

BIST DFT Control Register, offset: 0x20C

r_dout_query0

__I uint32 chip::fmu::Register::r_dout_query0

BIST DOUT Query 0 Register, offset: 0x230

r_dout_query1

__I uint32 chip::fmu::Register::r_dout_query1

BIST DOUT Query 1 Register, offset: 0x330

r_ip_config

__IO uint32 chip::fmu::Register::r_ip_config

BIST Configuration Register, offset: 0x204

r_pin_ctrl

__IO uint32 chip::fmu::Register::r_pin_ctrl

BIST Pin Control Register, offset: 0x218

r_repair0_0

__I uint32 chip::fmu::Register::r_repair0_0

BIST Repair 0 for Block 0 Register, offset: 0x280

r_repair0_1

__I uint32 chip::fmu::Register::r_repair0_1

BIST Repair 1 Block 0 Register, offset: 0x284

r_repair1_0

__I uint32 chip::fmu::Register::r_repair1_0

BIST Repair 0 Block 1 Register, offset: 0x288

r_repair1_1

__I uint32 chip::fmu::Register::r_repair1_1

BIST Repair 1 Block 1 Register, offset: 0x28C

r_sme_whv0

__IO uint32 chip::fmu::Register::r_sme_whv0

BIST SME WHV Setting 0 Register, offset: 0x250

r_sme_whv1

__IO uint32 chip::fmu::Register::r_sme_whv1

BIST SME WHV Setting 1 Register, offset: 0x254

r_smp_whv0

__IO uint32 chip::fmu::Register::r_smp_whv0

BIST SMP WHV Setting 0 Register, offset: 0x248

r_smp_whv1

__IO uint32 chip::fmu::Register::r_smp_whv1

BIST SMP WHV Setting 1 Register, offset: 0x24C

r_smw_query

__I uint32 chip::fmu::Register::r_smw_query

BIST SMW Query Register, offset: 0x23C

r_smw_setting0

__IO uint32 chip::fmu::Register::r_smw_setting0

BIST SMW Setting 0 Register, offset: 0x240

r_smw_setting1

__IO uint32 chip::fmu::Register::r_smw_setting1

BIST SMW Setting 1 Register, offset: 0x244

r_smw_setting2

__IO uint32 chip::fmu::Register::r_smw_setting2

BIST SMW Setting 2 Register, offset: 0x258

r_smw_setting3

__IO uint32 chip::fmu::Register::r_smw_setting3

BIST SMW Setting 3 Register, offset: 0x268

r_test_ctrl

__IO uint32 chip::fmu::Register::r_test_ctrl

BIST Test Control Register, offset: 0x224

r_testcode

__IO uint32 chip::fmu::Register::r_testcode

BIST Test Code Register, offset: 0x208

r_timer_ctrl

__IO uint32 chip::fmu::Register::r_timer_ctrl

BIST Timer Control Register, offset: 0x220

r_timer_ctrl_ex

__IO uint32 chip::fmu::Register::r_timer_ctrl_ex

BIST Timer Control Extension Register, offset: 0x320

rd_data0

__IO uint32 chip::fmu::Register::rd_data0

Read Data 0 Register, offset: 0x14C

rd_data1

__IO uint32 chip::fmu::Register::rd_data1

Read Data 1 Register, offset: 0x150

rd_data2

__IO uint32 chip::fmu::Register::rd_data2

Read Data 2 Register, offset: 0x154

rd_data3

__IO uint32 chip::fmu::Register::rd_data3

Read Data 3 Register, offset: 0x158

rd_path_ctrl_status

__IO uint32 chip::fmu::Register::rd_path_ctrl_status

Read Path Control and Status Register, offset: 0x160

repair0_0

__IO uint32 chip::fmu::Register::repair0_0

FMU Repair 0 Block 0 Register, offset: 0x500

repair0_1

__IO uint32 chip::fmu::Register::repair0_1

FMU Repair 1 Block 0 Register, offset: 0x504

repair1_0

__IO uint32 chip::fmu::Register::repair1_0

FMU Repair 0 Block 1 Register, offset: 0x508

repair1_1

__IO uint32 chip::fmu::Register::repair1_1

FMU Repair 1 Block 1 Register, offset: 0x50C

reset_status

__IO uint32 chip::fmu::Register::reset_status

FMU Initialization Tracking Register, offset: 0x100

smw_addr

__IO uint32 chip::fmu::Register::smw_addr

SMW Address Register, offset: 0x174

smw_cmd_wait

__IO uint32 chip::fmu::Register::smw_cmd_wait

SMW Command and Wait Register, offset: 0x178

smw_din0

__IO uint32 chip::fmu::Register::smw_din0

SMW DIN 0 Register, offset: 0x164

smw_din1

__IO uint32 chip::fmu::Register::smw_din1

SMW DIN 1 Register, offset: 0x168

smw_din2

__IO uint32 chip::fmu::Register::smw_din2

SMW DIN 2 Register, offset: 0x16C

smw_din3

__IO uint32 chip::fmu::Register::smw_din3

SMW DIN 3 Register, offset: 0x170

smw_hb_signals

__IO uint32 chip::fmu::Register::smw_hb_signals

SMW HB Signals Register, offset: 0x600

smw_setting_option0

__IO uint32 chip::fmu::Register::smw_setting_option0

SMW Setting Option 0 Register, offset: 0x404

smw_setting_option1

__IO uint32 chip::fmu::Register::smw_setting_option1

SMW Setting Option 1 Register, offset: 0x418

smw_setting_option2

__IO uint32 chip::fmu::Register::smw_setting_option2

SMW Setting Option 2 Register, offset: 0x408

smw_setting_option3

__IO uint32 chip::fmu::Register::smw_setting_option3

SMW Setting Option 3 Register, offset: 0x40C

smw_sme_whv_option0

__IO uint32 chip::fmu::Register::smw_sme_whv_option0

SMW SME WHV Option 0 Register, offset: 0x414

smw_sme_whv_option1

__IO uint32 chip::fmu::Register::smw_sme_whv_option1

SMW SME WHV Option 1 Register, offset: 0x420

smw_smp_whv_option0

__IO uint32 chip::fmu::Register::smw_smp_whv_option0

SMW SMP WHV Option 0 Register, offset: 0x410

smw_smp_whv_option1

__IO uint32 chip::fmu::Register::smw_smp_whv_option1

SMW SMP WHV Option 1 Register, offset: 0x41C

smw_status

__I uint32 chip::fmu::Register::smw_status

SMW Status Register, offset: 0x17C

smw_timer_option

__IO uint32 chip::fmu::Register::smw_timer_option

SMW Timer Option Register, offset: 0x400

soctrim0_0

__IO uint32 chip::fmu::Register::soctrim0_0

SoC Trim Phrase 0 Word 0 Register, offset: 0x180

soctrim0_1

__IO uint32 chip::fmu::Register::soctrim0_1

SoC Trim Phrase 0 Word 1 Register, offset: 0x184

soctrim0_2

__IO uint32 chip::fmu::Register::soctrim0_2

SoC Trim Phrase 0 Word 2 Register, offset: 0x188

soctrim0_3

__IO uint32 chip::fmu::Register::soctrim0_3

SoC Trim Phrase 0 Word 3 Register, offset: 0x18C

soctrim1_0

__IO uint32 chip::fmu::Register::soctrim1_0

SoC Trim Phrase 1 Word 0 Register, offset: 0x190

soctrim1_1

__IO uint32 chip::fmu::Register::soctrim1_1

SoC Trim Phrase 1 Word 1 Register, offset: 0x194

soctrim1_2

__IO uint32 chip::fmu::Register::soctrim1_2

SoC Trim Phrase 1 Word 2 Register, offset: 0x198

soctrim1_3

__IO uint32 chip::fmu::Register::soctrim1_3

SoC Trim Phrase 1 Word 3 Register, offset: 0x19C

soctrim2_0

__IO uint32 chip::fmu::Register::soctrim2_0

SoC Trim Phrase 2 Word 0 Register, offset: 0x1A0

soctrim2_1

__IO uint32 chip::fmu::Register::soctrim2_1

SoC Trim Phrase 2 Word 1 Register, offset: 0x1A4

soctrim2_2

__IO uint32 chip::fmu::Register::soctrim2_2

SoC Trim Phrase 2 Word 2 Register, offset: 0x1A8

soctrim2_3

__IO uint32 chip::fmu::Register::soctrim2_3

SoC Trim Phrase 2 Word 3 Register, offset: 0x1AC

soctrim3_0

__IO uint32 chip::fmu::Register::soctrim3_0

SoC Trim Phrase 3 Word 0 Register, offset: 0x1B0

soctrim3_1

__IO uint32 chip::fmu::Register::soctrim3_1

SoC Trim Phrase 3 Word 1 Register, offset: 0x1B4

soctrim3_2

__IO uint32 chip::fmu::Register::soctrim3_2

SoC Trim Phrase 3 Word 2 Register, offset: 0x1B8

soctrim3_3

__IO uint32 chip::fmu::Register::soctrim3_3

SoC Trim Phrase 3 Word 3 Register, offset: 0x1BC

soctrim4_0

__IO uint32 chip::fmu::Register::soctrim4_0

SoC Trim Phrase 4 Word 0 Register, offset: 0x1C0

soctrim4_1

__IO uint32 chip::fmu::Register::soctrim4_1

SoC Trim Phrase 4 Word 1 Register, offset: 0x1C4

soctrim4_2

__IO uint32 chip::fmu::Register::soctrim4_2

SoC Trim Phrase 4 Word 2 Register, offset: 0x1C8

soctrim4_3

__IO uint32 chip::fmu::Register::soctrim4_3

SoC Trim Phrase 4 Word 3 Register, offset: 0x1CC

soctrim5_0

__IO uint32 chip::fmu::Register::soctrim5_0

SoC Trim Phrase 5 Word 0 Register, offset: 0x1D0

soctrim5_1

__IO uint32 chip::fmu::Register::soctrim5_1

SoC Trim Phrase 5 Word 1 Register, offset: 0x1D4

soctrim5_2

__IO uint32 chip::fmu::Register::soctrim5_2

SoC Trim Phrase 5 Word 2 Register, offset: 0x1D8

soctrim5_3

__IO uint32 chip::fmu::Register::soctrim5_3

SoC Trim Phrase 5 Word 3 Register, offset: 0x1DC

soctrim6_0

__IO uint32 chip::fmu::Register::soctrim6_0

SoC Trim Phrase 6 Word 0 Register, offset: 0x1E0

soctrim6_1

__IO uint32 chip::fmu::Register::soctrim6_1

SoC Trim Phrase 6 Word 1 Register, offset: 0x1E4

soctrim6_2

__IO uint32 chip::fmu::Register::soctrim6_2

SoC Trim Phrase 6 Word 2 Register, offset: 0x1E8

soctrim6_3

__IO uint32 chip::fmu::Register::soctrim6_3

SoC Trim Phrase 6 Word 3 Register, offset: 0x1EC

soctrim7_0

__IO uint32 chip::fmu::Register::soctrim7_0

SoC Trim Phrase 7 Word 0 Register, offset: 0x1F0

soctrim7_1

__IO uint32 chip::fmu::Register::soctrim7_1

SoC Trim Phrase 7 Word 1 Register, offset: 0x1F4

soctrim7_2

__IO uint32 chip::fmu::Register::soctrim7_2

SoC Trim Phrase 7 Word 2 Register, offset: 0x1F8

soctrim7_3

__IO uint32 chip::fmu::Register::soctrim7_3

SoC Trim Phrase 7 Word 3 Register, offset: 0x1FC

uint_ctl

__IO uint32 chip::fmu::Register::uint_ctl

User Interface Control Register, offset: 0x148

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此結構(structure) 文件是由下列檔案中產生:

• fmu/Register.h