fmu/Register.h

 
#ifndef CHIP_4A5D4EFB_7D8F_4389_9030_22F8C5FC54DB
#define CHIP_4A5D4EFB_7D8F_4389_9030_22F8C5FC54DB
 
/* ***************************************************************************************
 * Include
 */
 
//----------------------------------------------------------------------------------------
#include "mframe.h"
 
//----------------------------------------------------------------------------------------
 
/* ***************************************************************************************
 * Namespace
 */
namespace chip::fmu {
  struct Register;
}  // namespace chip::fmu
 
/* ***************************************************************************************
 * Class/Interface/Struct/Enum
 */
struct chip::fmu::Register {
  __IO uint32 fstat;  
  __IO uint32 fcnfg;  
  __IO uint32 fctrl;  
  __I uint32  ftest;  
  __IO uint32 fccob0; 
  __IO uint32 fccob1; 
  __IO uint32 fccob2; 
  __IO uint32 fccob3; 
  __IO uint32 fccob4; 
  __IO uint32 fccob5; 
  __IO uint32 fccob6; 
  __IO uint32 fccob7; 
  uint8       reserved_0[208];
  __IO uint32 reset_status; 
  __IO uint32 mctl;         
  __I uint32  bsel_gen;     
  __IO uint32 pwr_opt;      
  __I uint32  cmd_check;    
  uint8       reserved_1[12];
  __IO uint32 bsel;         
  __IO uint32 msize;        
  __IO uint32 flash_rd_add; 
  uint8       reserved_2[4];
  __IO uint32 flash_stop_add; 
  __IO uint32 flash_rd_ctrl;  
  __IO uint32 mm_addr;        
  uint8       reserved_3[4];
  __IO uint32 mm_wdata;            
  __IO uint32 mm_ctl;              
  __IO uint32 uint_ctl;            
  __IO uint32 rd_data0;            
  __IO uint32 rd_data1;            
  __IO uint32 rd_data2;            
  __IO uint32 rd_data3;            
  __IO uint32 parity;              
  __IO uint32 rd_path_ctrl_status; 
  __IO uint32 smw_din0;            
  __IO uint32 smw_din1;            
  __IO uint32 smw_din2;            
  __IO uint32 smw_din3;            
  __IO uint32 smw_addr;            
  __IO uint32 smw_cmd_wait;        
  __I uint32  smw_status;          
  __IO uint32 soctrim0_0;          
  __IO uint32 soctrim0_1;          
  __IO uint32 soctrim0_2;          
  __IO uint32 soctrim0_3;          
  __IO uint32 soctrim1_0;          
  __IO uint32 soctrim1_1;          
  __IO uint32 soctrim1_2;          
  __IO uint32 soctrim1_3;          
  __IO uint32 soctrim2_0;          
  __IO uint32 soctrim2_1;          
  __IO uint32 soctrim2_2;          
  __IO uint32 soctrim2_3;          
  __IO uint32 soctrim3_0;          
  __IO uint32 soctrim3_1;          
  __IO uint32 soctrim3_2;          
  __IO uint32 soctrim3_3;          
  __IO uint32 soctrim4_0;          
  __IO uint32 soctrim4_1;          
  __IO uint32 soctrim4_2;          
  __IO uint32 soctrim4_3;          
  __IO uint32 soctrim5_0;          
  __IO uint32 soctrim5_1;          
  __IO uint32 soctrim5_2;          
  __IO uint32 soctrim5_3;          
  __IO uint32 soctrim6_0;          
  __IO uint32 soctrim6_1;          
  __IO uint32 soctrim6_2;          
  __IO uint32 soctrim6_3;          
  __IO uint32 soctrim7_0;          
  __IO uint32 soctrim7_1;          
  __IO uint32 soctrim7_2;          
  __IO uint32 soctrim7_3;          
  uint8       reserved_4[4];
  __IO uint32 r_ip_config;     
  __IO uint32 r_testcode;      
  __IO uint32 r_dft_ctrl;      
  __IO uint32 r_adr_ctrl;      
  __IO uint32 r_data_ctrl0;    
  __IO uint32 r_pin_ctrl;      
  __IO uint32 r_cnt_loop_ctrl; 
  __IO uint32 r_timer_ctrl;    
  __IO uint32 r_test_ctrl;     
  __O uint32  r_abort_loop;    
  __I uint32  r_adr_query;     
  __I uint32  r_dout_query0;   
  uint8       reserved_5[8];
  __I uint32  r_smw_query;    
  __IO uint32 r_smw_setting0; 
  __IO uint32 r_smw_setting1; 
  __IO uint32 r_smp_whv0;     
  __IO uint32 r_smp_whv1;     
  __IO uint32 r_sme_whv0;     
  __IO uint32 r_sme_whv1;     
  __IO uint32 r_smw_setting2; 
  __I uint32  r_d_misr0;      
  __I uint32  r_a_misr0;      
  __I uint32  r_c_misr0;      
  __IO uint32 r_smw_setting3; 
  __IO uint32 r_data_ctrl1;   
  __IO uint32 r_data_ctrl2;   
  __IO uint32 r_data_ctrl3;   
  uint8       reserved_6[8];
  __I uint32  r_repair0_0; 
  __I uint32  r_repair0_1; 
  __I uint32  r_repair1_0; 
  __I uint32  r_repair1_1; 
  uint8       reserved_7[132];
  __IO uint32 r_data_ctrl0_ex; 
  uint8       reserved_8[8];
  __IO uint32 r_timer_ctrl_ex; 
  uint8       reserved_9[12];
  __I uint32  r_dout_query1; 
  uint8       reserved_10[40];
  __I uint32  r_d_misr1; 
  __I uint32  r_a_misr1; 
  __I uint32  r_c_misr1; 
  uint8       reserved_11[4];
  __IO uint32 r_data_ctrl1_ex; 
  __IO uint32 r_data_ctrl2_ex; 
  __IO uint32 r_data_ctrl3_ex; 
  uint8       reserved_12[136];
  __IO uint32 smw_timer_option;    
  __IO uint32 smw_setting_option0; 
  __IO uint32 smw_setting_option2; 
  __IO uint32 smw_setting_option3; 
  __IO uint32 smw_smp_whv_option0; 
  __IO uint32 smw_sme_whv_option0; 
  __IO uint32 smw_setting_option1; 
  __IO uint32 smw_smp_whv_option1; 
  __IO uint32 smw_sme_whv_option1; 
  uint8       reserved_13[220];
  __IO uint32 repair0_0; 
  __IO uint32 repair0_1; 
  __IO uint32 repair1_0; 
  __IO uint32 repair1_1; 
  uint8       reserved_14[240];
  __IO uint32 smw_hb_signals; 
  __IO uint32 bist_dump_ctrl; 
  uint8       reserved_15[4];
  __IO uint32 atx_pin_ctrl;   
  __IO uint32 failcnt;        
  __IO uint32 pgm_pulse_cnt0; 
  __IO uint32 pgm_pulse_cnt1; 
  __IO uint32 ers_pulse_cnt;  
  __IO uint32 max_pulse_cnt;  
  __IO uint32 port_ctrl;      
};
 
/* ***************************************************************************************
 * End of file
 */
 
#endif /* CHIP_4A5D4EFB_7D8F_4389_9030_22F8C5FC54DB */