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複合項目 | 列舉型態 | 函式 | 變數
chip::port 命名空間(Namespace)參考文件

複合項目

struct  Config
 
class  Port
 
struct  Register
 
struct  Version
 

列舉型態

enum struct  DriveStrength : bool { LOW = 0U , HIGH = 1U }
 
enum struct  DriveStrengthDouble : bool { NORMAL = 0U , DOUBLE = 1U }
 
enum struct  InputBuffer : bool { DISABLE = 0U , ENABLE = 1U }
 
enum struct  Inverted : bool { NORMAL = 0U , INVERT = 1U }
 
enum struct  Lock : bool { UNLOCK = 0U , LOCK = 1U }
 
enum struct  Mask : unsigned int {
  VERID_FEATURE = 0xFFFFU , VERID_MINOR = 0xFF0000U , VERID_MAJOR = 0xFF000000U , GPCLR_GPWD = 0xFFFFU ,
  GPCLR_GPWE0 = 0x10000U , GPCLR_GPWE1 = 0x20000U , GPCLR_GPWE2 = 0x40000U , GPCLR_GPWE3 = 0x80000U ,
  GPCLR_GPWE4 = 0x100000U , GPCLR_GPWE5 = 0x200000U , GPCLR_GPWE6 = 0x400000U , GPCLR_GPWE7 = 0x800000U ,
  GPCLR_GPWE8 = 0x1000000U , GPCLR_GPWE9 = 0x2000000U , GPCLR_GPWE10 = 0x4000000U , GPCLR_GPWE11 = 0x8000000U ,
  GPCLR_GPWE12 = 0x10000000U , GPCLR_GPWE13 = 0x20000000U , GPCLR_GPWE14 = 0x40000000U , GPCLR_GPWE15 = 0x80000000U ,
  GPCHR_GPWD = 0xFFFFU , GPCHR_GPWE16 = 0x10000U , GPCHR_GPWE17 = 0x20000U , GPCHR_GPWE18 = 0x40000U ,
  GPCHR_GPWE19 = 0x80000U , GPCHR_GPWE20 = 0x100000U , GPCHR_GPWE21 = 0x200000U , GPCHR_GPWE22 = 0x400000U ,
  GPCHR_GPWE23 = 0x800000U , GPCHR_GPWE24 = 0x1000000U , GPCHR_GPWE25 = 0x2000000U , GPCHR_GPWE26 = 0x4000000U ,
  GPCHR_GPWE27 = 0x8000000U , GPCHR_GPWE28 = 0x10000000U , GPCHR_GPWE29 = 0x20000000U , GPCHR_GPWE30 = 0x40000000U ,
  GPCHR_GPWE31 = 0x80000000U , CONFIG_RANGE = 0x1U , CALIB0_NCAL = 0x3FU , CALIB0_PCAL = 0x3F0000U ,
  CALIB1_NCAL = 0x3FU , CALIB1_PCAL = 0x3F0000U , PCR_PS = 0x1U , PCR_PE = 0x2U ,
  PCR_PV = 0x4U , PCR_SRE = 0x8U , PCR_PFE = 0x10U , PCR_ODE = 0x20U ,
  PCR_DSE = 0x40U , PCR_DSE1 = 0x80U , PCR_MUX = 0xF00U , PCR_IBE = 0x1000U ,
  PCR_INV = 0x2000U , PCR_LK = 0x8000U
}
 PORT_Register_Masks PORT Register Masks. 更多...
 
enum struct  Mux : unsigned char {
  GPIO = 0U , ALT0 = 0U , ALT1 = 1U , ALT2 = 2U ,
  ALT3 = 3U , ALT4 = 4U , ALT5 = 5U , ALT6 = 6U ,
  ALT7 = 7U , ALT8 = 8U , ALT9 = 9U , ALT10 = 10U ,
  ALT11 = 11U , ALT12 = 12U , ALT13 = 13U , ALT14 = 14U ,
  ALT15 = 15U
}
 
enum struct  OpenDrain : bool { DISABLE = 0U , ENABLE = 1U }
 
enum struct  PassiveFilter : bool { DISABLE = 0U , ENABLE = 1U }
 
enum struct  Pull : unsigned char { DISABLE = 0U , DOWN = 2U , UP = 3U }
 
enum struct  PullResistor : bool { LOW = 0U , HIGH = 1U }
 
enum struct  Rate : bool { FAST = 0U , SLOW = 1U }
 
enum struct  Shift : unsigned int {
  VERID_FEATURE = 0U , VERID_MINOR = 16U , VERID_MAJOR = 24U , GPCLR_GPWD = 0U ,
  GPCLR_GPWE0 = 16U , GPCLR_GPWE1 = 17U , GPCLR_GPWE2 = 18U , GPCLR_GPWE3 = 19U ,
  GPCLR_GPWE4 = 20U , GPCLR_GPWE5 = 21U , GPCLR_GPWE6 = 22U , GPCLR_GPWE7 = 23U ,
  GPCLR_GPWE8 = 24U , GPCLR_GPWE9 = 25U , GPCLR_GPWE10 = 26U , GPCLR_GPWE11 = 27U ,
  GPCLR_GPWE12 = 28U , GPCLR_GPWE13 = 29U , GPCLR_GPWE14 = 30U , GPCLR_GPWE15 = 31U ,
  GPCHR_GPWD = 0U , GPCHR_GPWE16 = 16U , GPCHR_GPWE17 = 17U , GPCHR_GPWE18 = 18U ,
  GPCHR_GPWE19 = 19U , GPCHR_GPWE20 = 20U , GPCHR_GPWE21 = 21U , GPCHR_GPWE22 = 22U ,
  GPCHR_GPWE23 = 23U , GPCHR_GPWE24 = 24U , GPCHR_GPWE25 = 25U , GPCHR_GPWE26 = 26U ,
  GPCHR_GPWE27 = 27U , GPCHR_GPWE28 = 28U , GPCHR_GPWE29 = 29U , GPCHR_GPWE30 = 30U ,
  GPCHR_GPWE31 = 31U , CONFIG_RANGE = 0U , CALIB0_NCAL = 0U , CALIB0_PCAL = 16U ,
  CALIB1_NCAL = 0U , CALIB1_PCAL = 16U , PCR_PS = 0U , PCR_PE = 1U ,
  PCR_PV = 2U , PCR_SRE = 3U , PCR_PFE = 4U , PCR_ODE = 5U ,
  PCR_DSE = 6U , PCR_DSE1 = 7U , PCR_MUX = 8U , PCR_IBE = 12U ,
  PCR_INV = 13U , PCR_LK = 15U
}
 PORT_Register_Masks PORT Register Shift. 更多...
 
enum struct  VoltageRange : bool { RANGE_1V71_3V6 = 0x0U , RANGE_2V70_3V6 = 0x1U }
 

函式

constexpr bool operator+ (DriveStrength e)
 
constexpr bool operator+ (DriveStrengthDouble e)
 
constexpr bool operator+ (InputBuffer e)
 
constexpr bool operator+ (Inverted e)
 
constexpr bool operator+ (Lock e)
 
constexpr unsigned int operator+ (Mask e)
 
constexpr unsigned char operator+ (Mux e)
 
constexpr bool operator+ (OpenDrain e)
 
constexpr bool operator+ (PassiveFilter e)
 
constexpr unsigned char operator+ (Pull e)
 
constexpr bool operator+ (PullResistor e)
 
constexpr bool operator+ (Rate e)
 
constexpr unsigned int operator+ (Shift e)
 
constexpr bool operator+ (VoltageRange e)
 

變數

Register & PORT0
 
Register & PORT1
 
Register & PORT2
 
Register & PORT3
 
Register *const PORT [4]
 

詳細描述

Copyright (c) 2020 ZxyKira All rights reserved.

SPDX-License-Identifier: MIT

列舉型態說明文件

◆ DriveStrength

enum struct chip::port::DriveStrength : bool
strong
列舉值
LOW 

Low-drive strength is configured.

HIGH 

High-drive strength is configured.

◆ DriveStrengthDouble

enum struct chip::port::DriveStrengthDouble : bool
strong
列舉值
NORMAL 

Normal drive strength

DOUBLE 

Double drive strength

◆ InputBuffer

enum struct chip::port::InputBuffer : bool
strong
列舉值
DISABLE 

Digital input is disabled

ENABLE 

Digital input is enabled

◆ Inverted

enum struct chip::port::Inverted : bool
strong
列舉值
NORMAL 

Digital input is not inverted

INVERT 

Digital input is inverted

◆ Lock

enum struct chip::port::Lock : bool
strong
列舉值
UNLOCK 

Pin Control Register fields [15:0] are not locked.

LOCK 

Pin Control Register fields [15:0] are locked.

◆ Mask

enum struct chip::port::Mask : unsigned int
strong

PORT_Register_Masks PORT Register Masks.

列舉值
VERID_FEATURE 

VERID - FEATURE.

Version ID - Feature Specification Number

  • [0b0000000000000000]Basic implementation
VERID_MINOR 

VERID - MINOR.

Version ID - Minor Version Number

VERID_MAJOR 

VERID - MAJOR.

Version ID - Major Version Number

GPCLR_GPWD 

GPCLR - GPWD.

Global Pin Control Low - Global Pin Write Data

GPCLR_GPWE0 

GPCLR - GPWE0.

Global Pin Control Low - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCLR_GPWE1 

GPCLR - GPWE1.

Global Pin Control Low - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCLR_GPWE2 

GPCLR - GPWE2.

Global Pin Control Low - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCLR_GPWE3 

GPCLR - GPWE3.

Global Pin Control Low - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCLR_GPWE4 

GPCLR - GPWE4.

Global Pin Control Low - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCLR_GPWE5 

GPCLR - GPWE5.

Global Pin Control Low - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCLR_GPWE6 

GPCLR - GPWE6.

Global Pin Control Low - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCLR_GPWE7 

GPCLR - GPWE7.

Global Pin Control Low - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCLR_GPWE8 

GPCLR - GPWE8.

Global Pin Control Low - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCLR_GPWE9 

GPCLR - GPWE9.

Global Pin Control Low - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCLR_GPWE10 

GPCLR - GPWE10.

Global Pin Control Low - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCLR_GPWE11 

GPCLR - GPWE11.

Global Pin Control Low - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCLR_GPWE12 

GPCLR - GPWE12.

Global Pin Control Low - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCLR_GPWE13 

GPCLR - GPWE13.

Global Pin Control Low - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCLR_GPWE14 

GPCLR - GPWE14.

Global Pin Control Low - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCLR_GPWE15 

GPCLR - GPWE15.

Global Pin Control Low - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCHR_GPWD 

GPCHR - GPWD.

Global Pin Control High - Global Pin Write Data

GPCHR_GPWE16 

GPCHR - GPWE16.

Global Pin Control High - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCHR_GPWE17 

GPCHR - GPWE17.

Global Pin Control High - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCHR_GPWE18 

GPCHR - GPWE18.

Global Pin Control High - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCHR_GPWE19 

GPCHR - GPWE19.

Global Pin Control High - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCHR_GPWE20 

GPCHR - GPWE20.

Global Pin Control High - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCHR_GPWE21 

GPCHR - GPWE21.

Global Pin Control High - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCHR_GPWE22 

GPCHR - GPWE22.

Global Pin Control High - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCHR_GPWE23 

GPCHR - GPWE23.

Global Pin Control High - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCHR_GPWE24 

GPCHR - GPWE24.

Global Pin Control High - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCHR_GPWE25 

GPCHR - GPWE25.

Global Pin Control High - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCHR_GPWE26 

GPCHR - GPWE26.

Global Pin Control High - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCHR_GPWE27 

GPCHR - GPWE27.

Global Pin Control High - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCHR_GPWE28 

GPCHR - GPWE28.

Global Pin Control High - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCHR_GPWE29 

GPCHR - GPWE29.

Global Pin Control High - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCHR_GPWE30 

GPCHR - GPWE30.

Global Pin Control High - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCHR_GPWE31 

GPCHR - GPWE31.

Global Pin Control High - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
CONFIG_RANGE 

CONFIG - RANGE.

Configuration - Port Voltage Range

  • [0b0]1.71 V-3.6 V
  • [0b1]2.70 V-3.6 V
CALIB0_NCAL 

CALIB0 - NCAL.

Calibration 0 - Calibration of NMOS Output Driver

CALIB0_PCAL 

CALIB0 - PCAL.

Calibration 0 - Calibration of PMOS Output Driver

CALIB1_NCAL 

CALIB1 - NCAL.

Calibration 1 - Calibration of NMOS Output Driver

CALIB1_PCAL 

CALIB1 - PCAL.

Calibration 1 - Calibration of PMOS Output Driver

PCR_PS 

PCR - PS.

Pin Control 0..Pin Control 31 - Pull Select

  • [0b0]Enables internal pulldown resistor
  • [0b1]Enables internal pullup resistor
PCR_PE 

PCR - PE.

Pin Control 0..Pin Control 31 - Pull Enable

  • [0b0]Disables
  • [0b1]Enables
PCR_PV 

PCR - PV.

Pin Control 0..Pin Control 31 - Pull Value

  • [0b0]Low
  • [0b1]High
PCR_SRE 

PCR - SRE.

Pin Control 0..Pin Control 31 - Slew Rate Enable

  • [0b0]Fast
  • [0b1]Slow
PCR_PFE 

PCR - PFE.

Pin Control 0..Pin Control 31 - Passive Filter Enable

  • [0b0]Disables
  • [0b1]Enables
PCR_ODE 

PCR - ODE.

Pin Control 0..Pin Control 31 - Open Drain Enable

  • [0b0]Disables
  • [0b1]Enables
PCR_DSE 

PCR - DSE.

Pin Control 0..Pin Control 31 - Drive Strength Enable

  • [0b0]Low
  • [0b1]High
PCR_DSE1 

PCR - DSE1.

Pin Control 0..Pin Control 31 - Drive Strength Enable

  • [0b0]Normal
  • [0b1]Double
PCR_MUX 

PCR - MUX.

Pin Control 0..Pin Control 31 - Pin Multiplex Control

  • [0b0000]Alternative 0 (GPIO)
  • [0b0001]Alternative 1 (chip-specific)
  • [0b0010]Alternative 2 (chip-specific)
  • [0b0011]Alternative 3 (chip-specific)
  • [0b0100]Alternative 4 (chip-specific)
  • [0b0101]Alternative 5 (chip-specific)
  • [0b0110]Alternative 6 (chip-specific)
  • [0b0111]Alternative 7 (chip-specific)
  • [0b1000]Alternative 8 (chip-specific)
  • [0b1001]Alternative 9 (chip-specific)
  • [0b1010]Alternative 10 (chip-specific)
  • [0b1011]Alternative 11 (chip-specific)
  • [0b1100]Alternative 12 (chip-specific)
  • [0b1101]Alternative 13 (chip-specific)
PCR_IBE 

PCR - IBE.

Pin Control 0..Pin Control 31 - Input Buffer Enable

  • [0b0]Disables
  • [0b1]Enables
PCR_INV 

PCR - INV.

Pin Control 0..Pin Control 31 - Invert Input

  • [0b0]Does not invert
  • [0b1]Inverts
PCR_LK 

PCR - LK.

Pin Control 0..Pin Control 31 - Lock Register

  • [0b0]Does not lock
  • [0b1]Locks

◆ Mux

enum struct chip::port::Mux : unsigned char
strong
列舉值
GPIO 

Corresponding pin is configured as GPIO.

ALT0 

Chip-specific

ALT1 

Chip-specific

ALT2 

Chip-specific

ALT3 

Chip-specific

ALT4 

Chip-specific

ALT5 

Chip-specific

ALT6 

Chip-specific

ALT7 

Chip-specific

ALT8 

Chip-specific

ALT9 

Chip-specific

ALT10 

Chip-specific

ALT11 

Chip-specific

ALT12 

Chip-specific

ALT13 

Chip-specific

ALT14 

Chip-specific

ALT15 

Chip-specific

◆ OpenDrain

enum struct chip::port::OpenDrain : bool
strong
列舉值
DISABLE 

Open drain output is disabled.

ENABLE 

Open drain output is enabled.

◆ PassiveFilter

enum struct chip::port::PassiveFilter : bool
strong
列舉值
DISABLE 

Passive input filter is disabled.

ENABLE 

Passive input filter is enabled.

◆ Pull

enum struct chip::port::Pull : unsigned char
strong
列舉值
DISABLE 

Internal pull-up/down resistor is disabled.

DOWN 

Internal pull-down resistor is enabled.

UP 

Internal pull-up resistor is enabled.

◆ PullResistor

enum struct chip::port::PullResistor : bool
strong
列舉值
LOW 

Low internal pull resistor value is selected.

HIGH 

High internal pull resistor value is selected.

◆ Rate

enum struct chip::port::Rate : bool
strong
列舉值
FAST 

Fast slew rate is configured.

SLOW 

Slow slew rate is configured.

◆ Shift

enum struct chip::port::Shift : unsigned int
strong

PORT_Register_Masks PORT Register Shift.

列舉值
VERID_FEATURE 

VERID - FEATURE.

Version ID - Feature Specification Number

  • [0b0000000000000000]Basic implementation
VERID_MINOR 

VERID - MINOR.

Version ID - Minor Version Number

VERID_MAJOR 

VERID - MAJOR.

Version ID - Major Version Number

GPCLR_GPWD 

GPCLR - GPWD.

Global Pin Control Low - Global Pin Write Data

GPCLR_GPWE0 

GPCLR - GPWE0.

Global Pin Control Low - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCLR_GPWE1 

GPCLR - GPWE1.

Global Pin Control Low - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCLR_GPWE2 

GPCLR - GPWE2.

Global Pin Control Low - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCLR_GPWE3 

GPCLR - GPWE3.

Global Pin Control Low - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCLR_GPWE4 

GPCLR - GPWE4.

Global Pin Control Low - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCLR_GPWE5 

GPCLR - GPWE5.

Global Pin Control Low - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCLR_GPWE6 

GPCLR - GPWE6.

Global Pin Control Low - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCLR_GPWE7 

GPCLR - GPWE7.

Global Pin Control Low - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCLR_GPWE8 

GPCLR - GPWE8.

Global Pin Control Low - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCLR_GPWE9 

GPCLR - GPWE9.

Global Pin Control Low - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCLR_GPWE10 

GPCLR - GPWE10.

Global Pin Control Low - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCLR_GPWE11 

GPCLR - GPWE11.

Global Pin Control Low - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCLR_GPWE12 

GPCLR - GPWE12.

Global Pin Control Low - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCLR_GPWE13 

GPCLR - GPWE13.

Global Pin Control Low - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCLR_GPWE14 

GPCLR - GPWE14.

Global Pin Control Low - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCLR_GPWE15 

GPCLR - GPWE15.

Global Pin Control Low - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCHR_GPWD 

GPCHR - GPWD.

Global Pin Control High - Global Pin Write Data

GPCHR_GPWE16 

GPCHR - GPWE16.

Global Pin Control High - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCHR_GPWE17 

GPCHR - GPWE17.

Global Pin Control High - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCHR_GPWE18 

GPCHR - GPWE18.

Global Pin Control High - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCHR_GPWE19 

GPCHR - GPWE19.

Global Pin Control High - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCHR_GPWE20 

GPCHR - GPWE20.

Global Pin Control High - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCHR_GPWE21 

GPCHR - GPWE21.

Global Pin Control High - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCHR_GPWE22 

GPCHR - GPWE22.

Global Pin Control High - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCHR_GPWE23 

GPCHR - GPWE23.

Global Pin Control High - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCHR_GPWE24 

GPCHR - GPWE24.

Global Pin Control High - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCHR_GPWE25 

GPCHR - GPWE25.

Global Pin Control High - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCHR_GPWE26 

GPCHR - GPWE26.

Global Pin Control High - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCHR_GPWE27 

GPCHR - GPWE27.

Global Pin Control High - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCHR_GPWE28 

GPCHR - GPWE28.

Global Pin Control High - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCHR_GPWE29 

GPCHR - GPWE29.

Global Pin Control High - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCHR_GPWE30 

GPCHR - GPWE30.

Global Pin Control High - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
GPCHR_GPWE31 

GPCHR - GPWE31.

Global Pin Control High - Global Pin Write Enable

  • [0b0]Not updated
  • [0b1]Updated
CONFIG_RANGE 

CONFIG - RANGE.

Configuration - Port Voltage Range

  • [0b0]1.71 V-3.6 V
  • [0b1]2.70 V-3.6 V
CALIB0_NCAL 

CALIB0 - NCAL.

Calibration 0 - Calibration of NMOS Output Driver

CALIB0_PCAL 

CALIB0 - PCAL.

Calibration 0 - Calibration of PMOS Output Driver

CALIB1_NCAL 

CALIB1 - NCAL.

Calibration 1 - Calibration of NMOS Output Driver

CALIB1_PCAL 

CALIB1 - PCAL.

Calibration 1 - Calibration of PMOS Output Driver

PCR_PS 

PCR - PS.

Pin Control 0..Pin Control 31 - Pull Select

  • [0b0]Enables internal pulldown resistor
  • [0b1]Enables internal pullup resistor
PCR_PE 

PCR - PE.

Pin Control 0..Pin Control 31 - Pull Enable

  • [0b0]Disables
  • [0b1]Enables
PCR_PV 

PCR - PV.

Pin Control 0..Pin Control 31 - Pull Value

  • [0b0]Low
  • [0b1]High
PCR_SRE 

PCR - SRE.

Pin Control 0..Pin Control 31 - Slew Rate Enable

  • [0b0]Fast
  • [0b1]Slow
PCR_PFE 

PCR - PFE.

Pin Control 0..Pin Control 31 - Passive Filter Enable

  • [0b0]Disables
  • [0b1]Enables
PCR_ODE 

PCR - ODE.

Pin Control 0..Pin Control 31 - Open Drain Enable

  • [0b0]Disables
  • [0b1]Enables
PCR_DSE 

PCR - DSE.

Pin Control 0..Pin Control 31 - Drive Strength Enable

  • [0b0]Low
  • [0b1]High
PCR_DSE1 

PCR - DSE1.

Pin Control 0..Pin Control 31 - Drive Strength Enable

  • [0b0]Normal
  • [0b1]Double
PCR_MUX 

PCR - MUX.

Pin Control 0..Pin Control 31 - Pin Multiplex Control

  • [0b0000]Alternative 0 (GPIO)
  • [0b0001]Alternative 1 (chip-specific)
  • [0b0010]Alternative 2 (chip-specific)
  • [0b0011]Alternative 3 (chip-specific)
  • [0b0100]Alternative 4 (chip-specific)
  • [0b0101]Alternative 5 (chip-specific)
  • [0b0110]Alternative 6 (chip-specific)
  • [0b0111]Alternative 7 (chip-specific)
  • [0b1000]Alternative 8 (chip-specific)
  • [0b1001]Alternative 9 (chip-specific)
  • [0b1010]Alternative 10 (chip-specific)
  • [0b1011]Alternative 11 (chip-specific)
  • [0b1100]Alternative 12 (chip-specific)
  • [0b1101]Alternative 13 (chip-specific)
PCR_IBE 

PCR - IBE.

Pin Control 0..Pin Control 31 - Input Buffer Enable

  • [0b0]Disables
  • [0b1]Enables
PCR_INV 

PCR - INV.

Pin Control 0..Pin Control 31 - Invert Input

  • [0b0]Does not invert
  • [0b1]Inverts
PCR_LK 

PCR - LK.

Pin Control 0..Pin Control 31 - Lock Register

  • [0b0]Does not lock
  • [0b1]Locks

◆ VoltageRange

enum struct chip::port::VoltageRange : bool
strong
列舉值
RANGE_1V71_3V6 

Port voltage range is 1.71 V - 3.6 V.

RANGE_2V70_3V6 

Port voltage range is 2.70 V - 3.6 V.