複合項目
struct	ActiveModeCoreLdoOption
	Active Mode Core LDO Option Configuration. 更多...

struct	ActiveModeRegulatorsConfig
	Active Mode Regulators Configuration. 更多...

struct	CoreVoltageDetectConfig
	Core Voltage Detect Configuration This structure defines the configuration for core voltage detection, including options for high and low voltage detect interrupts and resets. 更多...

struct	LowPowerModeCoreLdoOption
	Low Power Mode Core LDO Option Configuration This structure defines the configuration options for the Core LDO (Low Dropout Regulator) in low power modes. It includes settings for voltage level and drive strength. 更多...

struct	LowPowerModeRegulatorsConfig

struct	LowPowerRequestConfig
	Low Power Request output pin configuration. 更多...

struct	Register
	System Power Controller (SPC) Register Structure. 更多...

class	SPC
	MCXA153 系統電源控制器 (SPC) 管理介面更多...

struct	SramVoltageConfig
	SRAM Voltage Configuration Structure. 更多...

struct	SystemVoltageDetectConfig
	System Voltage Detection Configuration Structure. 更多...

struct	VoltageDetectOption
	Voltage Detection Option Configuration Structure. 更多...

列舉型態
enum struct	AnalogModuleControl : unsigned int { VREF = 1UL << 0UL , USB_3V_DET = 1UL << 1UL , DAC0 = 1UL << 4UL , DAC1 = 1UL << 5UL , DAC2 = 1UL << 6UL , OPAMP0 = 1UL << 8UL , OPAMP1 = 1UL << 9UL , OPAMP2 = 1UL << 10UL , CMP0 = 1UL << 16UL , CMP1 = 1UL << 17UL , CMP2 = 1UL << 18UL , CMP0_DAC = 1UL << 20UL , CMP1_DAC = 1UL << 21UL , CMP2_DAC = 1UL << 22UL , ALL_MODULES = 0x770773UL }

enum struct	BandgapMode : unsigned char { DISABLED = 0x0U , ENABLED_BUFFER_DISABLED = 0x1U , ENABLED_BUFFER_ENABLED = 0x2U , RESERVED = 0x3U }
	Bandgap Mode Enumeration. 更多...

enum struct	CoreLdoDriveStrength : unsigned char { LOW = 0x0U , NORMAL = 0x1U }
	Core LDO Drive Strength Enumeration Enumeration for configuring the drive strength of the Core LDO (Low Dropout Regulator) in active mode. The drive strength affects the current sourcing/sinking capability of the LDO output, which can impact performance and power consumption. Core LDO驅動強度列舉。驅動強度影響LDO輸出電流源/沉能力更多...

enum struct	CoreLdoVoltageLevel : unsigned char { UNDER_DRIVE_VOLTAGE = 0x0U , RETENTION_VOLTAGE = 0x0U , MID_DRIVE_VOLTAGE = 0x1U , NORMAL_VOLTAGE = 0x2U , OVER_DRIVE_VOLTAGE = 0x3U }
	Core LDO Voltage Level Enumeration. 更多...

enum struct	Count : unsigned int { PD_STATUS = 1U }
	SPC Count Enumeration Enumeration for configuring the count of SPC (System Power Controller) status registers. The SPC provides power management and control features for the system, and this enumeration defines the number of status registers available. 更多...

enum struct	LowPowerRequestOutputOverride : unsigned char { Standard , Return , NOT_FORCED = 0x0U , Proper , Safe , RESERVED = 0x1U , External , Custom , Manufacturing , FORCED_LOW = 0x2U , Comprehensive , Complete , Custom , Debug , FORCED_HIGH = 0x3U }
	Low Power Request Output Override Control Options. 更多...

enum struct	LowPowerRequestPinPolarity : unsigned char { Custom , Signal , Supervisory , System , HIGH_TRUE_POLARITY = 0x0U , Standard , Battery-Powered , Industrial , Multi-Supply , Noise-Immune , LOW_TRUE_POLARITY = 0x1U }
	Low Power Request Output Pin Polarity Configuration. 更多...

enum struct	LowVoltageLevelSelect : unsigned char { NORMAL_LEVEL = 0x0U , SAFE_LEVEL = 0x1U , HIGH_RANGE = 0x0U , LOW_RANGE = 0x1U }
	Low Voltage Detection (LVD) Threshold Level Selection. 更多...

enum struct	Mask : unsigned int { VERID_FEATURE = 0x0000FFFFU , VERID_MINOR = 0x00FF0000U , VERID_MAJOR = 0xFF000000U , SC_BUSY = 0x00000001U , SC_SPC_LP_REQ = 0x00000002U , SC_SPC_LP_MODE = 0x000000F0U , SC_ISO_CLR = 0x00010000U , SC_SWITCH_STATE = 0x80000000U , LPREQ_CFG_LPREQOE = 0x00000001U , LPREQ_CFG_LPREQPOL = 0x00000002U , LPREQ_CFG_LPREQOV = 0x0000000CU , CFG_INTG_PWSWTCH_SLEEP_EN = 0x00000001U , CFG_INTG_PWSWTCH_WKUP_EN = 0x00000002U , CFG_INTG_PWSWTCH_SLEEP_ACTIVE_EN = 0x00000004U , CFG_INTG_PWSWTCH_WKUP_ACTIVE_EN = 0x00000008U , PD_STATUS_PWR_REQ_STATUS = 0x00000001U , PD_STATUS_PD_LP_REQ = 0x00000010U , PD_STATUS_LP_MODE = 0x00000F00U , SRAMCTL_VSM = 0x00000003U , SRAMCTL_REQ = 0x40000000U , SRAMCTL_ACK = 0x80000000U , SRAMRETLDO_REFTRIM_REFTRIM = 0x0000001FU , SRAMRETLDO_CNTRL_SRAMLDO_ON = 0x00000001U , SRAMRETLDO_CNTRL_SRAM_RET_EN = 0x00000F00U , ACTIVE_CFG_CORELDO_VDD_DS = 0x00000001U , ACTIVE_CFG_CORELDO_VDD_LVL = 0x0000000CU , ACTIVE_CFG_BGMODE = 0x00300000U , ACTIVE_CFG_VDD_VD_DISABLE = 0x00800000U , ACTIVE_CFG_CORE_LVDE = 0x01000000U , ACTIVE_CFG_SYS_LVDE = 0x02000000U , ACTIVE_CFG_SYS_HVDE = 0x10000000U , ACTIVE_CFG1_SOC_CNTRL = 0xFFFFFFFFU , LP_CFG_CORELDO_VDD_DS = 0x00000001U , LP_CFG_CORELDO_VDD_LVL = 0x0000000CU , LP_CFG_SRAMLDO_DPD_ON = 0x00080000U , LP_CFG_BGMODE = 0x00300000U , LP_CFG_LP_IREFEN = 0x00800000U , LP_CFG_CORE_LVDE = 0x01000000U , LP_CFG_SYS_LVDE = 0x02000000U , LP_CFG_SYS_HVDE = 0x10000000U , LP_CFG1_SOC_CNTRL = 0xFFFFFFFFU , LPWKUP_DELAY_LPWKUP_DELAY = 0x0000FFFFU , ACTIVE_VDELAY_ACTIVE_VDELAY = 0x0000FFFFU , VD_STAT_COREVDD_LVDF = 0x00000001U , VD_STAT_SYSVDD_LVDF = 0x00000002U , VD_STAT_SYSVDD_HVDF = 0x00000020U , VD_CORE_CFG_LVDRE = 0x00000001U , VD_CORE_CFG_LVDIE = 0x00000002U , VD_CORE_CFG_LOCK = 0x00010000U , VD_SYS_CFG_LVDRE = 0x00000001U , VD_SYS_CFG_LVDIE = 0x00000002U , VD_SYS_CFG_HVDRE = 0x00000004U , VD_SYS_CFG_HVDIE = 0x00000008U , VD_SYS_CFG_LVSEL = 0x00000100U , VD_SYS_CFG_LOCK = 0x00010000U , EVD_CFG_EVDISO = 0x00000007U , EVD_CFG_EVDLPISO = 0x00000700U , EVD_CFG_EVDSTAT = 0x00070000U }

enum struct	PowerDomainID : unsigned char { DOMAIN0 = 0U , DOMAIN1 = 1U }
	Power Domain Identifier Enumeration. 更多...

enum struct	PowerDomainLowPowerMode : unsigned char { SLEEP_WITH_SYS_CLOCK_RUNNING = 0U , DEEP_SLEEP_WITH_SYS_CLOCK_OFF = 1U , POWER_DOWN_WITH_SYS_CLOCK_OFF = 2U , DEEP_POWER_DOWN_WITH_SYS_CLOCK_OFF = 4U }
	Power Domain Low Power Mode Enumeration. 更多...

enum struct	PowerDomains : unsigned int { MAIN = 1UL << 16U , WAKE = 1UL << 17U }
	Power Domain Bitmask Enumeration. 更多...

enum struct	Shift : unsigned int { VERID_FEATURE = 0U , VERID_MINOR = 16U , VERID_MAJOR = 24U , SC_BUSY = 0U , SC_SPC_LP_REQ = 1U , SC_SPC_LP_MODE = 4U , SC_ISO_CLR = 16U , SC_SWITCH_STATE = 31U , LPREQ_CFG_LPREQOE = 0U , LPREQ_CFG_LPREQPOL = 1U , LPREQ_CFG_LPREQOV = 2U , CFG_INTG_PWSWTCH_SLEEP_EN = 0U , CFG_INTG_PWSWTCH_WKUP_EN = 1U , CFG_INTG_PWSWTCH_SLEEP_ACTIVE_EN = 2U , CFG_INTG_PWSWTCH_WKUP_ACTIVE_EN = 3U , PD_STATUS_PWR_REQ_STATUS = 0U , PD_STATUS_PD_LP_REQ = 4U , PD_STATUS_LP_MODE = 8U , SRAMCTL_VSM = 0U , SRAMCTL_REQ = 30U , SRAMCTL_ACK = 31U , SRAMRETLDO_REFTRIM_REFTRIM = 0U , SRAMRETLDO_CNTRL_SRAMLDO_ON = 0U , SRAMRETLDO_CNTRL_SRAM_RET_EN = 8U , ACTIVE_CFG_CORELDO_VDD_DS = 0U , ACTIVE_CFG_CORELDO_VDD_LVL = 2U , ACTIVE_CFG_BGMODE = 20U , ACTIVE_CFG_VDD_VD_DISABLE = 23U , ACTIVE_CFG_CORE_LVDE = 24U , ACTIVE_CFG_SYS_LVDE = 25U , ACTIVE_CFG_SYS_HVDE = 28U , ACTIVE_CFG1_SOC_CNTRL = 0U , LP_CFG_CORELDO_VDD_DS = 0U , LP_CFG_CORELDO_VDD_LVL = 2U , LP_CFG_SRAMLDO_DPD_ON = 19U , LP_CFG_BGMODE = 20U , LP_CFG_LP_IREFEN = 23U , LP_CFG_CORE_LVDE = 24U , LP_CFG_SYS_LVDE = 25U , LP_CFG_SYS_HVDE = 28U , LP_CFG1_SOC_CNTRL = 0U , LPWKUP_DELAY_LPWKUP_DELAY = 0U , ACTIVE_VDELAY_ACTIVE_VDELAY = 0U , VD_STAT_COREVDD_LVDF = 0U , VD_STAT_SYSVDD_LVDF = 1U , VD_STAT_SYSVDD_HVDF = 5U , VD_CORE_CFG_LVDRE = 0U , VD_CORE_CFG_LVDIE = 1U , VD_CORE_CFG_LOCK = 16U , VD_SYS_CFG_LVDRE = 0U , VD_SYS_CFG_LVDIE = 1U , VD_SYS_CFG_HVDRE = 2U , VD_SYS_CFG_HVDIE = 3U , VD_SYS_CFG_LVSEL = 8U , VD_SYS_CFG_LOCK = 16U , EVD_CFG_EVDISO = 0U , EVD_CFG_EVDLPISO = 8U , EVD_CFG_EVDSTAT = 16U , EVD_CFG_REG_EVDISO = 0U , EVD_CFG_REG_EVDLPISO = 8U , EVD_CFG_REG_EVDSTAT = 16U }
	SPC (System Power Controller) Register Bit Shift Positions Enumeration defining bit shift positions for accessing specific bit fields within SPC peripheral registers. These shift values are used in conjunction with bit masks to extract or set individual bit fields in the registers. SPC周邊暫存器位元位移位置列舉，用於存取暫存器中特定位元欄位。這些位移值與位元遮罩配合使用，以提取或設定暫存器中的個別位元欄位。更多...

enum struct	SramOperateVoltage : unsigned char { AT_1P0V = 0x1U , AT_1P1V = 0x2U , AT_1P2V = 0x3U }
	SRAM Operating Voltage Enumeration. 更多...

enum struct	Status : unsigned int { SUCCESS = +mcxa153::chip::Status::SUCCESS , FAIL = +mcxa153::chip::Status::FAIL , READONLY = +mcxa153::chip::Status::READONLY , OUT_OF_RANGE = +mcxa153::chip::Status::OUT_OF_RANGE , INVALID_ARGUMENT = +mcxa153::chip::Status::INVALID_ARGUMENT , TIMEOUT = +mcxa153::chip::Status::TIMEOUT , NO_TRANSFER_IN_PROGRESS = +mcxa153::chip::Status::NO_TRANSFER_IN_PROGRESS , BUSY = +mcxa153::chip::Status::BUSY , NO_DATA = +mcxa153::chip::Status::NO_DATA , SPC_BUSY = mcxa153::chip::MAKE_STATUS(mcxa153::chip::StatusGroup::SPC, 0U) , DCDC_LOW_DRIVE_STRENGTH_IGNORE = mcxa153::chip::MAKE_STATUS(mcxa153::chip::StatusGroup::SPC, 1U) , DCDC_PULSE_REFRESH_MODE_IGNORE = mcxa153::chip::MAKE_STATUS(mcxa153::chip::StatusGroup::SPC, 2U) , SYSLDO_OVER_DRIVE_VOLTAGE_FAIL = mcxa153::chip::MAKE_STATUS(mcxa153::chip::StatusGroup::SPC, 3U) , SYSLDO_LOW_DRIVE_STRENGTH_IGNORE = mcxa153::chip::MAKE_STATUS(mcxa153::chip::StatusGroup::SPC, 4U) , CORELDO_LOW_DRIVE_STRENGTH_IGNORE = mcxa153::chip::MAKE_STATUS(mcxa153::chip::StatusGroup::SPC, 5U) , BANDGAP_MODE_WRONG = mcxa153::chip::MAKE_STATUS(mcxa153::chip::StatusGroup::SPC, 6U) , CORELDO_VOLTAGE_WRONG = mcxa153::chip::MAKE_STATUS(mcxa153::chip::StatusGroup::SPC, 7U) , CORELDO_VOLTAGE_SET_FAIL = mcxa153::chip::MAKE_STATUS(mcxa153::chip::StatusGroup::SPC, 8U) }
	System Power Controller (SPC) Status Enumeration. 更多...

enum struct	VoltageDetectFlag : unsigned int { SYSTEM_VDD_HIGH = +Mask::VD_STAT_SYSVDD_HVDF , SYSTEM_VDD_LOW = +Mask::VD_STAT_SYSVDD_LVDF , CORE_VDD_LOW = +Mask::VD_STAT_COREVDD_LVDF }
	Voltage Detection Status Flag Enumeration. 更多...

函式
constexpr unsigned char	operator+ (BandgapMode e)
	Operator Overload - Convert BandgapMode enum to unsigned char.

constexpr unsigned char	operator+ (CoreLdoDriveStrength e)
	Operator Overload - Convert CoreLdoDriveStrength enum to unsigned char.

constexpr unsigned char	operator+ (CoreLdoVoltageLevel e)
	Operator Overload - Convert CoreLdoVoltageLevel enum to unsigned char.

constexpr unsigned int	operator+ (Count e)
	Operator Overload - Convert Count enum to unsigned int.

constexpr unsigned char	operator+ (LowPowerRequestOutputOverride e)

constexpr unsigned char	operator+ (LowPowerRequestPinPolarity e)

constexpr unsigned int	operator+ (Mask e)
	Operator Overload - Convert Mask enum to unsigned int.

constexpr unsigned char	operator+ (PowerDomainID e)

constexpr unsigned int	operator+ (Shift e)
	Unary plus operator overload for Shift enum.

constexpr unsigned char	operator+ (SramOperateVoltage e)

constexpr unsigned int	operator+ (Status e)

變數
Register &	SPC0

詳細描述

SPDX-License-Identifier: MIT

列舉型態說明文件

◆ AnalogModuleControl

enum struct mcxa153::chip::spc::AnalogModuleControl : unsigned int

strong

列舉值
VREF	Enable/disable VREF in active or low-power modes.
USB_3V_DET	Enable/disable USB3V_Det in active or low-power modes.
DAC0	Enable/disable DAC0 in active or low-power modes.
DAC1	Enable/disable DAC1 in active or low-power modes.
DAC2	Enable/disable DAC2 in active or low-power modes.
OPAMP0	Enable/disable OPAMP0 in active or low-power modes.
OPAMP1	Enable/disable OPAMP1 in active or low-power modes.
OPAMP2	Enable/disable OPAMP2 in active or low-power modes.
CMP0	Enable/disable CMP0 in active or low-power modes.
CMP1	Enable/disable CMP1 in active or low-power modes.
CMP2	Enable/disable CMP2 in active or low-power modes.
CMP0_DAC	Enable/disable CMP0_DAC in active or low-power modes.
CMP1_DAC	Enable/disable CMP1_DAC in active or low-power modes.
CMP2_DAC	Enable/disable CMP2_DAC in active or low-power modes. Enable/disable all modules in active or low-power modes.

◆ BandgapMode

enum struct mcxa153::chip::spc::BandgapMode : unsigned char

strong

Bandgap Mode Enumeration.

Enumeration for configuring the bandgap reference voltage mode in the SPC (System Power Control). The bandgap provides a stable reference voltage used for ADC, DAC, and other analog functions. Each mode defines how the bandgap is enabled and whether its output buffer is active.

SPC帶隙參考電壓模式列舉。帶隙提供穩定的參考電壓，用於ADC、DAC和其他類比功能。

DISABLED: Bandgap is turned off, no reference voltage provided
ENABLED_BUFFER_DISABLED: Bandgap is enabled, but output buffer is disabled
ENABLED_BUFFER_ENABLED: Bandgap is enabled with output buffer active
RESERVED: Reserved for future use or specific configurations

自: v1.0.0

列舉值
DISABLED	Bandgap disabled.
ENABLED_BUFFER_DISABLED	Bandgap enabled with Buffer disabled.
ENABLED_BUFFER_ENABLED	Bandgap enabled with Buffer enabled.
RESERVED	Reserved.

◆ CoreLdoDriveStrength

enum struct mcxa153::chip::spc::CoreLdoDriveStrength : unsigned char

strong

Core LDO Drive Strength Enumeration Enumeration for configuring the drive strength of the Core LDO (Low Dropout Regulator) in active mode. The drive strength affects the current sourcing/sinking capability of the LDO output, which can impact performance and power consumption. Core LDO驅動強度列舉。驅動強度影響LDO輸出電流源/沉能力

LOW: Low drive strength, suitable for low power applications
NORMAL: Normal drive strength, provides a balance between performance and power consumption
Used to optimize power consumption and performance in active mode
自
v1.0.0

列舉值
LOW	Core LDO VDD regulator Drive Strength set to low.
NORMAL	Core LDO VDD regulator Drive Strength set to Normal.

◆ CoreLdoVoltageLevel

enum struct mcxa153::chip::spc::CoreLdoVoltageLevel : unsigned char

strong

Core LDO Voltage Level Enumeration.

Enumeration for configuring the voltage level of the Core LDO (Low Dropout Regulator) in active mode. The voltage level affects the performance and power consumption of the core logic.

Core LDO電壓等級列舉。電壓等級影響核心邏輯的性能和功耗。

UNDER_DRIVE_VOLTAGE: Deprecated, use RETENTION_VOLTAGE instead
RETENTION_VOLTAGE: Low voltage for low power modes
MID_DRIVE_VOLTAGE: Normal operating voltage
NORMAL_VOLTAGE: Standard voltage for most operations
OVER_DRIVE_VOLTAGE: High voltage for maximum performance

自: v1.0.0

列舉值
UNDER_DRIVE_VOLTAGE	過時 UNDER_DRIVE_VOLTAGE deprecated to align with description of latest RM please use RETENTION_VOLTAGE as instead.
RETENTION_VOLTAGE	MID_DRIVE_VOLTAGE. Core LDO VDD regulator regulate to retention voltage please note that only useful in low power modes and not all devices support this options please refer to devices' RM for details.
MID_DRIVE_VOLTAGE	MID_DRIVE_VOLTAGE. Core LDO VDD regulator regulate to Mid Drive Voltage
NORMAL_VOLTAGE	NORMAL_VOLTAGE. Core LDO VDD regulator regulate to Normal Voltage.
OVER_DRIVE_VOLTAGE	OVER_DRIVE_VOLTAGE. Core LDO VDD regulator regulate to overdrive Voltage.

◆ Count

enum struct mcxa153::chip::spc::Count : unsigned int

strong

SPC Count Enumeration Enumeration for configuring the count of SPC (System Power Controller) status registers. The SPC provides power management and control features for the system, and this enumeration defines the number of status registers available.

SPC計數列舉。用於配置系統電源控制器(SPC)狀態暫存器的計數。 The SPC提供系統電源管理和控制功能，此列舉定義了可用的狀態暫存器數量。

PD_STATUS: Power Domain Mode Status - The count of SPC_PD_STATUS
Represents the number of power domain status registers available
Used to configure and monitor power domain states in the SPC
Important for power management and system stability
Must be set according to the system's power domain configuration

自: v1.0.0

列舉值

PD_STATUS

PD_STATUS - SPC_PD_STATUS.

SPC Power Domain Mode Status - The count of SPC_PD_STATUS

◆ LowPowerRequestOutputOverride

enum struct mcxa153::chip::spc::LowPowerRequestOutputOverride : unsigned char

strong

Low Power Request Output Override Control Options.

Defines the override control options for the Low Power Request (LPR) output signal in the MCXA153 microcontroller's System Power Controller (SPC). This enumeration allows software to manually control the LPR output state, bypassing the automatic power management hardware control for testing, debugging, and custom power sequencing applications.

MCXA153 低功耗請求輸出覆蓋控制選項，提供手動信號控制能力

Override Control Mechanism: The LPR signal can operate in two primary modes:

Automatic Mode: Hardware automatically controls signal based on power state transitions
Override Mode: Software manually forces signal to specific electrical levels

Override control provides direct electrical level control, bypassing polarity settings and automatic power management logic. This enables precise timing control for complex power management sequences and comprehensive system testing capabilities.

Signal Control Priority: When override is active:

Override setting takes precedence over automatic power management
Polarity configuration is ignored (direct electrical level control)
Power mode transitions do not affect LPR signal state
Manual software control is required to change signal state

Applications and Use Cases:

System Integration Testing: Verify external circuit response to LPR signals
Power Management Debugging: Isolate LPR signal behavior from power mode logic
Custom Power Sequencing: Implement application-specific power control timing
Manufacturing Test: Validate LPR signal integrity and external circuit operation
Emergency Power Control: Manual power management in fault conditions

註

Safety and Reliability Considerations: Override control bypasses automatic power management safety mechanisms and should be used with caution. Inappropriate override usage can cause:

External power management circuit malfunction
System power sequencing failures
Increased power consumption or power management inefficiency
Potential system instability or hardware damage

Development vs Production Usage: Override functionality is primarily intended for:

Development and debugging phases
System integration and validation
Manufacturing test and calibration
Field service and diagnostic procedures

Production code should use override sparingly and with appropriate safety mechanisms.

警告

Critical Usage Guidelines:

Always return to NOT_FORCED mode for normal system operation
Implement timeout mechanisms when using override in production code
Verify external circuit compatibility before applying override
Document override usage for system maintenance and support

列舉值
Standard	Automatic Control Mode (No Override) Configures the Low Power Request output to operate under automatic hardware control based on power management state transitions. In this mode, the LPR signal is controlled by the power management hardware and responds automatically to power mode changes according to the configured polarity settings. 自動控制模式（無覆蓋），LPR信號由硬體功率管理自動控制 Automatic Operation: LPR signal automatically asserts when entering low power modes LPR signal automatically deasserts when exiting low power modes Signal polarity determined by LowPowerRequestPinPolarity configuration Timing synchronized with internal power mode transition sequences No software intervention required during normal power management Hardware Control Benefits: Optimal timing coordination with power mode transitions Minimal software overhead and CPU intervention Consistent and predictable power management signaling Automatic integration with system power management sequences Reduced risk of timing errors in power management coordination 註 Normal Operation Mode: This is the standard operating mode for production systems where reliable, automatic power management coordination is required. The hardware ensures proper timing and sequence coordination between LPR signaling and actual power mode transitions. System Configuration: // Configure for normal automatic operation LowPowerRequestConfig config = { .enable = true, .polarity = LowPowerRequestPinPolarity::ACTIVE_LOW, .override = LowPowerRequestOutputOverride::NOT_FORCED }; // LPR signal will now automatically coordinate with power modes configure_low_power_request(&config); mcxa153::chip::spc::LowPowerRequestConfig Low Power Request output pin configuration. Definition LowPowerRequestConfig.h:200
Return	to Automatic After Testing: // After manual testing, return to automatic operation void restore_automatic_lpr_control() { LowPowerRequestConfig config; get_current_lpr_config(&config); // Ensure automatic mode is restored config.override = LowPowerRequestOutputOverride::NOT_FORCED; configure_low_power_request(&config); log_info("LPR restored to automatic control mode"); } 註 Power Management Integration: In NOT_FORCED mode, the LPR signal timing is optimized for: Proper external circuit setup time before power mode entry Adequate hold time for external circuit response Coordination with internal power management sequences Minimal glitch or timing uncertainty Recommended Usage: Use for all production systems requiring automatic power management Default mode for battery-powered applications Preferred mode for systems with external PMICs Standard configuration for reliable power coordination
Proper	Reserved Configuration Value. This enumeration value is reserved for future functionality or internal hardware use and should not be used in application software. Using this value may result in undefined behavior or may conflict with future hardware implementations. 保留配置值，不應在應用軟體中使用警告 Do Not Use: This value is reserved and must not be used in application code. Using reserved values may cause: Undefined hardware behavior Compatibility issues with future hardware revisions Unpredictable power management operation Potential system instability 註 Future Compatibility: Reserved values may be assigned specific functionality in future hardware revisions or software releases. To maintain forward compatibility, application software should never use reserved enumeration values. Value Validation: bool is_valid_override_value(LowPowerRequestOutputOverride value) { switch (value) { case LowPowerRequestOutputOverride::NOT_FORCED: case LowPowerRequestOutputOverride::FORCED_LOW: case LowPowerRequestOutputOverride::FORCED_HIGH: return true; case LowPowerRequestOutputOverride::RESERVED: default: return false; // Reserved or invalid values } } mcxa153::chip::spc::LowPowerRequestOutputOverride LowPowerRequestOutputOverride Low Power Request Output Override Control Options. Definition LowPowerRequestOutputOverride.h:222
Safe	Configuration Function: bool safe_configure_lpr_override(LowPowerRequestOutputOverride override) { if (override == LowPowerRequestOutputOverride::RESERVED) { log_error("Attempted to use reserved LPR override value"); return false; } // Proceed with valid configuration configure_lpr_override(override); return true; }
External	Force Low Power Request Output to Logic Low Level. Forces the Low Power Request output pin to a logic low electrical level, bypassing automatic power management control and polarity configuration. The pin is driven to approximately 0V regardless of the configured polarity setting, providing direct electrical level control for testing and custom power management sequences. 強制低功耗請求輸出為邏輯低電平，直接電氣控制忽略極性設定 Electrical Behavior: LPR pin driven to logic low level (~0V) Output level independent of polarity configuration Overrides automatic power management hardware control Pin state remains low until override is changed or disabled Provides deterministic electrical level for external circuit testing Override Operation: When FORCED_LOW is active: Power mode transitions do not affect LPR pin state Polarity setting is ignored (direct electrical control) External circuits see consistent logic low signal Manual software control required to change pin state Pin remains low even during power mode changes 註 Testing Applications: FORCED_LOW is particularly useful for: Testing external circuit response to logic low LPR signals Verifying external power management circuit functionality Isolating LPR signal behavior from power mode logic Manufacturing test and system validation procedures Circuit Response Testing: // Test external power management circuit response to low LPR signal void test_external_circuit_low_response() { // Force LPR signal low configure_lpr_override(LowPowerRequestOutputOverride::FORCED_LOW); // Allow time for external circuit to respond delay_ms(external_circuit_response_time); // Measure external circuit behavior ExternalCircuitState state = measure_external_circuit_state(); if (state == EXPECTED_LOW_RESPONSE_STATE) { log_info("External circuit responds correctly to low LPR signal"); } else { log_error("External circuit unexpected response to low LPR signal"); } // Return to automatic control configure_lpr_override(LowPowerRequestOutputOverride::NOT_FORCED); }
Custom	Power Sequence - Prepare External Circuits: // Custom power-down sequence with early LPR assertion void custom_power_down_with_early_lpr() { // Step 1: Force LPR low to prepare external circuits configure_lpr_override(LowPowerRequestOutputOverride::FORCED_LOW); // Step 2: Wait for external circuits to prepare for low power delay_ms(external_preparation_time); // Step 3: Configure system for low power mode prepare_peripherals_for_low_power(); configure_wake_sources(); // Step 4: Enter low power mode (LPR already asserted) enter_low_power_mode(); }
Manufacturing	Test Sequence: // Validate LPR signal integrity and external circuit response bool manufacturing_test_lpr_low() { // Force LPR signal low for testing configure_lpr_override(LowPowerRequestOutputOverride::FORCED_LOW); // Verify electrical level at pin if (!verify_pin_voltage_low(LPR_PIN)) { log_error("LPR pin not driven to low level"); return false; } // Test external circuit response if (!verify_external_circuit_low_response()) { log_error("External circuit does not respond to low LPR signal"); return false; } // Restore automatic operation configure_lpr_override(LowPowerRequestOutputOverride::NOT_FORCED); return true; } 警告 Usage Precautions: May cause external circuits to enter unintended power states Could lead to system power management confusion if used incorrectly Should be followed by return to NOT_FORCED mode for normal operation Test external circuit compatibility before production use 註 External Circuit Considerations: When using FORCED_LOW, consider: External circuit may interpret signal as power management request Some PMICs may respond by changing supply voltages or states Timing requirements for external circuit state changes Potential impact on other system components connected to external circuits
Comprehensive	Force Low Power Request Output to Logic High Level. Forces the Low Power Request output pin to a logic high electrical level, bypassing automatic power management control and polarity configuration. The pin is driven to approximately VDD regardless of the configured polarity setting, providing direct electrical level control for comprehensive testing and specialized power management applications. 強制低功耗請求輸出為邏輯高電平，直接電氣控制忽略極性設定 Electrical Behavior: LPR pin driven to logic high level (~VDD) Output level independent of polarity configuration Overrides automatic power management hardware control Pin state remains high until override is changed or disabled Provides deterministic electrical level for external circuit validation Override Characteristics: When FORCED_HIGH is active: Power mode transitions do not influence LPR pin state Polarity configuration is bypassed (direct electrical control) External circuits receive consistent logic high signal Software must explicitly change override to modify pin state Pin maintains high state across all power management operations 註 Complementary Testing: FORCED_HIGH enables comprehensive testing by providing the opposite electrical state to FORCED_LOW, allowing complete validation of: External circuit response to both signal levels LPR output driver functionality verification System behavior under different LPR signal conditions Power management circuit state machine testing External Circuit Testing: // Test external power management circuit response to high LPR signal void test_external_circuit_high_response() { // Force LPR signal high configure_lpr_override(LowPowerRequestOutputOverride::FORCED_HIGH); // Allow external circuit response time delay_ms(external_circuit_response_time); // Evaluate external circuit state ExternalCircuitState state = measure_external_circuit_state(); if (state == EXPECTED_HIGH_RESPONSE_STATE) { log_info("External circuit responds correctly to high LPR signal"); } else { log_error("External circuit unexpected response to high LPR signal"); } // Restore automatic control configure_lpr_override(LowPowerRequestOutputOverride::NOT_FORCED); }
Complete	LPR Signal Validation: // Comprehensive test of LPR signal functionality bool comprehensive_lpr_test() { bool test_result = true; // Test forced high state configure_lpr_override(LowPowerRequestOutputOverride::FORCED_HIGH); delay_ms(10); if (!verify_pin_voltage_high(LPR_PIN)) { log_error("LPR pin not driven to high level"); test_result = false; } if (!verify_external_circuit_high_response()) { log_error("External circuit does not respond to high LPR signal"); test_result = false; } // Test forced low state configure_lpr_override(LowPowerRequestOutputOverride::FORCED_LOW); delay_ms(10); if (!verify_pin_voltage_low(LPR_PIN)) { log_error("LPR pin not driven to low level"); test_result = false; } // Test automatic mode restoration configure_lpr_override(LowPowerRequestOutputOverride::NOT_FORCED); if (!verify_automatic_lpr_operation()) { log_error("LPR automatic mode not functioning"); test_result = false; } return test_result; }
Custom	Wake-up Sequence: // Custom wake-up sequence with controlled LPR timing void custom_wake_up_sequence() { // System is waking up from low power mode // Step 1: Force LPR high to signal external circuits configure_lpr_override(LowPowerRequestOutputOverride::FORCED_HIGH); // Step 2: Allow external circuits to prepare for active mode delay_ms(external_circuit_wake_time); // Step 3: Complete system wake-up configuration restore_peripheral_states(); reconfigure_clocks_for_active_mode(); // Step 4: Return to automatic LPR control configure_lpr_override(LowPowerRequestOutputOverride::NOT_FORCED); }
Debug	Power Management Coordination: // Debug external power management coordination issues void debug_power_coordination() { log_info("Testing power management coordination"); // Isolate LPR signal from automatic control configure_lpr_override(LowPowerRequestOutputOverride::FORCED_HIGH); // Test system behavior with LPR always high test_system_with_lpr_high(); // Test system behavior with LPR always low configure_lpr_override(LowPowerRequestOutputOverride::FORCED_LOW); test_system_with_lpr_low(); // Compare with automatic behavior configure_lpr_override(LowPowerRequestOutputOverride::NOT_FORCED); test_automatic_power_management(); analyze_power_coordination_results(); } 警告 System Impact Considerations: External circuits may interpret high LPR as specific power management command Some power management systems may respond by enabling high-power modes Could affect system power consumption if external circuits respond to signal May interfere with normal power management sequences if used inappropriately 註 External Circuit Response: When using FORCED_HIGH, external circuits may: Exit low power modes and enter active states Enable additional power supplies or increase voltage levels Activate peripheral devices or communication interfaces Change power management state machines to high-performance modes Signal Integrity: FORCED_HIGH provides maximum signal drive strength for: Overcoming external pull-down resistors Ensuring reliable signal transmission in noisy environments Testing signal integrity under worst-case loading conditions Validating output driver specifications and capabilities

◆ LowPowerRequestPinPolarity

enum struct mcxa153::chip::spc::LowPowerRequestPinPolarity : unsigned char

strong

Low Power Request Output Pin Polarity Configuration.

Defines the electrical polarity options for the Low Power Request (LPR) output signal in the MCXA153 microcontroller's System Power Controller (SPC). This enumeration determines how the LPR signal is interpreted electrically - whether a high voltage level or low voltage level represents the "active" or "request" state for external power management coordination.

MCXA153 低功耗請求輸出引腳極性配置，決定信號的電氣解釋方式

Signal Polarity Concepts: The LPR signal can operate in two fundamental polarity modes:

Active High (High True): Logic high voltage level indicates low power request
Active Low (Low True): Logic low voltage level indicates low power request

Polarity selection must match the input requirements of external power management circuits to ensure proper system-wide power coordination and avoid power management failures or misinterpretation of power state requests.

External Circuit Compatibility: Different external power management circuits expect different signal polarities:

Most Power Management ICs (PMICs) expect active-low signaling
Some supervisory circuits and custom power controllers expect active-high
Industrial power management systems typically use active-low conventions
Legacy systems may have varying polarity requirements

Electrical Characteristics Impact: Polarity selection affects:

Required external pull-up or pull-down resistors
Power consumption in inactive state
Signal integrity and noise immunity characteristics
EMC (Electromagnetic Compatibility) behavior
Fault detection and diagnostic capabilities

註

Power Management Integration: The selected polarity must coordinate with:

External PMIC input polarity requirements
System power sequencing logic
Fault detection and safety circuits
Other system components that monitor the LPR signal

Hardware Design Considerations: Polarity choice influences:

PCB layout and external component requirements
Signal routing and termination strategies
Power consumption optimization
System reliability and fault tolerance

警告

Critical System Compatibility:

Incorrect polarity configuration can cause external circuits to misinterpret power requests
May result in improper power management behavior or system instability
Could lead to power supply issues or damage to external circuits
Always verify polarity requirements with external circuit documentation

列舉值
Custom	Active High Polarity (High True Polarity) Configures the Low Power Request output to use active-high signaling, where a logic high voltage level (typically VDD) on the LPR pin indicates an active low power request to external circuits. When the microcontroller enters low power modes, the LPR signal transitions to logic high to notify external power management circuits of the power state change. 高電平有效極性，邏輯高電平表示低功耗請求狀態 Signal Behavior: Inactive State: LPR pin at logic low level (~0V) Active State: LPR pin at logic high level (~VDD) Low Power Request: Signal transitions from low to high Normal Operation Return: Signal transitions from high to low Electrical Characteristics: In HIGH_TRUE_POLARITY mode: Inactive current consumption depends on external pull-down resistor Active state drives pin to VDD for maximum noise immunity Output driver sources current when active May provide better drive capability for high-impedance loads External Circuit Requirements: Active-high configuration typically requires: External pull-down resistor to ensure defined inactive state Input circuits that interpret high voltage as active condition Compatible power management logic that responds to positive-going edges Adequate noise margins for high-level signal detection 註 Common Applications: HIGH_TRUE_POLARITY is often used with: Custom power management circuits designed for active-high signaling Specialized supervisory circuits expecting positive logic Systems where active-high provides better signal integrity Applications requiring compatibility with TTL logic families Power Management Circuit: // Configure for custom power controller expecting active-high LPR LowPowerRequestConfig config = { .enable = true, .polarity = LowPowerRequestPinPolarity::HIGH_TRUE_POLARITY, .override = LowPowerRequestOutputOverride::NOT_FORCED }; configure_low_power_request(&config); // When entering low power mode: // LPR pin goes HIGH -> External circuit recognizes low power request enter_low_power_mode();
Signal	Integrity Optimization: // Use active-high for better signal integrity in noisy environment void configure_high_noise_immunity_lpr() { LowPowerRequestConfig config; // Active-high provides better noise immunity when active config.polarity = LowPowerRequestPinPolarity::HIGH_TRUE_POLARITY; config.enable = true; config.override = LowPowerRequestOutputOverride::NOT_FORCED; configure_low_power_request(&config); // External pull-down resistor ensures clean inactive state // Active state drives strong high level for noise immunity }
Supervisory	Circuit Integration: // Integration with supervisory circuit expecting active-high void setup_supervisory_circuit_interface() { // Supervisory circuit monitors LPR for system power state LowPowerRequestConfig config = { .enable = true, .polarity = LowPowerRequestPinPolarity::HIGH_TRUE_POLARITY, .override = LowPowerRequestOutputOverride::NOT_FORCED }; configure_low_power_request(&config); // Supervisory circuit interprets: // LOW = System active, normal power management // HIGH = System requesting low power, reduce monitoring frequency }
System	Power Coordination: // Coordinate with multiple external circuits using active-high void coordinate_active_high_power_management() { // Configure LPR for active-high signaling LowPowerRequestConfig config; config.polarity = LowPowerRequestPinPolarity::HIGH_TRUE_POLARITY; config.enable = true; config.override = LowPowerRequestOutputOverride::NOT_FORCED; configure_low_power_request(&config); // System power management sequence prepare_for_low_power_mode(); // LPR goes high, external circuits receive notification enter_low_power_mode(); // LPR -> HIGH // External circuits can: // - Reduce clock frequencies // - Lower supply voltages // - Enter their own low power modes // - Adjust monitoring and control parameters } 警告 External Circuit Compatibility: Ensure external circuits expect and can handle active-high LPR signaling Verify input threshold voltages are compatible with VDD levels Check that external circuits don't misinterpret signal during power-up Validate signal timing meets external circuit setup/hold requirements 註 Power Consumption Considerations: May consume more power when LPR is active (during low power modes) Pull-down resistor value affects inactive state power consumption Consider duty cycle of LPR signal for overall power budget Active state current sourced by microcontroller output driver Design Recommendations: Use external pull-down resistor (10kΩ typical) for defined inactive state Verify signal levels meet external circuit input specifications Consider EMC implications of active-high switching Test signal integrity under all operating conditions
Standard	Active Low Polarity (Low True Polarity) Configures the Low Power Request output to use active-low signaling, where a logic low voltage level (typically 0V) on the LPR pin indicates an active low power request to external circuits. This is the most common polarity configuration in power management applications, as most PMICs and power management circuits expect active-low control signals. 低電平有效極性，邏輯低電平表示低功耗請求狀態，最常見的配置 Signal Behavior: Inactive State: LPR pin at logic high level (~VDD) Active State: LPR pin at logic low level (~0V) Low Power Request: Signal transitions from high to low Normal Operation Return: Signal transitions from low to high Electrical Characteristics: In LOW_TRUE_POLARITY mode: Inactive state typically maintained by external pull-up resistor Active state sinks current to ground through output driver Lower power consumption in inactive state (typical operating condition) Excellent noise immunity due to ground-referenced active state External Circuit Requirements: Active-low configuration typically requires: External pull-up resistor to maintain inactive high state Input circuits that interpret low voltage as active condition Compatible power management logic that responds to negative-going edges Ground-referenced signal detection for active state 註 Industry Standard Configuration: LOW_TRUE_POLARITY is the preferred choice because: Most Power Management ICs (PMICs) expect active-low enable signals Industrial power management systems typically use active-low conventions Better noise immunity (active state is ground-referenced) Lower power consumption in typical inactive state Compatible with open-drain/open-collector signaling PMIC Integration: // Configure for standard PMIC expecting active-low LPR LowPowerRequestConfig config = { .enable = true, .polarity = LowPowerRequestPinPolarity::LOW_TRUE_POLARITY, // Active low .override = LowPowerRequestOutputOverride::NOT_FORCED }; configure_low_power_request(&config); // When entering low power mode: // LPR pin goes LOW -> PMIC recognizes low power request // PMIC may reduce supply voltages, disable unused regulators enter_low_power_mode();
Battery-Powered	System: // Optimize for battery-powered application with PMIC void configure_battery_power_management() { LowPowerRequestConfig config = { .enable = true, .polarity = LowPowerRequestPinPolarity::LOW_TRUE_POLARITY, .override = LowPowerRequestOutputOverride::NOT_FORCED }; configure_low_power_request(&config); // Active-low provides optimal power efficiency: // - Inactive state (most of the time): Pull-up maintains high, low current // - Active state (during sleep): Pin sinks current to ground // - PMIC reduces voltages and currents during active (low) state }
Industrial	Power Management System: // Configure for industrial power management following industry standards void setup_industrial_power_coordination() { // Industrial systems typically use active-low signaling LowPowerRequestConfig config; config.polarity = LowPowerRequestPinPolarity::LOW_TRUE_POLARITY; config.enable = true; config.override = LowPowerRequestOutputOverride::NOT_FORCED; configure_low_power_request(&config); // External industrial power management interprets: // HIGH = Normal operation, full power available // LOW = Low power request, reduce system power consumption }
Multi-Supply	System Coordination: // Coordinate multiple power supplies using active-low LPR void coordinate_multi_supply_system() { // Configure active-low for compatibility with multiple PMICs LowPowerRequestConfig config = { .enable = true, .polarity = LowPowerRequestPinPolarity::LOW_TRUE_POLARITY, .override = LowPowerRequestOutputOverride::NOT_FORCED }; configure_low_power_request(&config); // Power management sequence coordination: prepare_peripherals_for_low_power(); // LPR goes low, multiple external circuits respond: enter_low_power_mode(); // LPR -> LOW // External power supplies can: // - Core voltage PMIC: Reduce CPU core voltage // - I/O voltage PMIC: Maintain or reduce I/O supply // - Peripheral power switches: Disable unused peripherals // - Clock generators: Reduce or disable high-frequency clocks }
Noise-Immune	Power Management: // Leverage active-low for maximum noise immunity void configure_noise_immune_power_management() { LowPowerRequestConfig config; // Active-low provides excellent noise immunity config.polarity = LowPowerRequestPinPolarity::LOW_TRUE_POLARITY; config.enable = true; config.override = LowPowerRequestOutputOverride::NOT_FORCED; configure_low_power_request(&config); // Benefits of active-low in noisy environments: // - Active state is ground-referenced (0V) - immune to VDD noise // - Inactive state maintained by pull-up - resistant to ground bounce // - External circuits can use Schmitt trigger inputs for hysteresis // - Less susceptible to EMI-induced false triggering } 註 PMIC Compatibility: Most commercial PMICs expect active-low enable/control signals: Texas Instruments power management ICs Analog Devices power management solutions Maxim Integrated power management devices STMicroelectronics power management circuits Power Optimization Benefits: LOW_TRUE_POLARITY provides power advantages: Inactive state (majority of operation time): Low current through pull-up Active state (during low power modes): Pin sinks current, PMIC reduces power External pull-up can be optimized for power vs. speed trade-off Compatible with power-gating and supply sequencing schemes 警告 External Component Requirements: Requires external pull-up resistor (typical values: 10kΩ - 100kΩ) Pull-up resistor value affects signal rise time and power consumption Verify external circuit input current requirements Ensure adequate current sink capability for reliable low state 註 Design Recommendations: Use external pull-up resistor appropriate for application speed requirements Verify VDD - 0.4V meets external circuit high-level input requirements Test signal integrity with actual external circuit loading Consider using Schmitt trigger inputs on external circuits for noise immunity Document pull-up resistor value selection rationale for maintenance

◆ LowVoltageLevelSelect

enum struct mcxa153::chip::spc::LowVoltageLevelSelect : unsigned char

strong

Low Voltage Detection (LVD) Threshold Level Selection.

Defines the threshold voltage levels for Low Voltage Detection functionality in the MCXA153 microcontroller's System Power Controller (SPC). LVD monitoring provides early warning and protection against supply voltage drops that could cause system malfunction or data corruption.

MCXA153 低電壓檢測閾值電平選擇，提供電源電壓監控保護

LVD System Overview: The Low Voltage Detection system continuously monitors supply voltage and generates warnings or resets when voltage drops below configured thresholds. Different threshold ranges allow optimization for various supply voltage scenarios and safety requirements.

Threshold Ranges:

High Range: Higher voltage thresholds for early warning and proactive response
Low Range: Lower voltage thresholds for critical protection and system safety

註

Voltage Monitoring Applications:

Battery voltage monitoring in portable devices
Power supply failure detection in industrial systems
Brown-out protection for data integrity
System safety monitoring in critical applications

警告

Critical System Function: Incorrect LVD configuration may result in:

Premature system shutdowns or resets
Insufficient protection against voltage drops
System instability during power fluctuations
Data corruption in low voltage conditions

參閱: System Power Controller (SPC) for complete power monitoring functionality; Low Power Modes for power management integration

列舉值
NORMAL_LEVEL	Normal Level Threshold (Deprecated) 過時 Use HIGH_RANGE instead for new designs Legacy enumeration value maintained for backward compatibility. Equivalent to HIGH_RANGE threshold configuration. 正常電平閾值（已棄用），請使用 HIGH_RANGE 替代
SAFE_LEVEL	Safe Level Threshold (Deprecated) 過時 Use LOW_RANGE instead for new designs Legacy enumeration value maintained for backward compatibility. Equivalent to LOW_RANGE threshold configuration. 安全電平閾值（已棄用），請使用 LOW_RANGE 替代
HIGH_RANGE	High Range LVD Threshold. Configures Low Voltage Detection to use higher threshold voltages for early warning and proactive power management. Provides advance notice of voltage drops before they become critical, allowing system to take preventive actions. 高範圍低電壓檢測閾值，提供早期警告和主動電源管理 Characteristics: Higher voltage thresholds for early detection Suitable for proactive power management strategies Provides margin for graceful system response Ideal for battery-powered applications requiring advance warning 註 Applications: Battery voltage monitoring with early warning Proactive power management systems Systems requiring graceful shutdown procedures Applications with critical data preservation requirements
LOW_RANGE	Low Range LVD Threshold. Configures Low Voltage Detection to use lower threshold voltages for critical protection and system safety. Triggers alerts or resets only when voltage drops approach levels that could cause system malfunction or data corruption. 低範圍低電壓檢測閾值，提供關鍵保護和系統安全 Characteristics: Lower voltage thresholds for critical protection Minimizes false alarms from temporary voltage fluctuations Provides last-line protection against system failure Suitable for systems with stable power supplies 註 Applications: Critical protection in stable power environments Systems with minimal power management requirements Industrial applications with regulated power supplies Cost-sensitive designs requiring basic protection

◆ Mask

enum struct mcxa153::chip::spc::Mask : unsigned int

strong

列舉值
VERID_FEATURE	VERID - FEATURE. Version ID - Feature Specification Number [0b0000000000000000..Standard features *..
VERID_MINOR	VERID - MINOR. Version ID - Minor Version Number
VERID_MAJOR	VERID - MAJOR. Version ID - Major Version Number
SC_BUSY	SC - BUSY. Status Control - SPC Busy Status Flag [0b0]Not busy [0b1]Busy
SC_SPC_LP_REQ	SC - SPC_LP_REQ. Status Control - SPC Power Mode Configuration Status Flag [0b0]SPC is in Active mode; the ACTIVE_CFG register has control [0b1]All power domains requested low-power mode; SPC entered a low-power state; power-mode configuration based on the LP_CFG register [0b0]No effect [0b1]Clear the flag
SC_SPC_LP_MODE	SC - SPC_LP_MODE. Status Control - Power Domain Low-Power Mode Request [0b0000]Sleep mode with system clock running [0b0001]DSLEEP with system clock off [0b0010]PDOWN with system clock off [0b0100] [0b1000]DPDOWN with system clock off
SC_ISO_CLR	SC - ISO_CLR. Status Control - Isolation Clear Flags
SC_SWITCH_STATE	SC - SWITCH_STATE. Status Control - Power Switch State [0b0]Off [0b1]On
LPREQ_CFG_LPREQOE	LPREQ_CFG - LPREQOE. Low-Power Request Configuration - Low-Power Request Output Enable [0b0]Disable [0b1]Enable
LPREQ_CFG_LPREQPOL	LPREQ_CFG - LPREQPOL. Low-Power Request Configuration - Low-Power Request Output Pin Polarity Control [0b0]High [0b1]Low
LPREQ_CFG_LPREQOV	LPREQ_CFG - LPREQOV. Low-Power Request Configuration - Low-Power Request Output Override [0b00]Not forced [0b01] [0b10]Forced low (ignore LPREQPOL settings) [0b11]Forced high (ignore LPREQPOL settings)
CFG_INTG_PWSWTCH_SLEEP_EN	CFG - INTG_PWSWTCH_SLEEP_EN. SPC Configuration - Integrated Power Switch Sleep Enable [0b0]Disable [0b1]Enable
CFG_INTG_PWSWTCH_WKUP_EN	CFG - INTG_PWSWTCH_WKUP_EN. SPC Configuration - Integrated Power Switch Wake-up Enable [0b0]Disable [0b1]Enable
CFG_INTG_PWSWTCH_SLEEP_ACTIVE_EN	CFG - INTG_PWSWTCH_SLEEP_ACTIVE_EN. SPC Configuration - Integrated Power Switch Active Enable [0b0]Disable [0b1]Enable
CFG_INTG_PWSWTCH_WKUP_ACTIVE_EN	CFG - INTG_PWSWTCH_WKUP_ACTIVE_EN. SPC Configuration - Integrated Power Switch Wake-up Enable [0b0]Disable [0b1]Enable
PD_STATUS_PWR_REQ_STATUS	PD_STATUS - PWR_REQ_STATUS. SPC Power Domain Mode Status - Power Request Status Flag [0b0]Did not request [0b1]Requested
PD_STATUS_PD_LP_REQ	PD_STATUS - PD_LP_REQ. SPC Power Domain Mode Status - Power Domain Low Power Request Flag [0b0]Did not request [0b1]Requested
PD_STATUS_LP_MODE	PD_STATUS - LP_MODE. SPC Power Domain Mode Status - Power Domain Low Power Mode Request [0b0000]SLEEP with system clock running [0b0001]DSLEEP with system clock off [0b0010]PDOWN with system clock off [0b0100] [0b1000]DPDOWN with system clock off
SRAMCTL_VSM	SRAMCTL - VSM. SRAM Control - Voltage Select Margin [0b00] [0b01]1.0 V [0b10]1.1 V [0b11]SRAM configured for 1.2 V operation
SRAMCTL_REQ	SRAMCTL - REQ. SRAM Control - SRAM Voltage Update Request [0b0]Do not request [0b1]Request
SRAMCTL_ACK	SRAMCTL - ACK. SRAM Control - SRAM Voltage Update Request Acknowledge [0b0]Not acknowledged [0b1]Acknowledged
SRAMRETLDO_REFTRIM_REFTRIM	SRAMRETLDO_REFTRIM - REFTRIM. SRAM Retention Reference Trim - Reference Trim. Voltage range is around 0.48V - 0.85V. Trim step is 12 mV.
SRAMRETLDO_CNTRL_SRAMLDO_ON	SRAMRETLDO_CNTRL - SRAMLDO_ON. SRAM Retention LDO Control - SRAM LDO Regulator Enable [0b0]Disable [0b1]Enable
SRAMRETLDO_CNTRL_SRAM_RET_EN	SRAMRETLDO_CNTRL - SRAM_RET_EN. SRAM Retention LDO Control - SRAM Retention
ACTIVE_CFG_CORELDO_VDD_DS	ACTIVE_CFG - CORELDO_VDD_DS. Active Power Mode Configuration - LDO_CORE VDD Drive Strength [0b0]Low [0b1]Normal
ACTIVE_CFG_CORELDO_VDD_LVL	ACTIVE_CFG - CORELDO_VDD_LVL. Active Power Mode Configuration - LDO_CORE VDD Regulator Voltage Level [0b00] [0b01]Regulate to mid voltage (1.0 V) [0b10]Regulate to normal voltage (1.1 V) [0b11]Regulate to overdrive voltage (1.15 V)
ACTIVE_CFG_BGMODE	ACTIVE_CFG - BGMODE. Active Power Mode Configuration - Bandgap Mode [0b00]Bandgap disabled [0b01]Bandgap enabled, buffer disabled [0b10]Bandgap enabled, buffer enabled [0b11]
ACTIVE_CFG_VDD_VD_DISABLE	ACTIVE_CFG - VDD_VD_DISABLE. Active Power Mode Configuration - VDD Voltage Detect Disable [0b0]Enable [0b1]Disable
ACTIVE_CFG_CORE_LVDE	ACTIVE_CFG - CORE_LVDE. Active Power Mode Configuration - Core Low-Voltage Detection Enable [0b0]Disable [0b1]Enable
ACTIVE_CFG_SYS_LVDE	ACTIVE_CFG - SYS_LVDE. Active Power Mode Configuration - System Low-Voltage Detection Enable [0b0]Disable [0b1]Enable
ACTIVE_CFG_SYS_HVDE	ACTIVE_CFG - SYS_HVDE. Active Power Mode Configuration - System High-Voltage Detection Enable [0b0]Disable [0b1]Enable
ACTIVE_CFG1_SOC_CNTRL	ACTIVE_CFG1 - SOC_CNTRL. Active Power Mode Configuration 1 - Active Config Chip Control
LP_CFG_CORELDO_VDD_DS	LP_CFG - CORELDO_VDD_DS. Low-Power Mode Configuration - LDO_CORE VDD Drive Strength [0b0]Low [0b1]Normal
LP_CFG_CORELDO_VDD_LVL	LP_CFG - CORELDO_VDD_LVL. Low-Power Mode Configuration - LDO_CORE VDD Regulator Voltage Level [0b00]Reserved [0b01]Mid voltage (1.0 V) [0b10]Normal voltage (1.1 V) [0b11]Overdrive voltage (1.15 V) *]
LP_CFG_SRAMLDO_DPD_ON	LP_CFG - SRAMLDO_DPD_ON. Low-Power Mode Configuration - SRAM_LDO Deep Power Low Power IREF Enable [0b0]Low Power IREF is disabled for power saving in Deep Power Down mode [0b1]Low Power IREF is enabled
LP_CFG_BGMODE	LP_CFG - BGMODE. Low-Power Mode Configuration - Bandgap Mode [0b00]Bandgap disabled [0b01]Bandgap enabled, buffer disabled [0b10]Bandgap enabled, buffer enabled [0b11]
LP_CFG_LP_IREFEN	LP_CFG - LP_IREFEN. Low-Power Mode Configuration - Low-Power IREF Enable [0b0]Disable for power saving in Deep Power Down mode [0b1]Enable
LP_CFG_CORE_LVDE	LP_CFG - CORE_LVDE. Low-Power Mode Configuration - Core Low Voltage Detect Enable [0b0]Disable [0b1]Enable
LP_CFG_SYS_LVDE	LP_CFG - SYS_LVDE. Low-Power Mode Configuration - System Low Voltage Detect Enable [0b0]Disable [0b1]Enable
LP_CFG_SYS_HVDE	LP_CFG - SYS_HVDE. Low-Power Mode Configuration - System High Voltage Detect Enable [0b0]Disable [0b1]Enable
LP_CFG1_SOC_CNTRL	LP_CFG1 - SOC_CNTRL. Low Power Mode Configuration 1 - Low-Power Configuration Chip Control
LPWKUP_DELAY_LPWKUP_DELAY	LPWKUP_DELAY - LPWKUP_DELAY. Low Power Wake-Up Delay - Low-Power Wake-Up Delay
ACTIVE_VDELAY_ACTIVE_VDELAY	ACTIVE_VDELAY - ACTIVE_VDELAY. Active Voltage Trim Delay - Active Voltage Delay
VD_STAT_COREVDD_LVDF	VD_STAT - COREVDD_LVDF. Voltage Detect Status - Core Low-Voltage Detect Flag [0b0]Event not detected [0b1]Event detected [0b0]No effect [0b1]Clear the flag
VD_STAT_SYSVDD_LVDF	VD_STAT - SYSVDD_LVDF. Voltage Detect Status - System Low-Voltage Detect Flag [0b0]Event not detected [0b1]Event detected [0b0]No effect [0b1]Clear the flag
VD_STAT_SYSVDD_HVDF	VD_STAT - SYSVDD_HVDF. Voltage Detect Status - System HVD Flag [0b0]Event not detected [0b1]Event detected [0b0]No effect [0b1]Clear the flag
VD_CORE_CFG_LVDRE	VD_CORE_CFG - LVDRE. Core Voltage Detect Configuration - Core LVD Reset Enable [0b0]Disable [0b1]Enable
VD_CORE_CFG_LVDIE	VD_CORE_CFG - LVDIE. Core Voltage Detect Configuration - Core LVD Interrupt Enable [0b0]Disable [0b1]Enable
VD_CORE_CFG_LOCK	VD_CORE_CFG - LOCK. Core Voltage Detect Configuration - Core Voltage Detect Reset Enable Lock [0b0]Allow [0b1]Deny
VD_SYS_CFG_LVDRE	VD_SYS_CFG - LVDRE. System Voltage Detect Configuration - System LVD Reset Enable [0b0]Disable [0b1]Enable
VD_SYS_CFG_LVDIE	VD_SYS_CFG - LVDIE. System Voltage Detect Configuration - System LVD Interrupt Enable [0b0]Disable [0b1]Enable
VD_SYS_CFG_HVDRE	VD_SYS_CFG - HVDRE. System Voltage Detect Configuration - System HVD Reset Enable [0b0]Disable [0b1]Enable
VD_SYS_CFG_HVDIE	VD_SYS_CFG - HVDIE. System Voltage Detect Configuration - System HVD Interrupt Enable [0b0]Disable [0b1]Enable
VD_SYS_CFG_LVSEL	VD_SYS_CFG - LVSEL. System Voltage Detect Configuration - System Low-Voltage Level Select [0b0]Normal [0b1]Safe
VD_SYS_CFG_LOCK	VD_SYS_CFG - LOCK. System Voltage Detect Configuration - System Voltage Detect Reset Enable Lock [0b0]Allow [0b1]Deny
EVD_CFG_EVDISO	EVD_CFG - EVDISO. External Voltage Domain Configuration - External Voltage Domain Isolation
EVD_CFG_EVDLPISO	EVD_CFG - EVDLPISO. External Voltage Domain Configuration - External Voltage Domain Low-Power Isolation
EVD_CFG_EVDSTAT	EVD_CFG - EVDSTAT. External Voltage Domain Configuration - External Voltage Domain Status

範例: F:/mframe/doxy-document/src/mcxa153/src/mcxa153/chip/spc/Mask.h.

◆ PowerDomainID

enum struct mcxa153::chip::spc::PowerDomainID : unsigned char

strong

Power Domain Identifier Enumeration.

Defines identifiers for independent power domains within the MCXA153 microcontroller. Each power domain can be independently controlled, monitored, and configured for optimal power management across different functional blocks of the system.

電源域識別符枚舉，定義 MCXA153 微控制器內的獨立電源域

Power Domain Characteristics:

Independent voltage regulation for each domain
Selective power-down capability for unused functional blocks
Fine-grained power management control
Chip-specific functional block assignments

註

Usage Considerations:

Power domain mapping is device-specific and may vary between chip variants
Proper sequencing required when powering domains on/off
Some functional blocks may span multiple power domains
Always verify domain assignments in device documentation

參閱: SPC registers for power domain control implementation; Device Reference Manual for specific functional block assignments

列舉值

DOMAIN0

Power Domain 0 Identifier.

Represents the first power domain in the MCXA153 power management system. The specific functional blocks assigned to this domain are chip-specific and defined in the device reference manual.

電源域 0 識別符，代表 MCXA153 電源管理系統中的第一個電源域

Domain 0 Characteristics:

Primary power domain for core system functions
May include essential peripherals and memory blocks
Typically remains active during most low power modes
Critical for basic system operation

註

Applications:

Core processor and memory power management
Essential peripheral power control
System-critical functional blocks
Always-on or semi-always-on components

警告: The exact functional block assignment is chip-specific. Refer to device documentation for precise domain mapping.

DOMAIN1

Power Domain 1 Identifier.

Represents the second power domain in the MCXA153 power management system. This domain typically controls auxiliary or optional functional blocks that can be powered down independently for power optimization.

電源域 1 識別符，代表 MCXA153 電源管理系統中的第二個電源域

Domain 1 Characteristics:

Secondary power domain for auxiliary functions
Often includes optional or application-specific peripherals
Can be independently powered down for energy savings
Suitable for conditional power management strategies

註

Applications:

Optional peripheral power management
Application-specific functional blocks
Power-optimized system designs
Conditional feature enablement

警告: The exact functional block assignment is chip-specific. Verify domain contents before implementing power management strategies.

◆ PowerDomainLowPowerMode

enum struct mcxa153::chip::spc::PowerDomainLowPowerMode : unsigned char

strong

Power Domain Low Power Mode Enumeration.

Defines available low power modes for individual power domains within the MCXA153 microcontroller. Each mode provides different levels of power reduction with corresponding trade-offs in wake-up time and system functionality preservation.

電源域低功耗模式枚舉，定義各個電源域可用的低功耗模式

Power Mode Hierarchy (lowest to highest power savings):

SLEEP - Light sleep with system clock running
DEEP_SLEEP - Deep sleep with system clock disabled
POWER_DOWN - Power down with additional circuit shutdown
DEEP_POWER_DOWN - Maximum power savings with extensive shutdown

註

Mode Selection Considerations:

Higher power savings typically require longer wake-up times
System clock status affects overall system responsiveness
Power domain interdependencies may limit available modes
Wake-up source availability varies by power mode

參閱: SPC registers for power mode control implementation; Wake-up sources documentation for mode-specific limitations

列舉值
SLEEP_WITH_SYS_CLOCK_RUNNING	Sleep Mode with System Clock Running. Light sleep mode where the power domain enters a low power state while maintaining the system clock. This provides minimal power savings with fastest wake-up response time. 保持系統時鐘運行的睡眠模式，提供最快的喚醒響應時間 Mode Characteristics: System clock continues running Fastest wake-up time among all modes Minimal power reduction Full system responsiveness maintained All wake-up sources remain active 註 Applications: Short idle periods Real-time systems requiring quick response Applications with frequent interrupts Systems requiring continuous timing accuracy
DEEP_SLEEP_WITH_SYS_CLOCK_OFF	Deep Sleep Mode with System Clock Off. Medium power savings mode where the power domain enters deep sleep with the system clock disabled. Provides balanced power savings and wake-up time. 系統時鐘關閉的深度睡眠模式，提供平衡的功耗節省和喚醒時間 Mode Characteristics: System clock is disabled Moderate power savings Medium wake-up time due to clock restart Limited wake-up sources may be available Timing accuracy lost during sleep 註 Applications: Medium-duration idle periods Battery-powered applications Systems with predictable wake-up requirements Applications tolerating clock restart delays
POWER_DOWN_WITH_SYS_CLOCK_OFF	Power Down Mode with System Clock Off. High power savings mode where the power domain is powered down with system clock disabled. Additional circuits are shut down for increased power efficiency. 系統時鐘關閉的斷電模式，額外電路關閉以提高功耗效率 Mode Characteristics: System clock disabled Additional circuit shutdown for higher power savings Longer wake-up time due to circuit restoration Reduced wake-up source availability State preservation may be limited 註 Applications: Long idle periods Battery-critical applications Seasonal or periodic operation systems Applications with external wake-up triggers
DEEP_POWER_DOWN_WITH_SYS_CLOCK_OFF	Deep Power Down Mode with System Clock Off. Maximum power savings mode where the power domain enters the deepest low power state. Extensive circuit shutdown provides maximum power efficiency at the cost of longest wake-up time. 系統時鐘關閉的深度斷電模式，提供最大功耗效率和最長喚醒時間 Mode Characteristics: Maximum power savings available Extensive circuit shutdown Longest wake-up time among all modes Very limited wake-up sources Significant state loss possible May require system reinitializatio 註 Applications: Extended dormant periods (hours/days) Ultra-low power battery applications Emergency power conservation Long-term storage or shipping modes 警告 Extended wake-up sequence may be required. Verify wake-up source compatibility before use.

◆ PowerDomains

enum struct mcxa153::chip::spc::PowerDomains : unsigned int

strong

Power Domain Bitmask Enumeration.

Defines bitmask values for power domains within the MCXA153 microcontroller. These values are used to identify and control specific power domains through bitwise operations in power management registers.

電源域位掩碼枚舉，定義 MCXA153 微控制器內的電源域位掩碼值

Domain Organization:

MAIN Domain: Contains most peripherals and general-purpose IO pads
WAKE Domain: Contains wake-up capable peripherals and always-on functions
Bitmask design allows multiple domain selection through bitwise OR
Each domain can be independently controlled for power optimization

註

Usage Patterns:

Use single values for individual domain control
Combine with bitwise OR for multi-domain operations
Check specific domain status with bitwise AND
Essential for power state retention during low power modes

參閱: PowerDomainID for domain identification; PowerDomainLowPowerMode for power mode selection; SPC registers for power domain control implementation

列舉值

MAIN

Main Power Domain Bitmask.

Bitmask for the main power domain containing most system peripherals and general-purpose IO pads. This domain typically includes non-critical peripherals that can be powered down during low power modes.

主電源域位掩碼，包含大部分系統外設和通用 IO 焊盤

MAIN Domain Characteristics:

Contains majority of system peripherals
Includes general-purpose IO pads and pin multiplexing
Can be powered down during deep sleep modes
Non-essential for basic wake-up functionality
Optimized for operational power efficiency

註

Typical Contents:

Communication peripherals (UART, SPI, I2C)
Timer peripherals (excluding always-on timers)
ADC and DAC peripherals
General-purpose IO pins and multiplexers
DMA controllers and memory interfaces

警告: Powering down this domain will disable most system functionality. Ensure proper wake-up mechanisms are configured before entering low power modes.

WAKE

Wake Power Domain Bitmask.

Bitmask for the wake power domain containing wake-up capable peripherals and always-on functions. This domain remains active during most low power modes to enable system wake-up and maintain critical functions.

喚醒電源域位掩碼，包含具有喚醒能力的外設和常開功能

WAKE Domain Characteristics:

Contains wake-up capable peripherals
Remains active during most low power modes
Includes always-on timers and clock sources
Essential for system wake-up functionality
Optimized for low power consumption during sleep

註

Typical Contents:

Real-time clock (RTC) and low power timers
Wake-up interrupt controllers
Low power oscillators and clock sources
Essential power management circuits
Wake-up capable IO pins and interrupt sources

警告: This domain should typically remain powered to ensure proper wake-up functionality. Powering down may prevent system wake-up.

◆ Shift

enum struct mcxa153::chip::spc::Shift : unsigned int

strong

SPC (System Power Controller) Register Bit Shift Positions Enumeration defining bit shift positions for accessing specific bit fields within SPC peripheral registers. These shift values are used in conjunction with bit masks to extract or set individual bit fields in the registers. SPC周邊暫存器位元位移位置列舉，用於存取暫存器中特定位元欄位。這些位移值與位元遮罩配合使用，以提取或設定暫存器中的個別位元欄位。

Used with bitwise shift operations (<<, >>) for bit field manipulation
Combined with masks for register read/write operations
All values represent bit positions within 32-bit registers
Shift positions are zero-based (0 = LSB, 31 = MSB)
註
Use these values with corresponding masks from Mask.h

Example: (register_value >> shift_position) & field_mask

自
v1.0.0

列舉值
VERID_FEATURE	VERID - FEATURE. Version ID - Feature Specification Number [0b0000000000000000..Standard features *..
VERID_MINOR	VERID - MINOR. Version ID - Minor Version Number
VERID_MAJOR	VERID - MAJOR. Version ID - Major Version Number
SC_BUSY	SC - BUSY. Status Control - SPC Busy Status Flag [0b0]Not busy [0b1]Busy
SC_SPC_LP_REQ	SC - SPC_LP_REQ. Status Control - SPC Power Mode Configuration Status Flag [0b0]SPC is in Active mode; the ACTIVE_CFG register has control [0b1]All power domains requested low-power mode; SPC entered a low-power state; power-mode configuration based on the LP_CFG register [0b0]No effect [0b1]Clear the flag
SC_SPC_LP_MODE	SC - SPC_LP_MODE. Status Control - Power Domain Low-Power Mode Request [0b0000]Sleep mode with system clock running [0b0001]DSLEEP with system clock off [0b0010]PDOWN with system clock off [0b0100] [0b1000]DPDOWN with system clock off
SC_ISO_CLR	SC - ISO_CLR. Status Control - Isolation Clear Flags
SC_SWITCH_STATE	SC - SWITCH_STATE. Status Control - Power Switch State [0b0]Off [0b1]On
LPREQ_CFG_LPREQOE	LPREQ_CFG - LPREQOE. Low-Power Request Configuration - Low-Power Request Output Enable [0b0]Disable [0b1]Enable
LPREQ_CFG_LPREQPOL	LPREQ_CFG - LPREQPOL. Low-Power Request Configuration - Low-Power Request Output Pin Polarity Control [0b0]High [0b1]Low
LPREQ_CFG_LPREQOV	LPREQ_CFG - LPREQOV. Low-Power Request Configuration - Low-Power Request Output Override [0b00]Not forced [0b01] [0b10]Forced low (ignore LPREQPOL settings) [0b11]Forced high (ignore LPREQPOL settings)
CFG_INTG_PWSWTCH_SLEEP_EN	CFG - INTG_PWSWTCH_SLEEP_EN. SPC Configuration - Integrated Power Switch Sleep Enable [0b0]Disable [0b1]Enable
CFG_INTG_PWSWTCH_WKUP_EN	CFG - INTG_PWSWTCH_WKUP_EN. SPC Configuration - Integrated Power Switch Wake-up Enable [0b0]Disable [0b1]Enable
CFG_INTG_PWSWTCH_SLEEP_ACTIVE_EN	CFG - INTG_PWSWTCH_SLEEP_ACTIVE_EN. SPC Configuration - Integrated Power Switch Active Enable [0b0]Disable [0b1]Enable
CFG_INTG_PWSWTCH_WKUP_ACTIVE_EN	CFG - INTG_PWSWTCH_WKUP_ACTIVE_EN. SPC Configuration - Integrated Power Switch Wake-up Enable [0b0]Disable [0b1]Enable
PD_STATUS_PWR_REQ_STATUS	PD_STATUS - PWR_REQ_STATUS. SPC Power Domain Mode Status - Power Request Status Flag [0b0]Did not request [0b1]Requested
PD_STATUS_PD_LP_REQ	PD_STATUS - PD_LP_REQ. SPC Power Domain Mode Status - Power Domain Low Power Request Flag [0b0]Did not request [0b1]Requested
PD_STATUS_LP_MODE	PD_STATUS - LP_MODE. SPC Power Domain Mode Status - Power Domain Low Power Mode Request [0b0000]SLEEP with system clock running [0b0001]DSLEEP with system clock off [0b0010]PDOWN with system clock off [0b0100] [0b1000]DPDOWN with system clock off
SRAMCTL_VSM	SRAMCTL - VSM. SRAM Control - Voltage Select Margin [0b00] [0b01]1.0 V [0b10]1.1 V [0b11]SRAM configured for 1.2 V operation
SRAMCTL_REQ	SRAMCTL - REQ. SRAM Control - SRAM Voltage Update Request [0b0]Do not request [0b1]Request
SRAMCTL_ACK	SRAMCTL - ACK. SRAM Control - SRAM Voltage Update Request Acknowledge [0b0]Not acknowledged [0b1]Acknowledged
SRAMRETLDO_REFTRIM_REFTRIM	SRAMRETLDO_REFTRIM - REFTRIM. SRAM Retention Reference Trim - Reference Trim. Voltage range is around 0.48V - 0.85V. Trim step is 12 mV.
SRAMRETLDO_CNTRL_SRAMLDO_ON	SRAMRETLDO_CNTRL - SRAMLDO_ON. SRAM Retention LDO Control - SRAM LDO Regulator Enable [0b0]Disable [0b1]Enable
SRAMRETLDO_CNTRL_SRAM_RET_EN	SRAMRETLDO_CNTRL - SRAM_RET_EN. SRAM Retention LDO Control - SRAM Retention
ACTIVE_CFG_CORELDO_VDD_DS	ACTIVE_CFG - CORELDO_VDD_DS. Active Power Mode Configuration - LDO_CORE VDD Drive Strength [0b0]Low [0b1]Normal
ACTIVE_CFG_CORELDO_VDD_LVL	ACTIVE_CFG - CORELDO_VDD_LVL. Active Power Mode Configuration - LDO_CORE VDD Regulator Voltage Level [0b00] [0b01]Regulate to mid voltage (1.0 V) [0b10]Regulate to normal voltage (1.1 V) [0b11]Regulate to overdrive voltage (1.15 V)
ACTIVE_CFG_BGMODE	ACTIVE_CFG - BGMODE. Active Power Mode Configuration - Bandgap Mode [0b00]Bandgap disabled [0b01]Bandgap enabled, buffer disabled [0b10]Bandgap enabled, buffer enabled [0b11]
ACTIVE_CFG_VDD_VD_DISABLE	ACTIVE_CFG - VDD_VD_DISABLE. Active Power Mode Configuration - VDD Voltage Detect Disable [0b0]Enable [0b1]Disable
ACTIVE_CFG_CORE_LVDE	ACTIVE_CFG - CORE_LVDE. Active Power Mode Configuration - Core Low-Voltage Detection Enable [0b0]Disable [0b1]Enable
ACTIVE_CFG_SYS_LVDE	ACTIVE_CFG - SYS_LVDE. Active Power Mode Configuration - System Low-Voltage Detection Enable [0b0]Disable [0b1]Enable
ACTIVE_CFG_SYS_HVDE	ACTIVE_CFG - SYS_HVDE. Active Power Mode Configuration - System High-Voltage Detection Enable [0b0]Disable [0b1]Enable
ACTIVE_CFG1_SOC_CNTRL	ACTIVE_CFG1 - SOC_CNTRL. Active Power Mode Configuration 1 - Active Config Chip Control
LP_CFG_CORELDO_VDD_DS	LP_CFG - CORELDO_VDD_DS. Low-Power Mode Configuration - LDO_CORE VDD Drive Strength [0b0]Low [0b1]Normal
LP_CFG_CORELDO_VDD_LVL	LP_CFG - CORELDO_VDD_LVL. Low-Power Mode Configuration - LDO_CORE VDD Regulator Voltage Level [0b00]Reserved [0b01]Mid voltage (1.0 V) [0b10]Normal voltage (1.1 V) [0b11]Overdrive voltage (1.15 V) *]
LP_CFG_SRAMLDO_DPD_ON	LP_CFG - SRAMLDO_DPD_ON. Low-Power Mode Configuration - SRAM_LDO Deep Power Low Power IREF Enable [0b0]Low Power IREF is disabled for power saving in Deep Power Down mode [0b1]Low Power IREF is enabled
LP_CFG_BGMODE	LP_CFG - BGMODE. Low-Power Mode Configuration - Bandgap Mode [0b00]Bandgap disabled [0b01]Bandgap enabled, buffer disabled [0b10]Bandgap enabled, buffer enabled [0b11]
LP_CFG_LP_IREFEN	LP_CFG - LP_IREFEN. Low-Power Mode Configuration - Low-Power IREF Enable [0b0]Disable for power saving in Deep Power Down mode [0b1]Enable
LP_CFG_CORE_LVDE	LP_CFG - CORE_LVDE. Low-Power Mode Configuration - Core Low Voltage Detect Enable [0b0]Disable [0b1]Enable
LP_CFG_SYS_LVDE	LP_CFG - SYS_LVDE. Low-Power Mode Configuration - System Low Voltage Detect Enable [0b0]Disable [0b1]Enable
LP_CFG_SYS_HVDE	LP_CFG - SYS_HVDE. Low-Power Mode Configuration - System High Voltage Detect Enable [0b0]Disable [0b1]Enable
LP_CFG1_SOC_CNTRL	LP_CFG1 - SOC_CNTRL. Low Power Mode Configuration 1 - Low-Power Configuration Chip Control
LPWKUP_DELAY_LPWKUP_DELAY	LPWKUP_DELAY - LPWKUP_DELAY. Low Power Wake-Up Delay - Low-Power Wake-Up Delay
ACTIVE_VDELAY_ACTIVE_VDELAY	ACTIVE_VDELAY - ACTIVE_VDELAY. Active Voltage Trim Delay - Active Voltage Delay
VD_STAT_COREVDD_LVDF	VD_STAT - COREVDD_LVDF. Voltage Detect Status - Core Low-Voltage Detect Flag [0b0]Event not detected [0b1]Event detected [0b0]No effect [0b1]Clear the flag
VD_STAT_SYSVDD_LVDF	VD_STAT - SYSVDD_LVDF. Voltage Detect Status - System Low-Voltage Detect Flag [0b0]Event not detected [0b1]Event detected [0b0]No effect [0b1]Clear the flag
VD_STAT_SYSVDD_HVDF	VD_STAT - SYSVDD_HVDF. Voltage Detect Status - System HVD Flag [0b0]Event not detected [0b1]Event detected [0b0]No effect [0b1]Clear the flag
VD_CORE_CFG_LVDRE	VD_CORE_CFG - LVDRE. Core Voltage Detect Configuration - Core LVD Reset Enable [0b0]Disable [0b1]Enable
VD_CORE_CFG_LVDIE	VD_CORE_CFG - LVDIE. Core Voltage Detect Configuration - Core LVD Interrupt Enable [0b0]Disable [0b1]Enable
VD_CORE_CFG_LOCK	VD_CORE_CFG - LOCK. Core Voltage Detect Configuration - Core Voltage Detect Reset Enable Lock [0b0]Allow [0b1]Deny
VD_SYS_CFG_LVDRE	VD_SYS_CFG - LVDRE. System Voltage Detect Configuration - System LVD Reset Enable [0b0]Disable [0b1]Enable
VD_SYS_CFG_LVDIE	VD_SYS_CFG - LVDIE. System Voltage Detect Configuration - System LVD Interrupt Enable [0b0]Disable [0b1]Enable
VD_SYS_CFG_HVDRE	VD_SYS_CFG - HVDRE. System Voltage Detect Configuration - System HVD Reset Enable [0b0]Disable [0b1]Enable
VD_SYS_CFG_HVDIE	VD_SYS_CFG - HVDIE. System Voltage Detect Configuration - System HVD Interrupt Enable [0b0]Disable [0b1]Enable
VD_SYS_CFG_LVSEL	VD_SYS_CFG - LVSEL. System Voltage Detect Configuration - System Low-Voltage Level Select [0b0]Normal [0b1]Safe
VD_SYS_CFG_LOCK	VD_SYS_CFG - LOCK. System Voltage Detect Configuration - System Voltage Detect Reset Enable Lock [0b0]Allow [0b1]Deny
EVD_CFG_EVDISO	EVD_CFG - EVDISO. External Voltage Domain Configuration - External Voltage Domain Isolation
EVD_CFG_EVDLPISO	EVD_CFG - EVDLPISO. External Voltage Domain Configuration - External Voltage Domain Low-Power Isolation
EVD_CFG_EVDSTAT	EVD_CFG - EVDSTAT. External Voltage Domain Configuration - External Voltage Domain Status

◆ SramOperateVoltage

enum struct mcxa153::chip::spc::SramOperateVoltage : unsigned char

strong

SRAM Operating Voltage Enumeration.

Defines operating voltage levels for SRAM read/write timing margin optimization. Different voltage levels provide different timing margins and power consumption characteristics, allowing system designers to optimize for performance or efficiency.

SRAM 操作電壓枚舉，定義不同電壓等級的讀寫時序裕量優化

Voltage Selection Considerations:

Higher voltages provide better timing margins and reliability
Lower voltages reduce power consumption but may affect performance
Voltage selection affects SRAM access timing and hold times
Must match system power supply capabilities and requirements

註

Performance Impact:

1.0V: Lowest power consumption, tightest timing margins
1.1V: Balanced power consumption and timing performance
1.2V: Highest timing margins and reliability, increased power

警告

Important Considerations:

SRAM voltage must not exceed system supply voltage
Voltage changes may require timing parameter adjustments
Some applications may require specific voltage levels for certification
Always verify voltage compatibility with system design requirements

參閱: SRAM Control registers for voltage configuration; System Power Controller for voltage regulation

列舉值

AT_1P0V

SRAM 1.0V Operation Mode.

Configures SRAM for operation at 1.0V supply voltage. This mode provides the lowest power consumption but requires careful timing consideration due to reduced noise margins and slower switching speeds.

SRAM 1.0V 操作模式，提供最低功耗但需要謹慎考慮時序

1.0V Mode Characteristics:

Lowest power consumption among available voltage levels
Tightest timing margins requiring careful system design
Reduced noise immunity and switching speed
Suitable for ultra-low power applications
May require slower system clock frequencies

註

Applications:

Battery-powered devices with strict power budgets
Ultra-low power sleep modes with SRAM retention
Cost-sensitive applications requiring power efficiency
Systems with relaxed performance requirements

警告: Verify timing margins at system operating frequency. May require system clock reduction for reliable operation.

AT_1P1V

SRAM 1.1V Operation Mode.

Configures SRAM for operation at 1.1V supply voltage. This mode provides a balanced compromise between power consumption and timing performance, suitable for most general-purpose applications.

SRAM 1.1V 操作模式，提供功耗和性能的平衡折衷

1.1V Mode Characteristics:

Balanced power consumption and timing performance
Good timing margins for typical system frequencies
Reasonable noise immunity and switching speed
Suitable for most general-purpose applications
Compatible with standard system clock frequencies

註

Applications:

General-purpose embedded systems
IoT devices with moderate performance requirements
Systems requiring balance between power and performance
Applications with standard timing requirements

@recommended This voltage level is typically recommended for most applications as it provides good balance of all characteristics.

AT_1P2V

SRAM 1.2V Operation Mode.

Configures SRAM for operation at 1.2V supply voltage. This mode provides the highest timing margins and reliability but consumes more power. Ideal for high-performance applications or harsh operating environments.

SRAM 1.2V 操作模式，提供最高時序裕量和可靠性但功耗較高

1.2V Mode Characteristics:

Highest timing margins and reliability
Best noise immunity and fastest switching speeds
Higher power consumption than lower voltage modes
Suitable for high-performance and critical applications
Supports highest system clock frequencies

註

Applications:

High-performance computing applications
Safety-critical systems requiring maximum reliability
Industrial applications in harsh environments
Systems with abundant power budgets
Applications requiring highest possible clock frequencies

@performance Provides best SRAM access timing and hold margins for maximum system performance and reliability.

◆ Status

enum struct mcxa153::chip::spc::Status : unsigned int

strong

System Power Controller (SPC) Status Enumeration.

Comprehensive status codes for SPC operations including generic system status and SPC-specific error conditions. These codes provide detailed feedback for power management operations, voltage regulation, and system configuration.

SPC 狀態枚舉，提供電源管理操作的詳細狀態回饋

Status Categories:

Generic Status: Common system operation results (SUCCESS, FAIL, etc.)
SPC-Specific Status: Power controller specific error conditions
Voltage Regulator Status: LDO and DCDC specific error codes
System Configuration Status: Bandgap and drive strength related errors

註: Device Compatibility: Some MCXA family devices do not include DCDC or System LDO components. Always refer to the device reference manual to verify available features before using related status codes.

警告

Important Usage:

Always check return status for critical power operations
Some status codes are device-specific and may not apply to all variants
Power mode transitions may temporarily return SPC_BUSY status
Voltage-related errors may indicate hardware configuration issues

參閱: MCXA153 Reference Manual for device-specific feature availability; SPC Register definitions for related control mechanisms

列舉值
SUCCESS	Operation Successful. Generic status indicating successful completion of SPC operation 操作成功狀態，表示 SPC 操作成功完成
FAIL	Operation Failed. Generic status indicating SPC operation failure 操作失敗狀態，表示 SPC 操作失敗
READONLY	Read-Only Access Violation. Attempt to modify read-only SPC register or configuration 只讀訪問違規，嘗試修改只讀的 SPC 寄存器或配置
OUT_OF_RANGE	Parameter Out of Valid Range. SPC parameter value exceeds allowable range 參數超出有效範圍，SPC 參數值超過允許範圍
INVALID_ARGUMENT	Invalid Argument Provided. SPC function called with invalid or incompatible argument 提供無效參數，使用無效或不兼容的參數調用 SPC 函數
TIMEOUT	Operation Timeout. SPC operation did not complete within expected time limit 操作超時，SPC 操作未在預期時間限制內完成
NO_TRANSFER_IN_PROGRESS	No Transfer in Progress. No active SPC transfer or transition operation 沒有進行中的傳輸，沒有活動的 SPC 傳輸或轉換操作
BUSY	SPC Module Busy. SPC is currently busy and cannot accept new operations SPC 模組忙碌，目前忙碌無法接受新操作
NO_DATA	No Data Available. Requested SPC data or status information not available 無可用數據，請求的 SPC 數據或狀態信息不可用
SPC_BUSY	SPC Power Mode Transition Busy. The SPC instance is currently executing a power mode transition and cannot accept new power management commands until completion. SPC 電源模式轉換忙碌，SPC 實例正在執行電源模式轉換註 This is a temporary condition that resolves when transition completes. Applications should wait or retry the operation after a brief delay.
DCDC_LOW_DRIVE_STRENGTH_IGNORE	DCDC Low Drive Strength Setting Ignored. DCDC low drive strength setting was ignored because LVD/HVD (Low/High Voltage Detection) is enabled, which overrides drive strength. DCDC 低驅動強度設置被忽略，因為啟用了 LVD/HVD 檢測註 This is an informational status. The system prioritizes voltage detection over drive strength optimization for safety reasons.
DCDC_PULSE_REFRESH_MODE_IGNORE	DCDC Pulse Refresh Mode Setting Ignored. DCDC pulse refresh mode setting was ignored because LVD/HVD is enabled, which takes precedence over refresh mode configuration. DCDC 脈衝刷新模式設置被忽略，因為啟用了 LVD/HVD 檢測註 Voltage detection safety features override power optimization settings to ensure system stability and protection.
SYSLDO_OVER_DRIVE_VOLTAGE_FAIL	System LDO Over Drive Voltage Configuration Failed. System LDO failed to regulate to over drive voltage because System LDO HVD (High Voltage Detection) must be disabled for this mode. 系統 LDO 過驱動電壓配置失敗，因為必須禁用系統 LDO HVD 警告 This indicates a configuration conflict. Disable System LDO HVD before attempting to configure over drive voltage mode.
SYSLDO_LOW_DRIVE_STRENGTH_IGNORE	System LDO Low Drive Strength Setting Ignored. System LDO low driver strength setting was ignored because LDO LVD/HVD is enabled, which overrides the drive strength configuration. 系統 LDO 低驅動強度設置被忽略，因為啟用了 LDO LVD/HVD 註 Voltage detection features take precedence over power optimization settings to maintain system safety and stability.
CORELDO_LOW_DRIVE_STRENGTH_IGNORE	Core LDO Low Drive Strength Setting Ignored. Core LDO low driver strength setting was ignored because LDO LVD/HVD is enabled, which takes priority over drive strength. 核心 LDO 低驅動強度設置被忽略，因為啟用了 LDO LVD/HVD 註 This is an informational status indicating safety features are active and overriding power optimization settings.
BANDGAP_MODE_WRONG	Bandgap Mode Selection Error. The selected bandgap mode is incorrect or incompatible with current system configuration or operating conditions. 帶隙模式選擇錯誤，選擇的帶隙模式不正確或與當前配置不兼容警告 This indicates a critical configuration error that may affect voltage reference stability. Verify bandgap mode compatibility.
CORELDO_VOLTAGE_WRONG	Core LDO Voltage Configuration Error. The specified Core LDO voltage value is incorrect or outside the allowable range for the current operating conditions. 核心 LDO 電壓配置錯誤，指定的電壓值不正確或超出允許範圍警告 This may cause system instability. Verify voltage requirements and ensure compatibility with system specifications.
CORELDO_VOLTAGE_SET_FAIL	Core LDO Voltage Setting Failed. Core LDO failed to set the requested voltage level, possibly due to hardware limitations or conflicting configuration settings. 核心 LDO 電壓設置失敗，可能因硬體限制或配置衝突警告 This indicates a hardware or configuration issue that prevents proper voltage regulation. System may not operate correctly.

◆ VoltageDetectFlag

enum struct mcxa153::chip::spc::VoltageDetectFlag : unsigned int

strong

Voltage Detection Status Flag Enumeration.

Status flags for voltage detection circuits within the MCXA153 System Power Controller. These flags indicate the current state of voltage monitoring circuits and provide real-time feedback on system and core voltage conditions.

電壓檢測狀態標誌枚舉，指示電壓監控電路的當前狀態

Voltage Detection Features:

Real-time monitoring of system and core voltage levels
High and low voltage detection for system VDD
Core VDD low voltage detection for processor protection
Integration with SPC interrupt and alert systems
Support for voltage-based system protection mechanisms

註

Flag Usage:

Flags are set automatically by voltage detection hardware
Can be used to trigger interrupt service routines
Essential for implementing voltage-based system protection
May require clearing after handling voltage events
Should be checked regularly in critical applications

警告

Important Considerations:

Voltage detection flags indicate potentially critical system conditions
High voltage flags may indicate overvoltage conditions requiring immediate action
Low voltage flags may indicate power supply issues or battery depletion
Core voltage issues may affect processor stability and require system reset

參閱: Mask enumeration for underlying bit mask definitions; VD_STAT register for flag status implementation; SPC interrupt configuration for voltage event handling

列舉值

SYSTEM_VDD_HIGH

System VDD High Voltage Detection Flag.

Indicates that the system VDD voltage has exceeded the high voltage detection threshold. This flag signals a potential overvoltage condition that may require immediate system attention to prevent hardware damage.

系統 VDD 高電壓檢測標誌，指示系統 VDD 電壓超過高電壓檢測閾值

High Voltage Detection Characteristics:

Set when system VDD exceeds configured high voltage threshold
Indicates potential overvoltage condition
May trigger system protection mechanisms
Could indicate power supply malfunction or configuration error
Requires immediate attention to prevent system damage

註

Response Actions:

Check power supply output voltage and regulation
Verify system power configuration settings
Consider implementing overvoltage protection measures
May require system shutdown or voltage reduction

警告: Critical Condition: This flag indicates a potentially dangerous overvoltage condition. Immediate action may be required to prevent hardware damage.

參閱: SYSTEM_VDD voltage specifications for threshold levels; Overvoltage protection mechanisms for response strategies

SYSTEM_VDD_LOW

System VDD Low Voltage Detection Flag.

Indicates that the system VDD voltage has fallen below the low voltage detection threshold. This flag signals insufficient supply voltage that may cause system instability or malfunction if not addressed promptly.

系統 VDD 低電壓檢測標誌，指示系統 VDD 電壓低於低電壓檢測閾值

Low Voltage Detection Characteristics:

Set when system VDD falls below configured low voltage threshold
Indicates insufficient system supply voltage
May cause system instability or unpredictable behavior
Could indicate power supply problems or battery depletion
May trigger low power mode transitions for protection

註

Response Actions:

Check power supply capacity and regulation
Consider entering low power mode to reduce consumption
Implement graceful system shutdown if voltage continues falling
May require load reduction or power source switching

警告: System Reliability Risk: Low system voltage may cause unpredictable system behavior. Take appropriate action to ensure system stability and data integrity.

參閱: Low power mode configuration for voltage-based power management; Battery management for power source monitoring

CORE_VDD_LOW

Core VDD Low Voltage Detection Flag.

Indicates that the core VDD voltage has fallen below the low voltage detection threshold. This flag signals insufficient processor core voltage that may cause CPU malfunction, data corruption, or system crashes.

核心 VDD 低電壓檢測標誌，指示核心 VDD 電壓低於低電壓檢測閾值

Core Voltage Detection Characteristics:

Set when core VDD falls below configured low voltage threshold
Indicates insufficient processor core supply voltage
May cause CPU malfunction or erratic program execution
Could lead to data corruption or system crashes
Critical for processor stability and system integrity

註

Response Actions:

Immediately check core voltage regulator operation
Consider reducing CPU clock frequency to lower voltage requirements
Implement emergency system shutdown if voltage cannot be restored
Save critical data before potential system failure

警告: Critical System Condition: Low core voltage directly threatens processor stability and system integrity. Immediate corrective action is essential to prevent system failure.

參閱: Core LDO configuration for voltage regulation; CPU clock management for frequency scaling options; Emergency shutdown procedures for system protection

函式說明文件

◆ operator+() [1/6]

unsigned char mcxa153::chip::spc::operator+ ( BandgapMode e )

constexpr

Operator Overload - Convert BandgapMode enum to unsigned char.

Converts BandgapMode enumeration value to unsigned char for register assignment. Useful for setting bandgap mode in SPC configuration registers.

將BandgapMode列舉值轉換為無符號字元，便於直接暫存器賦值

參數

e	BandgapMode enumeration value 帶隙模式列舉值

傳回值: constexpr unsigned char Numeric bandgap mode value (0-3)

範例: F:/mframe/doxy-document/src/mcxa153/src/mcxa153/chip/spc/Mask.h.

◆ operator+() [2/6]

unsigned char mcxa153::chip::spc::operator+ ( CoreLdoDriveStrength e )

constexpr

Operator Overload - Convert CoreLdoDriveStrength enum to unsigned char.

Converts CoreLdoDriveStrength enumeration value to unsigned char for register assignment. Useful for setting core LDO drive strength in SPC configuration registers.

將CoreLdoDriveStrength列舉值轉換為無符號字元，便於直接暫存器賦值

參數

e	CoreLdoDriveStrength enumeration value 核心LDO驅動強度列舉值

傳回值: constexpr unsigned char Numeric drive strength value (0-1)

◆ operator+() [3/6]

unsigned char mcxa153::chip::spc::operator+ ( CoreLdoVoltageLevel e )

constexpr

Operator Overload - Convert CoreLdoVoltageLevel enum to unsigned char.

Converts CoreLdoVoltageLevel enumeration value to unsigned char for register assignment. Useful for setting core LDO voltage levels in SPC configuration registers.

將CoreLdoVoltageLevel列舉值轉換為無符號字元，便於直接暫存器賦值

參數

e	CoreLdoVoltageLevel enumeration value 核心LDO電壓等級列舉值

傳回值: constexpr unsigned char Numeric voltage level value (0-3)

◆ operator+() [4/6]

unsigned int mcxa153::chip::spc::operator+ ( Count e )

constexpr

Operator Overload - Convert Count enum to unsigned int.

Converts Count enumeration value to unsigned integer for register assignment. Useful for setting SPC count values in SPC configuration registers.

將Count列舉值轉換為無符號整數，便於直接暫存器賦值

參數

e	Count enumeration value 計數列舉值

傳回值: constexpr unsigned int Numeric count value (0-255)

◆ operator+() [5/6]

unsigned int mcxa153::chip::spc::operator+ ( Mask e )

constexpr

Operator Overload - Convert Mask enum to unsigned int.

Converts Mask enumeration value to unsigned integer for easy register manipulation. Useful for setting or clearing specific bits in SPC control and status registers.

將Mask列舉值轉換為無號整數，便於暫存器操作

參數

e	Mask enumeration value 列舉值

傳回值: constexpr unsigned int Unsigned integer representation of the mask

◆ operator+() [6/6]

unsigned int mcxa153::chip::spc::operator+ ( Shift e )

constexpr

Unary plus operator overload for Shift enum.

Converts Shift enumeration value to its underlying unsigned integer representation. This operator enables implicit conversion to numeric values for register operations, configuration functions, and bit manipulation when interfacing with SPC registers.

Shift 枚舉的一元加號運算子重載，用於類型轉換

參數

e	Shift enum value to convert

傳回值: unsigned int The underlying numeric value of the enum

複合項目

列舉型態

函式

變數

詳細描述

列舉型態說明文件

◆ AnalogModuleControl

◆ BandgapMode

◆ CoreLdoDriveStrength

◆ CoreLdoVoltageLevel

◆ Count

◆ LowPowerRequestOutputOverride

◆ LowPowerRequestPinPolarity

◆ LowVoltageLevelSelect

◆ Mask

◆ PowerDomainID

◆ PowerDomainLowPowerMode

◆ PowerDomains

◆ Shift

◆ SramOperateVoltage

◆ Status

◆ VoltageDetectFlag

函式說明文件

◆ operator+() [1/6]

◆ operator+() [2/6]

◆ operator+() [3/6]

◆ operator+() [4/6]

◆ operator+() [5/6]

◆ operator+() [6/6]