System Power Controller (SPC) Register Structure. 更多...

#include <Register.h>

公開屬性
__I uint32	verid
	Version ID Register.

uint8	reserved_0 [12]
	Reserved Space 0.

__IO uint32	sc
	Status Control Register.

uint8	reserved_1 [8]
	Reserved Space 1.

__IO uint32	lpreq_cfg
	Low Power Request Configuration Register.

__IO uint32	cfg
	SPC Configuration Register.

uint8	reserved_2 [12]
	Reserved Space 2.

__IO uint32	pd_status [1]
	Power Domain Status Register Array.

uint8	reserved_3 [12]
	Reserved Space 3.

__IO uint32	sramctl
	SRAM Control Register.

uint8	reserved_4 [16]
	Reserved Space 4.

__IO uint32	sramretldo_reftrim
	SRAM Retention Reference Trim Register.

__IO uint32	sramretldo_cntrl
	SRAM Retention LDO Control Register.

uint8	reserved_5 [164]
	Reserved Space 5.

__IO uint32	active_cfg
	Active Power Mode Configuration Register.

__IO uint32	active_cfg1
	Active Power Mode Configuration 1 Register.

__IO uint32	lp_cfg
	Low Power Mode Configuration Register.

__IO uint32	lp_cfg1
	Low Power Mode Configuration 1 Register.

uint8	reserved_6 [16]
	Reserved Space 6.

__IO uint32	lpwkup_delay
	Low Power Wake-Up Delay Register.

__IO uint32	active_vdelay
	Active Voltage Trim Delay Register.

uint8	reserved_7 [8]
	Reserved Space 7.

__IO uint32	vd_stat
	Voltage Detect Status Register.

__IO uint32	vd_core_cfg
	Core Voltage Detect Configuration Register.

__IO uint32	vd_sys_cfg
	System Voltage Detect Configuration Register.

uint8	reserved_8 [4]
	Reserved Space 8.

__IO uint32	evd_cfg
	External Voltage Domain Configuration Register.

uint8	reserved_9 [444]
	Reserved Space 9.

uint32	coreldo_cfg
	LDO Core Configuration Register.

詳細描述

System Power Controller (SPC) Register Structure.

Complete register map for the MCXA153 System Power Controller peripheral. The SPC provides comprehensive power management functionality including voltage regulation, power domain control, low power mode management, and voltage detection.

SPC 寄存器結構體，提供完整的系統電源控制功能

SPC Functionality:

System voltage regulation and monitoring
Power domain management and control
Low power mode configuration and transition
SRAM retention control during low power states
Voltage detection and protection mechanisms
Wake-up timing and delay management

註

Register Access:

Base Address: SPC peripheral base address
Most registers are 32-bit aligned
Some registers have restricted access in certain power modes
Reserved areas must not be accessed

警告

Important Considerations:

Improper SPC configuration may cause system instability
Some registers may only be writable in specific power states
Always follow proper power mode transition sequences
Voltage detection settings affect system protection

參閱: MCXA153 Reference Manual for detailed register descriptions; Power Management Guide for configuration examples

資料成員說明文件

◆ active_cfg

__IO uint32 mcxa153::chip::spc::Register::active_cfg

Active Power Mode Configuration Register.

Configuration settings for active power mode operation @offset 0x100 @access Read/Write

◆ active_cfg1

__IO uint32 mcxa153::chip::spc::Register::active_cfg1

Active Power Mode Configuration 1 Register.

Extended configuration settings for active power mode @offset 0x104 @access Read/Write

◆ active_vdelay

__IO uint32 mcxa153::chip::spc::Register::active_vdelay

Active Voltage Trim Delay Register.

Delay configuration for voltage transitions in active mode @offset 0x124 @access Read/Write

◆ cfg

__IO uint32 mcxa153::chip::spc::Register::cfg

SPC Configuration Register.

Main SPC configuration register for power management settings @offset 0x20 @access Read/Write

◆ coreldo_cfg

uint32 mcxa153::chip::spc::Register::coreldo_cfg

LDO Core Configuration Register.

Configuration register for core LDO voltage regulator @offset 0x300 @access Read-only

◆ evd_cfg

__IO uint32 mcxa153::chip::spc::Register::evd_cfg

External Voltage Domain Configuration Register.

Configuration for external voltage domain management @offset 0x140 @access Read/Write

◆ lp_cfg

__IO uint32 mcxa153::chip::spc::Register::lp_cfg

Low Power Mode Configuration Register.

Configuration settings for low power mode operation @offset 0x108 @access Read/Write

◆ lp_cfg1

__IO uint32 mcxa153::chip::spc::Register::lp_cfg1

Low Power Mode Configuration 1 Register.

Extended configuration settings for low power mode @offset 0x10C @access Read/Write

◆ lpreq_cfg

__IO uint32 mcxa153::chip::spc::Register::lpreq_cfg

Low Power Request Configuration Register.

Configuration for low power request signals and wake-up sources @offset 0x1C @access Read/Write

◆ lpwkup_delay

__IO uint32 mcxa153::chip::spc::Register::lpwkup_delay

Low Power Wake-Up Delay Register.

Delay configuration for wake-up from low power modes @offset 0x120 @access Read/Write

◆ pd_status

__IO uint32 mcxa153::chip::spc::Register::pd_status[1]

Power Domain Status Register Array.

Status registers for individual power domains @offset 0x30 (array step: 0x4) @access Read/Write

◆ reserved_0

uint8 mcxa153::chip::spc::Register::reserved_0[12]

Reserved Space 0.

Reserved register space - do not access @offset 0x4-0xC

◆ reserved_1

uint8 mcxa153::chip::spc::Register::reserved_1[8]

Reserved Space 1.

Reserved register space - do not access @offset 0x14-0x18

◆ reserved_2

uint8 mcxa153::chip::spc::Register::reserved_2[12]

Reserved Space 2.

Reserved register space - do not access @offset 0x24-0x2C

◆ reserved_3

uint8 mcxa153::chip::spc::Register::reserved_3[12]

Reserved Space 3.

Reserved register space - do not access @offset 0x34-0x3C

◆ reserved_4

uint8 mcxa153::chip::spc::Register::reserved_4[16]

Reserved Space 4.

Reserved register space - do not access @offset 0x44-0x50

◆ reserved_5

uint8 mcxa153::chip::spc::Register::reserved_5[164]

Reserved Space 5.

Reserved register space - do not access @offset 0x5C-0xFC

◆ reserved_6

uint8 mcxa153::chip::spc::Register::reserved_6[16]

Reserved Space 6.

Reserved register space - do not access @offset 0x110-0x11C

◆ reserved_7

uint8 mcxa153::chip::spc::Register::reserved_7[8]

Reserved Space 7.

Reserved register space - do not access @offset 0x128-0x12C

◆ reserved_8

uint8 mcxa153::chip::spc::Register::reserved_8[4]

Reserved Space 8.

Reserved register space - do not access @offset 0x13C

◆ reserved_9

uint8 mcxa153::chip::spc::Register::reserved_9[444]

Reserved Space 9.

Reserved register space - do not access @offset 0x144-0x2FC

◆ sc

__IO uint32 mcxa153::chip::spc::Register::sc

Status Control Register.

Main SPC status and control register for power management operations @offset 0x10 @access Read/Write

◆ sramctl

__IO uint32 mcxa153::chip::spc::Register::sramctl

SRAM Control Register.

Control register for SRAM power management and retention @offset 0x40 @access Read/Write

◆ sramretldo_cntrl

__IO uint32 mcxa153::chip::spc::Register::sramretldo_cntrl

SRAM Retention LDO Control Register.

Control register for SRAM retention LDO settings @offset 0x58 @access Read/Write

◆ sramretldo_reftrim

__IO uint32 mcxa153::chip::spc::Register::sramretldo_reftrim

SRAM Retention Reference Trim Register.

Trimming configuration for SRAM retention voltage reference @offset 0x54 @access Read/Write

◆ vd_core_cfg

__IO uint32 mcxa153::chip::spc::Register::vd_core_cfg

Core Voltage Detect Configuration Register.

Configuration for core voltage detection and monitoring @offset 0x134 @access Read/Write

◆ vd_stat

__IO uint32 mcxa153::chip::spc::Register::vd_stat

Voltage Detect Status Register.

Status information for voltage detection circuits @offset 0x130 @access Read/Write

◆ vd_sys_cfg

__IO uint32 mcxa153::chip::spc::Register::vd_sys_cfg

System Voltage Detect Configuration Register.

Configuration for system voltage detection and monitoring @offset 0x138 @access Read/Write

◆ verid

__I uint32 mcxa153::chip::spc::Register::verid

Version ID Register.

Read-only register containing SPC peripheral version information @offset 0x0 @access Read-only

此結構(structure) 文件是由下列檔案中產生:

spc/Register.h

公開屬性