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core/src/mux/Mux.h
1
7#ifndef CORE_7E9D719A_76F9_4D7D_86D0_B2F9958C74F3
8#define CORE_7E9D719A_76F9_4D7D_86D0_B2F9958C74F3
9
10/* ***************************************************************************************
11 * Include
12 */
13
14//----------------------------------------------------------------------------------------
15#include "mframe.h"
16
17//----------------------------------------------------------------------------------------
18#include "./MuxPortPin.h"
19
20/* ***************************************************************************************
21 * Namespace
22 */
23namespace core::mux {
24 enum struct Mux : uint32;
25
26 constexpr uint32 operator+(Mux e) {
27 return static_cast<uint32>(e);
28 }
29
30 static inline constexpr uint8 getMuxPort(Mux e) {
31 return static_cast<uint8>((+e & 0x00000300) >> 8U);
32 }
33
34 static inline constexpr uint8 getMuxPin(Mux e) {
35 return static_cast<uint8>(+e & 0x0000001F);
36 }
37
38 static inline constexpr core::mux::MuxPortPin getMuxPortPin(Mux e) {
39 return static_cast<core::mux::MuxPortPin>(static_cast<uint16>(+e & 0x0000FFFF));
40 }
41
42 static inline constexpr uint16 getMuxAlt(Mux e) {
43 return static_cast<uint16>((+e & 0xFFFF0000) >> 16U);
44 }
45
46 static inline constexpr uint32 genMuxAlt(core::mux::MuxPortPin portPin, uint16 alt) {
47 return (static_cast<uint32>(alt) << 16U) + (+portPin);
48 }
49} // namespace core::mux
50
51/* ***************************************************************************************
52 * Class/Interface/Struct/Enum
53 */
54enum struct core::mux::Mux : uint32 {
55 P0_0_GPIO = genMuxAlt(core::mux::MuxPortPin::P0_0, 0),
56 P0_0_TMS_SWDIO = genMuxAlt(core::mux::MuxPortPin::P0_0, 1),
57 P0_0_LPUART0_RTS_B = genMuxAlt(core::mux::MuxPortPin::P0_0, 2),
58 P0_0_LPSPI0_PCS0 = genMuxAlt(core::mux::MuxPortPin::P0_0, 3),
59 P0_0_CT_INP0 = genMuxAlt(core::mux::MuxPortPin::P0_0, 4),
60
61 P0_1_GPIO = genMuxAlt(core::mux::MuxPortPin::P0_1, 0),
62 P0_1_TCLK_SWCLK = genMuxAlt(core::mux::MuxPortPin::P0_1, 1),
63 P0_1_LPUART0_CTS_B = genMuxAlt(core::mux::MuxPortPin::P0_1, 2),
64 P0_1_LPSPI0_SDI = genMuxAlt(core::mux::MuxPortPin::P0_1, 3),
65 P0_1_CT_INP1 = genMuxAlt(core::mux::MuxPortPin::P0_1, 4),
66
67 P0_2_GPIO = genMuxAlt(core::mux::MuxPortPin::P0_2, 0),
68 P0_2_TDO_SWO = genMuxAlt(core::mux::MuxPortPin::P0_2, 1),
69 P0_2_LPUART0_RXD = genMuxAlt(core::mux::MuxPortPin::P0_2, 2),
70 P0_2_LPSPI0_SCK = genMuxAlt(core::mux::MuxPortPin::P0_2, 3),
71 P0_2_CT0_MAT0 = genMuxAlt(core::mux::MuxPortPin::P0_2, 4),
72 P0_2_UTICK_CAP0 = genMuxAlt(core::mux::MuxPortPin::P0_2, 5),
73 P0_2_I3C0_PUR = genMuxAlt(core::mux::MuxPortPin::P0_2, 10),
74
75 P0_3_GPIO = genMuxAlt(core::mux::MuxPortPin::P0_3, 0),
76 P0_3_TDI = genMuxAlt(core::mux::MuxPortPin::P0_3, 1),
77 P0_3_LPUART0_TXD = genMuxAlt(core::mux::MuxPortPin::P0_3, 2),
78 P0_3_LPSPI0_SDO = genMuxAlt(core::mux::MuxPortPin::P0_3, 3),
79 P0_3_CT0_MAT1 = genMuxAlt(core::mux::MuxPortPin::P0_3, 4),
80 P0_3_UTICK_CAP1 = genMuxAlt(core::mux::MuxPortPin::P0_3, 5),
81 P0_3_CMP0_OUT = genMuxAlt(core::mux::MuxPortPin::P0_3, 8),
82
83 P0_6_GPIO = genMuxAlt(core::mux::MuxPortPin::P0_6, 0),
84 P0_6_LPI2C0_HREQ = genMuxAlt(core::mux::MuxPortPin::P0_6, 2),
85 P0_6_LPSPI0_PCS1 = genMuxAlt(core::mux::MuxPortPin::P0_6, 3),
86 P0_6_CT_INP2 = genMuxAlt(core::mux::MuxPortPin::P0_6, 4),
87 P0_6_CMP1_OUT = genMuxAlt(core::mux::MuxPortPin::P0_6, 8),
88 P0_6_CLKOUT = genMuxAlt(core::mux::MuxPortPin::P0_6, 12),
89
90 P0_16_GPIO = genMuxAlt(core::mux::MuxPortPin::P0_16, 0),
91 P0_16_LPI2C0_SDA = genMuxAlt(core::mux::MuxPortPin::P0_16, 2),
92 P0_16_LPSPI0_PCS2 = genMuxAlt(core::mux::MuxPortPin::P0_16, 3),
93 P0_16_CT0_MAT0 = genMuxAlt(core::mux::MuxPortPin::P0_16, 4),
94 P0_16_UTICK_CAP2 = genMuxAlt(core::mux::MuxPortPin::P0_16, 5),
95 P0_16_I3C0_SDA = genMuxAlt(core::mux::MuxPortPin::P0_16, 10),
96
97 P0_17_GPIO = genMuxAlt(core::mux::MuxPortPin::P0_17, 0),
98 P0_17_LPI2C0_SCL = genMuxAlt(core::mux::MuxPortPin::P0_17, 2),
99 P0_17_LPSPI0_PCS3 = genMuxAlt(core::mux::MuxPortPin::P0_17, 3),
100 P0_17_CT0_MAT1 = genMuxAlt(core::mux::MuxPortPin::P0_17, 4),
101 P0_17_UTICK_CAP3 = genMuxAlt(core::mux::MuxPortPin::P0_17, 5),
102 P0_17_I3C0_SCL = genMuxAlt(core::mux::MuxPortPin::P0_17, 10),
103
104 P1_0_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_0, 0),
105 P1_0_TRIG_IN0 = genMuxAlt(core::mux::MuxPortPin::P1_0, 1),
106 P1_0_LPSPI0_SDO = genMuxAlt(core::mux::MuxPortPin::P1_0, 2),
107 P1_0_LPI2C0_SDA = genMuxAlt(core::mux::MuxPortPin::P1_0, 3),
108 P1_0_CT_INP4 = genMuxAlt(core::mux::MuxPortPin::P1_0, 4),
109 P1_0_CT0_MAT2 = genMuxAlt(core::mux::MuxPortPin::P1_0, 5),
110
111 P1_1_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_1, 0),
112 P1_1_TRIG_IN1 = genMuxAlt(core::mux::MuxPortPin::P1_1, 1),
113 P1_1_LPSPI0_SCK = genMuxAlt(core::mux::MuxPortPin::P1_1, 2),
114 P1_1_LPI2C0_SCL = genMuxAlt(core::mux::MuxPortPin::P1_1, 3),
115 P1_1_CT_INP5 = genMuxAlt(core::mux::MuxPortPin::P1_1, 4),
116 P1_1_CT0_MAT3 = genMuxAlt(core::mux::MuxPortPin::P1_1, 5),
117
118 P1_2_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_2, 0),
119 P1_2_TRIG_OUT0 = genMuxAlt(core::mux::MuxPortPin::P1_2, 1),
120 P1_2_LPSPI0_SDI = genMuxAlt(core::mux::MuxPortPin::P1_2, 2),
121 P1_2_LPI2C0_SDAS = genMuxAlt(core::mux::MuxPortPin::P1_2, 3),
122 P1_2_CT1_MAT0 = genMuxAlt(core::mux::MuxPortPin::P1_2, 4),
123 P1_2_CT_INP0 = genMuxAlt(core::mux::MuxPortPin::P1_2, 5),
124
125 P1_3_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_3, 0),
126 P1_3_TRIG_OUT1 = genMuxAlt(core::mux::MuxPortPin::P1_3, 1),
127 P1_3_LPSPI0_PCS0 = genMuxAlt(core::mux::MuxPortPin::P1_3, 2),
128 P1_3_LPI2C0_SCLS = genMuxAlt(core::mux::MuxPortPin::P1_3, 3),
129 P1_3_CT1_MAT1 = genMuxAlt(core::mux::MuxPortPin::P1_3, 4),
130 P1_3_CT_INP1 = genMuxAlt(core::mux::MuxPortPin::P1_3, 5),
131
132 P1_4_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_4, 0),
133 P1_4_FREQME_CLK_IN0 = genMuxAlt(core::mux::MuxPortPin::P1_4, 1),
134 P1_4_LPSPI0_PCS3 = genMuxAlt(core::mux::MuxPortPin::P1_4, 2),
135 P1_4_LPUART2_RXD = genMuxAlt(core::mux::MuxPortPin::P1_4, 3),
136 P1_4_CT1_MAT2 = genMuxAlt(core::mux::MuxPortPin::P1_4, 4),
137
138 P1_5_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_5, 0),
139 P1_5_FREQME_CLK_IN1 = genMuxAlt(core::mux::MuxPortPin::P1_5, 1),
140 P1_5_LPSPI0_PCS2 = genMuxAlt(core::mux::MuxPortPin::P1_5, 2),
141 P1_5_LPUART2_TXD = genMuxAlt(core::mux::MuxPortPin::P1_5, 3),
142 P1_5_CT1_MAT3 = genMuxAlt(core::mux::MuxPortPin::P1_5, 4),
143
144 P1_6_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_6, 0),
145 P1_6_TRIG_IN2 = genMuxAlt(core::mux::MuxPortPin::P1_6, 0),
146 P1_6_LPSPI0_PCS1 = genMuxAlt(core::mux::MuxPortPin::P1_6, 0),
147 P1_6_LPUART2_RTS_B = genMuxAlt(core::mux::MuxPortPin::P1_6, 0),
148 P1_6_CT_INP6 = genMuxAlt(core::mux::MuxPortPin::P1_6, 0),
149
150 P1_7_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_7, 0),
151 P1_7_TRIG_OUT2 = genMuxAlt(core::mux::MuxPortPin::P1_7, 1),
152 P1_7_LPUART2_CTS_B = genMuxAlt(core::mux::MuxPortPin::P1_7, 3),
153 P1_7_CT_INP7 = genMuxAlt(core::mux::MuxPortPin::P1_7, 4),
154
155 P1_8_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_8, 0),
156 P1_8_LPUART1_RXD = genMuxAlt(core::mux::MuxPortPin::P1_8, 2),
157 P1_8_LPI2C0_SDA = genMuxAlt(core::mux::MuxPortPin::P1_8, 3),
158 P1_8_CT_INP8 = genMuxAlt(core::mux::MuxPortPin::P1_8, 4),
159 P1_8_CT0_MAT2 = genMuxAlt(core::mux::MuxPortPin::P1_8, 5),
160 P1_8_I3C0_SDA = genMuxAlt(core::mux::MuxPortPin::P1_8, 10),
161
162 P1_9_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_9, 0),
163 P1_9_LPUART1_TXD = genMuxAlt(core::mux::MuxPortPin::P1_9, 2),
164 P1_9_LPI2C0_SCL = genMuxAlt(core::mux::MuxPortPin::P1_9, 3),
165 P1_9_CT_INP9 = genMuxAlt(core::mux::MuxPortPin::P1_9, 4),
166 P1_9_CT0_MAT3 = genMuxAlt(core::mux::MuxPortPin::P1_9, 5),
167 P1_9_I3C0_SCL = genMuxAlt(core::mux::MuxPortPin::P1_9, 10),
168
169 P1_10_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_10, 0),
170 P1_10_LPUART1_RTS_B = genMuxAlt(core::mux::MuxPortPin::P1_10, 2),
171 P1_10_LPI2C0_SDAS = genMuxAlt(core::mux::MuxPortPin::P1_10, 3),
172 P1_10_CT2_MAT0 = genMuxAlt(core::mux::MuxPortPin::P1_10, 4),
173
174 P1_11_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_11, 0),
175 P1_11_TRIG_OUT2 = genMuxAlt(core::mux::MuxPortPin::P1_11, 1),
176 P1_11_LPUART1_CTS_B = genMuxAlt(core::mux::MuxPortPin::P1_11, 2),
177 P1_11_LPI2C0_SCLS = genMuxAlt(core::mux::MuxPortPin::P1_11, 3),
178 P1_11_CT2_MAT1 = genMuxAlt(core::mux::MuxPortPin::P1_11, 4),
179 P1_11_I3C0_PUR = genMuxAlt(core::mux::MuxPortPin::P1_11, 10),
180
181 P1_12_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_12, 0),
182 P1_12_LPUART2_RXD = genMuxAlt(core::mux::MuxPortPin::P1_12, 3),
183 P1_12_CT2_MAT2 = genMuxAlt(core::mux::MuxPortPin::P1_12, 4),
184
185 P1_13_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_13, 0),
186 P1_13_TRIG_IN3 = genMuxAlt(core::mux::MuxPortPin::P1_13, 1),
187 P1_13_LPUART2_TXD = genMuxAlt(core::mux::MuxPortPin::P1_13, 3),
188 P1_13_CT2_MAT3 = genMuxAlt(core::mux::MuxPortPin::P1_13, 4),
189
190 P1_29_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_29, 0),
191 P1_29_RESET_B = genMuxAlt(core::mux::MuxPortPin::P1_29, 1),
192 P1_29_SPC_LPREQ = genMuxAlt(core::mux::MuxPortPin::P1_29, 2),
193
194 P1_30_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_30, 0),
195 P1_30_TRIG_OUT3 = genMuxAlt(core::mux::MuxPortPin::P1_30, 1),
196 P1_30_LPI2C0_SDA = genMuxAlt(core::mux::MuxPortPin::P1_30, 3),
197 P1_30_CT_INP16 = genMuxAlt(core::mux::MuxPortPin::P1_30, 4),
198 P1_30_I3C0_SDA = genMuxAlt(core::mux::MuxPortPin::P1_30, 10),
199
200 P1_31_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_31, 0),
201 P1_31_TRIG_IN4 = genMuxAlt(core::mux::MuxPortPin::P1_31, 1),
202 P1_31_LPI2C0_SCL = genMuxAlt(core::mux::MuxPortPin::P1_31, 3),
203 P1_31_CT_INP17 = genMuxAlt(core::mux::MuxPortPin::P1_31, 4),
204 P1_31_I3C0_SCL = genMuxAlt(core::mux::MuxPortPin::P1_31, 10),
205
206 P2_0_GPIO = genMuxAlt(core::mux::MuxPortPin::P2_0, 0),
207 P2_0_TRIG_IN6 = genMuxAlt(core::mux::MuxPortPin::P2_0, 1),
208 P2_0_LPUART0_RXD = genMuxAlt(core::mux::MuxPortPin::P2_0, 2),
209 P2_0_CT_INP16 = genMuxAlt(core::mux::MuxPortPin::P2_0, 4),
210 P2_0_CT2_MAT0 = genMuxAlt(core::mux::MuxPortPin::P2_0, 5),
211
212 P2_1_GPIO = genMuxAlt(core::mux::MuxPortPin::P2_1, 0),
213 P2_1_TRIG_IN7 = genMuxAlt(core::mux::MuxPortPin::P2_1, 1),
214 P2_1_LPUART0_TXD = genMuxAlt(core::mux::MuxPortPin::P2_1, 2),
215 P2_1_CT_INP17 = genMuxAlt(core::mux::MuxPortPin::P2_1, 4),
216 P2_1_CT2_MAT1 = genMuxAlt(core::mux::MuxPortPin::P2_1, 5),
217
218 P2_2_GPIO = genMuxAlt(core::mux::MuxPortPin::P2_2, 0),
219 P2_2_TRIG_IN6 = genMuxAlt(core::mux::MuxPortPin::P2_2, 1),
220 P2_2_LPUART0_RTS_B = genMuxAlt(core::mux::MuxPortPin::P2_2, 2),
221 P2_2_LPUART2_TXD = genMuxAlt(core::mux::MuxPortPin::P2_2, 3),
222 P2_2_CT_INP12 = genMuxAlt(core::mux::MuxPortPin::P2_2, 4),
223 P2_2_CT2_MAT2 = genMuxAlt(core::mux::MuxPortPin::P2_2, 5),
224
225 P2_3_GPIO = genMuxAlt(core::mux::MuxPortPin::P2_3, 0),
226 P2_3_TRIG_IN7 = genMuxAlt(core::mux::MuxPortPin::P2_3, 1),
227 P2_3_LPUART0_CTS_B = genMuxAlt(core::mux::MuxPortPin::P2_3, 2),
228 P2_3_LPUART2_RXD = genMuxAlt(core::mux::MuxPortPin::P2_3, 3),
229 P2_3_CT_INP13 = genMuxAlt(core::mux::MuxPortPin::P2_3, 4),
230 P2_3_CT2_MAT3 = genMuxAlt(core::mux::MuxPortPin::P2_3, 5),
231
232 P2_4_GPIO = genMuxAlt(core::mux::MuxPortPin::P2_4, 0),
233 P2_4_CT_INP14 = genMuxAlt(core::mux::MuxPortPin::P2_4, 1),
234 P2_4_CT1_MAT0 = genMuxAlt(core::mux::MuxPortPin::P2_4, 2),
235
236 P2_5_GPIO = genMuxAlt(core::mux::MuxPortPin::P2_5, 0),
237 P2_5_CT_INP15 = genMuxAlt(core::mux::MuxPortPin::P2_5, 1),
238 P2_5_CT1_MAT1 = genMuxAlt(core::mux::MuxPortPin::P2_5, 2),
239
240 P2_6_GPIO = genMuxAlt(core::mux::MuxPortPin::P2_6, 0),
241 P2_6_TRIG_OUT4 = genMuxAlt(core::mux::MuxPortPin::P2_6, 1),
242 P2_6_LPSPI1_PCS1 = genMuxAlt(core::mux::MuxPortPin::P2_6, 2),
243 P2_6_CT_INP18 = genMuxAlt(core::mux::MuxPortPin::P2_6, 4),
244 P2_6_CT1_MAT2 = genMuxAlt(core::mux::MuxPortPin::P2_6, 5),
245
246 P2_7_GPIO = genMuxAlt(core::mux::MuxPortPin::P2_7, 0),
247 P2_7_TRIG_IN5 = genMuxAlt(core::mux::MuxPortPin::P2_7, 1),
248 P2_7_CT_INP19 = genMuxAlt(core::mux::MuxPortPin::P2_7, 4),
249 P2_7_CT1_MAT3 = genMuxAlt(core::mux::MuxPortPin::P2_7, 5),
250
251 P2_12_GPIO = genMuxAlt(core::mux::MuxPortPin::P2_12, 0),
252 P2_12_USB0_VBUS_DET = genMuxAlt(core::mux::MuxPortPin::P2_12, 1),
253 P2_12_LPSPI1_SCK = genMuxAlt(core::mux::MuxPortPin::P2_12, 2),
254 P2_12_LPUART1_RXD = genMuxAlt(core::mux::MuxPortPin::P2_12, 3),
255 P2_12_CT0_MAT0 = genMuxAlt(core::mux::MuxPortPin::P2_12, 5),
256
257 P2_13_GPIO = genMuxAlt(core::mux::MuxPortPin::P2_13, 0),
258 P2_13_TRIG_IN8 = genMuxAlt(core::mux::MuxPortPin::P2_13, 1),
259 P2_13_LPSPI1_SDO = genMuxAlt(core::mux::MuxPortPin::P2_13, 2),
260 P2_13_LPUART1_TXD = genMuxAlt(core::mux::MuxPortPin::P2_13, 3),
261 P2_13_CT0_MAT1 = genMuxAlt(core::mux::MuxPortPin::P2_13, 5),
262
263 P2_16_GPIO = genMuxAlt(core::mux::MuxPortPin::P2_16, 0),
264 P2_16_LPSPI1_SDI = genMuxAlt(core::mux::MuxPortPin::P2_16, 2),
265 P2_16_LPUART1_RTS_B = genMuxAlt(core::mux::MuxPortPin::P2_16, 3),
266 P2_16_CT0_MAT2 = genMuxAlt(core::mux::MuxPortPin::P2_16, 5),
267
268 P3_0_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_0, 0),
269 P3_0_TRIG_IN0 = genMuxAlt(core::mux::MuxPortPin::P3_0, 1),
270 P3_0_CT_INP16 = genMuxAlt(core::mux::MuxPortPin::P3_0, 4),
271 P3_0_PWM0_A0 = genMuxAlt(core::mux::MuxPortPin::P3_0, 5),
272
273 P3_1_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_1, 0),
274 P3_1_TRIG_IN1 = genMuxAlt(core::mux::MuxPortPin::P3_1, 1),
275 P3_1_CT_INP17 = genMuxAlt(core::mux::MuxPortPin::P3_1, 4),
276 P3_1_PWM0_B0 = genMuxAlt(core::mux::MuxPortPin::P3_1, 5),
277 P3_1_FREQME_CLK_OUT0 = genMuxAlt(core::mux::MuxPortPin::P3_1, 12),
278
279 P3_6_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_6, 0),
280 P3_6_CLKOUT = genMuxAlt(core::mux::MuxPortPin::P3_6, 1),
281 P3_6_LPSPI1_PCS3 = genMuxAlt(core::mux::MuxPortPin::P3_6, 2),
282 P3_6_PWM0_A0 = genMuxAlt(core::mux::MuxPortPin::P3_6, 5),
283 P3_6_FREQME_CLK_OUT1 = genMuxAlt(core::mux::MuxPortPin::P3_6, 12),
284
285 P3_7_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_7, 0),
286 P3_7_TRIG_IN2 = genMuxAlt(core::mux::MuxPortPin::P3_7, 1),
287 P3_7_LPSPI1_PCS2 = genMuxAlt(core::mux::MuxPortPin::P3_7, 2),
288 P3_7_PWM0_B0 = genMuxAlt(core::mux::MuxPortPin::P3_7, 5),
289
290 P3_8_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_8, 0),
291 P3_8_TRIG_IN3 = genMuxAlt(core::mux::MuxPortPin::P3_8, 1),
292 P3_8_LPSPI1_SDO = genMuxAlt(core::mux::MuxPortPin::P3_8, 2),
293 P3_8_LPUART1_RXD = genMuxAlt(core::mux::MuxPortPin::P3_8, 3),
294 P3_8_CT_INP4 = genMuxAlt(core::mux::MuxPortPin::P3_8, 4),
295 P3_8_PWM0_A1 = genMuxAlt(core::mux::MuxPortPin::P3_8, 5),
296 P3_8_CLKOUT = genMuxAlt(core::mux::MuxPortPin::P3_8, 12),
297
298 P3_9_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_9, 0),
299 P3_9_TRIG_IN4 = genMuxAlt(core::mux::MuxPortPin::P3_9, 1),
300 P3_9_LPSPI1_SDI = genMuxAlt(core::mux::MuxPortPin::P3_9, 2),
301 P3_9_LPUART1_TXD = genMuxAlt(core::mux::MuxPortPin::P3_9, 3),
302 P3_9_CT_INP5 = genMuxAlt(core::mux::MuxPortPin::P3_9, 4),
303 P3_9_PWM0_B1 = genMuxAlt(core::mux::MuxPortPin::P3_9, 5),
304
305 P3_10_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_10, 0),
306 P3_10_TRIG_IN5 = genMuxAlt(core::mux::MuxPortPin::P3_10, 1),
307 P3_10_LPSPI1_SCK = genMuxAlt(core::mux::MuxPortPin::P3_10, 2),
308 P3_10_LPUART1_RTS_B = genMuxAlt(core::mux::MuxPortPin::P3_10, 3),
309 P3_10_CT1_MAT0 = genMuxAlt(core::mux::MuxPortPin::P3_10, 4),
310 P3_10_PWM0_A2 = genMuxAlt(core::mux::MuxPortPin::P3_10, 5),
311
312 P3_11_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_11, 0),
313 P3_11_TRIG_IN6 = genMuxAlt(core::mux::MuxPortPin::P3_11, 1),
314 P3_11_LPSPI1_PCS0 = genMuxAlt(core::mux::MuxPortPin::P3_11, 2),
315 P3_11_LPUART1_CTS_B = genMuxAlt(core::mux::MuxPortPin::P3_11, 3),
316 P3_11_CT1_MAT1 = genMuxAlt(core::mux::MuxPortPin::P3_11, 4),
317 P3_11_PWM0_B2 = genMuxAlt(core::mux::MuxPortPin::P3_11, 5),
318
319 P3_12_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_12, 0),
320 P3_12_LPUART2_RTS_B = genMuxAlt(core::mux::MuxPortPin::P3_12, 2),
321 P3_12_CT1_MAT2 = genMuxAlt(core::mux::MuxPortPin::P3_12, 4),
322 P3_12_PWM0_X0 = genMuxAlt(core::mux::MuxPortPin::P3_12, 5),
323
324 P3_13_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_13, 0),
325 P3_13_LPUART2_CTS_B = genMuxAlt(core::mux::MuxPortPin::P3_13, 2),
326 P3_13_CT1_MAT3 = genMuxAlt(core::mux::MuxPortPin::P3_13, 4),
327 P3_13_PWM0_X1 = genMuxAlt(core::mux::MuxPortPin::P3_13, 5),
328
329 P3_14_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_14, 0),
330 P3_14_LPUART2_RXD = genMuxAlt(core::mux::MuxPortPin::P3_14, 2),
331 P3_14_CT_INP6 = genMuxAlt(core::mux::MuxPortPin::P3_14, 4),
332 P3_14_PWM0_X2 = genMuxAlt(core::mux::MuxPortPin::P3_14, 5),
333
334 P3_15_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_15, 0),
335 P3_15_LPUART2_TXD = genMuxAlt(core::mux::MuxPortPin::P3_15, 2),
336 P3_15_CT_INP7 = genMuxAlt(core::mux::MuxPortPin::P3_15, 4),
337
338 P3_27_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_27, 0),
339 P3_27_TRIG_OUT7 = genMuxAlt(core::mux::MuxPortPin::P3_27, 1),
340 P3_27_LPI2C0_SCL = genMuxAlt(core::mux::MuxPortPin::P3_27, 2),
341 P3_27_CT_INP13 = genMuxAlt(core::mux::MuxPortPin::P3_27, 4),
342
343 P3_28_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_28, 0),
344 P3_28_TRIG_IN11 = genMuxAlt(core::mux::MuxPortPin::P3_28, 1),
345 P3_28_LPI2C0_SDA = genMuxAlt(core::mux::MuxPortPin::P3_28, 2),
346 P3_28_CT_INP12 = genMuxAlt(core::mux::MuxPortPin::P3_28, 4),
347
348 P3_29_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_29, 0),
349 P3_29_ISPMODE_N = genMuxAlt(core::mux::MuxPortPin::P3_29, 1),
350 P3_29_CT_INP3 = genMuxAlt(core::mux::MuxPortPin::P3_29, 4),
351
352 P3_30_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_30, 0),
353 P3_30_TRIG_OUT6 = genMuxAlt(core::mux::MuxPortPin::P3_30, 1),
354 P3_30_CT0_MAT2 = genMuxAlt(core::mux::MuxPortPin::P3_30, 4),
355
356 P3_31_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_31, 0),
357 P3_31_TRIG_IN10 = genMuxAlt(core::mux::MuxPortPin::P3_31, 1),
358 P3_31_CT0_MAT3 = genMuxAlt(core::mux::MuxPortPin::P3_31, 4),
359
360 NONE = 0xFFFFFFFF
361};
362
363/* ***************************************************************************************
364 * End of file
365 */
366
367#endif /* CORE_7E9D719A_76F9_4D7D_86D0_B2F9958C74F3 */
chip::port::Mux
Mux
Definition chip/src/port/Mux.h:33
core::mux
Definition ctimer0/MAT0.h:23