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命名空間(Namespaces) | 列舉型態 | 函式
core::mux 命名空間(Namespace)參考文件

命名空間(Namespaces)

namespace  ctimer0
 
namespace  ctimer1
 
namespace  ctimer2
 
namespace  gpio0
 
namespace  gpio1
 
namespace  gpio2
 
namespace  gpio3
 
namespace  lpi2c0
 
namespace  lpuart0
 
namespace  lpuart1
 
namespace  lpuart2
 

列舉型態

enum struct  Mux : uint32 {
  P0_0_GPIO = genMuxAlt(core::mux::MuxPortPin::P0_0, 0) , P0_0_TMS_SWDIO = genMuxAlt(core::mux::MuxPortPin::P0_0, 1) , P0_0_LPUART0_RTS_B = genMuxAlt(core::mux::MuxPortPin::P0_0, 2) , P0_0_LPSPI0_PCS0 = genMuxAlt(core::mux::MuxPortPin::P0_0, 3) ,
  P0_0_CT_INP0 = genMuxAlt(core::mux::MuxPortPin::P0_0, 4) , P0_1_GPIO = genMuxAlt(core::mux::MuxPortPin::P0_1, 0) , P0_1_TCLK_SWCLK = genMuxAlt(core::mux::MuxPortPin::P0_1, 1) , P0_1_LPUART0_CTS_B = genMuxAlt(core::mux::MuxPortPin::P0_1, 2) ,
  P0_1_LPSPI0_SDI = genMuxAlt(core::mux::MuxPortPin::P0_1, 3) , P0_1_CT_INP1 = genMuxAlt(core::mux::MuxPortPin::P0_1, 4) , P0_2_GPIO = genMuxAlt(core::mux::MuxPortPin::P0_2, 0) , P0_2_TDO_SWO = genMuxAlt(core::mux::MuxPortPin::P0_2, 1) ,
  P0_2_LPUART0_RXD = genMuxAlt(core::mux::MuxPortPin::P0_2, 2) , P0_2_LPSPI0_SCK = genMuxAlt(core::mux::MuxPortPin::P0_2, 3) , P0_2_CT0_MAT0 = genMuxAlt(core::mux::MuxPortPin::P0_2, 4) , P0_2_UTICK_CAP0 = genMuxAlt(core::mux::MuxPortPin::P0_2, 5) ,
  P0_2_I3C0_PUR = genMuxAlt(core::mux::MuxPortPin::P0_2, 10) , P0_3_GPIO = genMuxAlt(core::mux::MuxPortPin::P0_3, 0) , P0_3_TDI = genMuxAlt(core::mux::MuxPortPin::P0_3, 1) , P0_3_LPUART0_TXD = genMuxAlt(core::mux::MuxPortPin::P0_3, 2) ,
  P0_3_LPSPI0_SDO = genMuxAlt(core::mux::MuxPortPin::P0_3, 3) , P0_3_CT0_MAT1 = genMuxAlt(core::mux::MuxPortPin::P0_3, 4) , P0_3_UTICK_CAP1 = genMuxAlt(core::mux::MuxPortPin::P0_3, 5) , P0_3_CMP0_OUT = genMuxAlt(core::mux::MuxPortPin::P0_3, 8) ,
  P0_6_GPIO = genMuxAlt(core::mux::MuxPortPin::P0_6, 0) , P0_6_LPI2C0_HREQ = genMuxAlt(core::mux::MuxPortPin::P0_6, 2) , P0_6_LPSPI0_PCS1 = genMuxAlt(core::mux::MuxPortPin::P0_6, 3) , P0_6_CT_INP2 = genMuxAlt(core::mux::MuxPortPin::P0_6, 4) ,
  P0_6_CMP1_OUT = genMuxAlt(core::mux::MuxPortPin::P0_6, 8) , P0_6_CLKOUT = genMuxAlt(core::mux::MuxPortPin::P0_6, 12) , P0_16_GPIO = genMuxAlt(core::mux::MuxPortPin::P0_16, 0) , P0_16_LPI2C0_SDA = genMuxAlt(core::mux::MuxPortPin::P0_16, 2) ,
  P0_16_LPSPI0_PCS2 = genMuxAlt(core::mux::MuxPortPin::P0_16, 3) , P0_16_CT0_MAT0 = genMuxAlt(core::mux::MuxPortPin::P0_16, 4) , P0_16_UTICK_CAP2 = genMuxAlt(core::mux::MuxPortPin::P0_16, 5) , P0_16_I3C0_SDA = genMuxAlt(core::mux::MuxPortPin::P0_16, 10) ,
  P0_17_GPIO = genMuxAlt(core::mux::MuxPortPin::P0_17, 0) , P0_17_LPI2C0_SCL = genMuxAlt(core::mux::MuxPortPin::P0_17, 2) , P0_17_LPSPI0_PCS3 = genMuxAlt(core::mux::MuxPortPin::P0_17, 3) , P0_17_CT0_MAT1 = genMuxAlt(core::mux::MuxPortPin::P0_17, 4) ,
  P0_17_UTICK_CAP3 = genMuxAlt(core::mux::MuxPortPin::P0_17, 5) , P0_17_I3C0_SCL = genMuxAlt(core::mux::MuxPortPin::P0_17, 10) , P1_0_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_0, 0) , P1_0_TRIG_IN0 = genMuxAlt(core::mux::MuxPortPin::P1_0, 1) ,
  P1_0_LPSPI0_SDO = genMuxAlt(core::mux::MuxPortPin::P1_0, 2) , P1_0_LPI2C0_SDA = genMuxAlt(core::mux::MuxPortPin::P1_0, 3) , P1_0_CT_INP4 = genMuxAlt(core::mux::MuxPortPin::P1_0, 4) , P1_0_CT0_MAT2 = genMuxAlt(core::mux::MuxPortPin::P1_0, 5) ,
  P1_1_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_1, 0) , P1_1_TRIG_IN1 = genMuxAlt(core::mux::MuxPortPin::P1_1, 1) , P1_1_LPSPI0_SCK = genMuxAlt(core::mux::MuxPortPin::P1_1, 2) , P1_1_LPI2C0_SCL = genMuxAlt(core::mux::MuxPortPin::P1_1, 3) ,
  P1_1_CT_INP5 = genMuxAlt(core::mux::MuxPortPin::P1_1, 4) , P1_1_CT0_MAT3 = genMuxAlt(core::mux::MuxPortPin::P1_1, 5) , P1_2_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_2, 0) , P1_2_TRIG_OUT0 = genMuxAlt(core::mux::MuxPortPin::P1_2, 1) ,
  P1_2_LPSPI0_SDI = genMuxAlt(core::mux::MuxPortPin::P1_2, 2) , P1_2_LPI2C0_SDAS = genMuxAlt(core::mux::MuxPortPin::P1_2, 3) , P1_2_CT1_MAT0 = genMuxAlt(core::mux::MuxPortPin::P1_2, 4) , P1_2_CT_INP0 = genMuxAlt(core::mux::MuxPortPin::P1_2, 5) ,
  P1_3_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_3, 0) , P1_3_TRIG_OUT1 = genMuxAlt(core::mux::MuxPortPin::P1_3, 1) , P1_3_LPSPI0_PCS0 = genMuxAlt(core::mux::MuxPortPin::P1_3, 2) , P1_3_LPI2C0_SCLS = genMuxAlt(core::mux::MuxPortPin::P1_3, 3) ,
  P1_3_CT1_MAT1 = genMuxAlt(core::mux::MuxPortPin::P1_3, 4) , P1_3_CT_INP1 = genMuxAlt(core::mux::MuxPortPin::P1_3, 5) , P1_4_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_4, 0) , P1_4_FREQME_CLK_IN0 = genMuxAlt(core::mux::MuxPortPin::P1_4, 1) ,
  P1_4_LPSPI0_PCS3 = genMuxAlt(core::mux::MuxPortPin::P1_4, 2) , P1_4_LPUART2_RXD = genMuxAlt(core::mux::MuxPortPin::P1_4, 3) , P1_4_CT1_MAT2 = genMuxAlt(core::mux::MuxPortPin::P1_4, 4) , P1_5_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_5, 0) ,
  P1_5_FREQME_CLK_IN1 = genMuxAlt(core::mux::MuxPortPin::P1_5, 1) , P1_5_LPSPI0_PCS2 = genMuxAlt(core::mux::MuxPortPin::P1_5, 2) , P1_5_LPUART2_TXD = genMuxAlt(core::mux::MuxPortPin::P1_5, 3) , P1_5_CT1_MAT3 = genMuxAlt(core::mux::MuxPortPin::P1_5, 4) ,
  P1_6_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_6, 0) , P1_6_TRIG_IN2 = genMuxAlt(core::mux::MuxPortPin::P1_6, 0) , P1_6_LPSPI0_PCS1 = genMuxAlt(core::mux::MuxPortPin::P1_6, 0) , P1_6_LPUART2_RTS_B = genMuxAlt(core::mux::MuxPortPin::P1_6, 0) ,
  P1_6_CT_INP6 = genMuxAlt(core::mux::MuxPortPin::P1_6, 0) , P1_7_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_7, 0) , P1_7_TRIG_OUT2 = genMuxAlt(core::mux::MuxPortPin::P1_7, 1) , P1_7_LPUART2_CTS_B = genMuxAlt(core::mux::MuxPortPin::P1_7, 3) ,
  P1_7_CT_INP7 = genMuxAlt(core::mux::MuxPortPin::P1_7, 4) , P1_8_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_8, 0) , P1_8_LPUART1_RXD = genMuxAlt(core::mux::MuxPortPin::P1_8, 2) , P1_8_LPI2C0_SDA = genMuxAlt(core::mux::MuxPortPin::P1_8, 3) ,
  P1_8_CT_INP8 = genMuxAlt(core::mux::MuxPortPin::P1_8, 4) , P1_8_CT0_MAT2 = genMuxAlt(core::mux::MuxPortPin::P1_8, 5) , P1_8_I3C0_SDA = genMuxAlt(core::mux::MuxPortPin::P1_8, 10) , P1_9_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_9, 0) ,
  P1_9_LPUART1_TXD = genMuxAlt(core::mux::MuxPortPin::P1_9, 2) , P1_9_LPI2C0_SCL = genMuxAlt(core::mux::MuxPortPin::P1_9, 3) , P1_9_CT_INP9 = genMuxAlt(core::mux::MuxPortPin::P1_9, 4) , P1_9_CT0_MAT3 = genMuxAlt(core::mux::MuxPortPin::P1_9, 5) ,
  P1_9_I3C0_SCL = genMuxAlt(core::mux::MuxPortPin::P1_9, 10) , P1_10_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_10, 0) , P1_10_LPUART1_RTS_B = genMuxAlt(core::mux::MuxPortPin::P1_10, 2) , P1_10_LPI2C0_SDAS = genMuxAlt(core::mux::MuxPortPin::P1_10, 3) ,
  P1_10_CT2_MAT0 = genMuxAlt(core::mux::MuxPortPin::P1_10, 4) , P1_11_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_11, 0) , P1_11_TRIG_OUT2 = genMuxAlt(core::mux::MuxPortPin::P1_11, 1) , P1_11_LPUART1_CTS_B = genMuxAlt(core::mux::MuxPortPin::P1_11, 2) ,
  P1_11_LPI2C0_SCLS = genMuxAlt(core::mux::MuxPortPin::P1_11, 3) , P1_11_CT2_MAT1 = genMuxAlt(core::mux::MuxPortPin::P1_11, 4) , P1_11_I3C0_PUR = genMuxAlt(core::mux::MuxPortPin::P1_11, 10) , P1_12_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_12, 0) ,
  P1_12_LPUART2_RXD = genMuxAlt(core::mux::MuxPortPin::P1_12, 3) , P1_12_CT2_MAT2 = genMuxAlt(core::mux::MuxPortPin::P1_12, 4) , P1_13_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_13, 0) , P1_13_TRIG_IN3 = genMuxAlt(core::mux::MuxPortPin::P1_13, 1) ,
  P1_13_LPUART2_TXD = genMuxAlt(core::mux::MuxPortPin::P1_13, 3) , P1_13_CT2_MAT3 = genMuxAlt(core::mux::MuxPortPin::P1_13, 4) , P1_29_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_29, 0) , P1_29_RESET_B = genMuxAlt(core::mux::MuxPortPin::P1_29, 1) ,
  P1_29_SPC_LPREQ = genMuxAlt(core::mux::MuxPortPin::P1_29, 2) , P1_30_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_30, 0) , P1_30_TRIG_OUT3 = genMuxAlt(core::mux::MuxPortPin::P1_30, 1) , P1_30_LPI2C0_SDA = genMuxAlt(core::mux::MuxPortPin::P1_30, 3) ,
  P1_30_CT_INP16 = genMuxAlt(core::mux::MuxPortPin::P1_30, 4) , P1_30_I3C0_SDA = genMuxAlt(core::mux::MuxPortPin::P1_30, 10) , P1_31_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_31, 0) , P1_31_TRIG_IN4 = genMuxAlt(core::mux::MuxPortPin::P1_31, 1) ,
  P1_31_LPI2C0_SCL = genMuxAlt(core::mux::MuxPortPin::P1_31, 3) , P1_31_CT_INP17 = genMuxAlt(core::mux::MuxPortPin::P1_31, 4) , P1_31_I3C0_SCL = genMuxAlt(core::mux::MuxPortPin::P1_31, 10) , P2_0_GPIO = genMuxAlt(core::mux::MuxPortPin::P2_0, 0) ,
  P2_0_TRIG_IN6 = genMuxAlt(core::mux::MuxPortPin::P2_0, 1) , P2_0_LPUART0_RXD = genMuxAlt(core::mux::MuxPortPin::P2_0, 2) , P2_0_CT_INP16 = genMuxAlt(core::mux::MuxPortPin::P2_0, 4) , P2_0_CT2_MAT0 = genMuxAlt(core::mux::MuxPortPin::P2_0, 5) ,
  P2_1_GPIO = genMuxAlt(core::mux::MuxPortPin::P2_1, 0) , P2_1_TRIG_IN7 = genMuxAlt(core::mux::MuxPortPin::P2_1, 1) , P2_1_LPUART0_TXD = genMuxAlt(core::mux::MuxPortPin::P2_1, 2) , P2_1_CT_INP17 = genMuxAlt(core::mux::MuxPortPin::P2_1, 4) ,
  P2_1_CT2_MAT1 = genMuxAlt(core::mux::MuxPortPin::P2_1, 5) , P2_2_GPIO = genMuxAlt(core::mux::MuxPortPin::P2_2, 0) , P2_2_TRIG_IN6 = genMuxAlt(core::mux::MuxPortPin::P2_2, 1) , P2_2_LPUART0_RTS_B = genMuxAlt(core::mux::MuxPortPin::P2_2, 2) ,
  P2_2_LPUART2_TXD = genMuxAlt(core::mux::MuxPortPin::P2_2, 3) , P2_2_CT_INP12 = genMuxAlt(core::mux::MuxPortPin::P2_2, 4) , P2_2_CT2_MAT2 = genMuxAlt(core::mux::MuxPortPin::P2_2, 5) , P2_3_GPIO = genMuxAlt(core::mux::MuxPortPin::P2_3, 0) ,
  P2_3_TRIG_IN7 = genMuxAlt(core::mux::MuxPortPin::P2_3, 1) , P2_3_LPUART0_CTS_B = genMuxAlt(core::mux::MuxPortPin::P2_3, 2) , P2_3_LPUART2_RXD = genMuxAlt(core::mux::MuxPortPin::P2_3, 3) , P2_3_CT_INP13 = genMuxAlt(core::mux::MuxPortPin::P2_3, 4) ,
  P2_3_CT2_MAT3 = genMuxAlt(core::mux::MuxPortPin::P2_3, 5) , P2_4_GPIO = genMuxAlt(core::mux::MuxPortPin::P2_4, 0) , P2_4_CT_INP14 = genMuxAlt(core::mux::MuxPortPin::P2_4, 1) , P2_4_CT1_MAT0 = genMuxAlt(core::mux::MuxPortPin::P2_4, 2) ,
  P2_5_GPIO = genMuxAlt(core::mux::MuxPortPin::P2_5, 0) , P2_5_CT_INP15 = genMuxAlt(core::mux::MuxPortPin::P2_5, 1) , P2_5_CT1_MAT1 = genMuxAlt(core::mux::MuxPortPin::P2_5, 2) , P2_6_GPIO = genMuxAlt(core::mux::MuxPortPin::P2_6, 0) ,
  P2_6_TRIG_OUT4 = genMuxAlt(core::mux::MuxPortPin::P2_6, 1) , P2_6_LPSPI1_PCS1 = genMuxAlt(core::mux::MuxPortPin::P2_6, 2) , P2_6_CT_INP18 = genMuxAlt(core::mux::MuxPortPin::P2_6, 4) , P2_6_CT1_MAT2 = genMuxAlt(core::mux::MuxPortPin::P2_6, 5) ,
  P2_7_GPIO = genMuxAlt(core::mux::MuxPortPin::P2_7, 0) , P2_7_TRIG_IN5 = genMuxAlt(core::mux::MuxPortPin::P2_7, 1) , P2_7_CT_INP19 = genMuxAlt(core::mux::MuxPortPin::P2_7, 4) , P2_7_CT1_MAT3 = genMuxAlt(core::mux::MuxPortPin::P2_7, 5) ,
  P2_12_GPIO = genMuxAlt(core::mux::MuxPortPin::P2_12, 0) , P2_12_USB0_VBUS_DET = genMuxAlt(core::mux::MuxPortPin::P2_12, 1) , P2_12_LPSPI1_SCK = genMuxAlt(core::mux::MuxPortPin::P2_12, 2) , P2_12_LPUART1_RXD = genMuxAlt(core::mux::MuxPortPin::P2_12, 3) ,
  P2_12_CT0_MAT0 = genMuxAlt(core::mux::MuxPortPin::P2_12, 5) , P2_13_GPIO = genMuxAlt(core::mux::MuxPortPin::P2_13, 0) , P2_13_TRIG_IN8 = genMuxAlt(core::mux::MuxPortPin::P2_13, 1) , P2_13_LPSPI1_SDO = genMuxAlt(core::mux::MuxPortPin::P2_13, 2) ,
  P2_13_LPUART1_TXD = genMuxAlt(core::mux::MuxPortPin::P2_13, 3) , P2_13_CT0_MAT1 = genMuxAlt(core::mux::MuxPortPin::P2_13, 5) , P2_16_GPIO = genMuxAlt(core::mux::MuxPortPin::P2_16, 0) , P2_16_LPSPI1_SDI = genMuxAlt(core::mux::MuxPortPin::P2_16, 2) ,
  P2_16_LPUART1_RTS_B = genMuxAlt(core::mux::MuxPortPin::P2_16, 3) , P2_16_CT0_MAT2 = genMuxAlt(core::mux::MuxPortPin::P2_16, 5) , P3_0_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_0, 0) , P3_0_TRIG_IN0 = genMuxAlt(core::mux::MuxPortPin::P3_0, 1) ,
  P3_0_CT_INP16 = genMuxAlt(core::mux::MuxPortPin::P3_0, 4) , P3_0_PWM0_A0 = genMuxAlt(core::mux::MuxPortPin::P3_0, 5) , P3_1_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_1, 0) , P3_1_TRIG_IN1 = genMuxAlt(core::mux::MuxPortPin::P3_1, 1) ,
  P3_1_CT_INP17 = genMuxAlt(core::mux::MuxPortPin::P3_1, 4) , P3_1_PWM0_B0 = genMuxAlt(core::mux::MuxPortPin::P3_1, 5) , P3_1_FREQME_CLK_OUT0 = genMuxAlt(core::mux::MuxPortPin::P3_1, 12) , P3_6_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_6, 0) ,
  P3_6_CLKOUT = genMuxAlt(core::mux::MuxPortPin::P3_6, 1) , P3_6_LPSPI1_PCS3 = genMuxAlt(core::mux::MuxPortPin::P3_6, 2) , P3_6_PWM0_A0 = genMuxAlt(core::mux::MuxPortPin::P3_6, 5) , P3_6_FREQME_CLK_OUT1 = genMuxAlt(core::mux::MuxPortPin::P3_6, 12) ,
  P3_7_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_7, 0) , P3_7_TRIG_IN2 = genMuxAlt(core::mux::MuxPortPin::P3_7, 1) , P3_7_LPSPI1_PCS2 = genMuxAlt(core::mux::MuxPortPin::P3_7, 2) , P3_7_PWM0_B0 = genMuxAlt(core::mux::MuxPortPin::P3_7, 5) ,
  P3_8_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_8, 0) , P3_8_TRIG_IN3 = genMuxAlt(core::mux::MuxPortPin::P3_8, 1) , P3_8_LPSPI1_SDO = genMuxAlt(core::mux::MuxPortPin::P3_8, 2) , P3_8_LPUART1_RXD = genMuxAlt(core::mux::MuxPortPin::P3_8, 3) ,
  P3_8_CT_INP4 = genMuxAlt(core::mux::MuxPortPin::P3_8, 4) , P3_8_PWM0_A1 = genMuxAlt(core::mux::MuxPortPin::P3_8, 5) , P3_8_CLKOUT = genMuxAlt(core::mux::MuxPortPin::P3_8, 12) , P3_9_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_9, 0) ,
  P3_9_TRIG_IN4 = genMuxAlt(core::mux::MuxPortPin::P3_9, 1) , P3_9_LPSPI1_SDI = genMuxAlt(core::mux::MuxPortPin::P3_9, 2) , P3_9_LPUART1_TXD = genMuxAlt(core::mux::MuxPortPin::P3_9, 3) , P3_9_CT_INP5 = genMuxAlt(core::mux::MuxPortPin::P3_9, 4) ,
  P3_9_PWM0_B1 = genMuxAlt(core::mux::MuxPortPin::P3_9, 5) , P3_10_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_10, 0) , P3_10_TRIG_IN5 = genMuxAlt(core::mux::MuxPortPin::P3_10, 1) , P3_10_LPSPI1_SCK = genMuxAlt(core::mux::MuxPortPin::P3_10, 2) ,
  P3_10_LPUART1_RTS_B = genMuxAlt(core::mux::MuxPortPin::P3_10, 3) , P3_10_CT1_MAT0 = genMuxAlt(core::mux::MuxPortPin::P3_10, 4) , P3_10_PWM0_A2 = genMuxAlt(core::mux::MuxPortPin::P3_10, 5) , P3_11_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_11, 0) ,
  P3_11_TRIG_IN6 = genMuxAlt(core::mux::MuxPortPin::P3_11, 1) , P3_11_LPSPI1_PCS0 = genMuxAlt(core::mux::MuxPortPin::P3_11, 2) , P3_11_LPUART1_CTS_B = genMuxAlt(core::mux::MuxPortPin::P3_11, 3) , P3_11_CT1_MAT1 = genMuxAlt(core::mux::MuxPortPin::P3_11, 4) ,
  P3_11_PWM0_B2 = genMuxAlt(core::mux::MuxPortPin::P3_11, 5) , P3_12_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_12, 0) , P3_12_LPUART2_RTS_B = genMuxAlt(core::mux::MuxPortPin::P3_12, 2) , P3_12_CT1_MAT2 = genMuxAlt(core::mux::MuxPortPin::P3_12, 4) ,
  P3_12_PWM0_X0 = genMuxAlt(core::mux::MuxPortPin::P3_12, 5) , P3_13_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_13, 0) , P3_13_LPUART2_CTS_B = genMuxAlt(core::mux::MuxPortPin::P3_13, 2) , P3_13_CT1_MAT3 = genMuxAlt(core::mux::MuxPortPin::P3_13, 4) ,
  P3_13_PWM0_X1 = genMuxAlt(core::mux::MuxPortPin::P3_13, 5) , P3_14_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_14, 0) , P3_14_LPUART2_RXD = genMuxAlt(core::mux::MuxPortPin::P3_14, 2) , P3_14_CT_INP6 = genMuxAlt(core::mux::MuxPortPin::P3_14, 4) ,
  P3_14_PWM0_X2 = genMuxAlt(core::mux::MuxPortPin::P3_14, 5) , P3_15_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_15, 0) , P3_15_LPUART2_TXD = genMuxAlt(core::mux::MuxPortPin::P3_15, 2) , P3_15_CT_INP7 = genMuxAlt(core::mux::MuxPortPin::P3_15, 4) ,
  P3_27_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_27, 0) , P3_27_TRIG_OUT7 = genMuxAlt(core::mux::MuxPortPin::P3_27, 1) , P3_27_LPI2C0_SCL = genMuxAlt(core::mux::MuxPortPin::P3_27, 2) , P3_27_CT_INP13 = genMuxAlt(core::mux::MuxPortPin::P3_27, 4) ,
  P3_28_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_28, 0) , P3_28_TRIG_IN11 = genMuxAlt(core::mux::MuxPortPin::P3_28, 1) , P3_28_LPI2C0_SDA = genMuxAlt(core::mux::MuxPortPin::P3_28, 2) , P3_28_CT_INP12 = genMuxAlt(core::mux::MuxPortPin::P3_28, 4) ,
  P3_29_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_29, 0) , P3_29_ISPMODE_N = genMuxAlt(core::mux::MuxPortPin::P3_29, 1) , P3_29_CT_INP3 = genMuxAlt(core::mux::MuxPortPin::P3_29, 4) , P3_30_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_30, 0) ,
  P3_30_TRIG_OUT6 = genMuxAlt(core::mux::MuxPortPin::P3_30, 1) , P3_30_CT0_MAT2 = genMuxAlt(core::mux::MuxPortPin::P3_30, 4) , P3_31_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_31, 0) , P3_31_TRIG_IN10 = genMuxAlt(core::mux::MuxPortPin::P3_31, 1) ,
  P3_31_CT0_MAT3 = genMuxAlt(core::mux::MuxPortPin::P3_31, 4) , NONE = 0xFFFFFFFF
}
 
enum struct  MuxPortPin : uint16 {
  P0_0 = genMuxPortPin(0, 0) , P0_1 = genMuxPortPin(0, 1) , P0_2 = genMuxPortPin(0, 2) , P0_3 = genMuxPortPin(0, 3) ,
  P0_6 = genMuxPortPin(0, 6) , P0_16 = genMuxPortPin(0, 16) , P0_17 = genMuxPortPin(0, 17) , P1_0 = genMuxPortPin(1, 0) ,
  P1_1 = genMuxPortPin(1, 1) , P1_2 = genMuxPortPin(1, 2) , P1_3 = genMuxPortPin(1, 3) , P1_4 = genMuxPortPin(1, 4) ,
  P1_5 = genMuxPortPin(1, 5) , P1_6 = genMuxPortPin(1, 6) , P1_7 = genMuxPortPin(1, 7) , P1_8 = genMuxPortPin(1, 8) ,
  P1_9 = genMuxPortPin(1, 9) , P1_10 = genMuxPortPin(1, 10) , P1_11 = genMuxPortPin(1, 11) , P1_12 = genMuxPortPin(1, 12) ,
  P1_13 = genMuxPortPin(1, 13) , P1_29 = genMuxPortPin(1, 29) , P1_30 = genMuxPortPin(1, 30) , P1_31 = genMuxPortPin(1, 31) ,
  P2_0 = genMuxPortPin(2, 0) , P2_1 = genMuxPortPin(2, 1) , P2_2 = genMuxPortPin(2, 2) , P2_3 = genMuxPortPin(2, 3) ,
  P2_4 = genMuxPortPin(2, 4) , P2_5 = genMuxPortPin(2, 5) , P2_6 = genMuxPortPin(2, 6) , P2_7 = genMuxPortPin(2, 7) ,
  P2_12 = genMuxPortPin(2, 12) , P2_13 = genMuxPortPin(2, 13) , P2_16 = genMuxPortPin(2, 16) , P3_0 = genMuxPortPin(3, 0) ,
  P3_1 = genMuxPortPin(3, 1) , P3_6 = genMuxPortPin(3, 6) , P3_7 = genMuxPortPin(3, 7) , P3_8 = genMuxPortPin(3, 8) ,
  P3_9 = genMuxPortPin(3, 9) , P3_10 = genMuxPortPin(3, 10) , P3_11 = genMuxPortPin(3, 11) , P3_12 = genMuxPortPin(3, 12) ,
  P3_13 = genMuxPortPin(3, 13) , P3_14 = genMuxPortPin(3, 14) , P3_15 = genMuxPortPin(3, 15) , P3_27 = genMuxPortPin(3, 27) ,
  P3_28 = genMuxPortPin(3, 28) , P3_29 = genMuxPortPin(3, 29) , P3_30 = genMuxPortPin(3, 30) , P3_31 = genMuxPortPin(3, 31)
}
 

函式

constexpr uint32 operator+ (Mux e)
 
constexpr uint16 operator+ (MuxPortPin e)
 

詳細描述

Copyright (c) 2020 ZxyKira All rights reserved.

SPDX-License-Identifier: MIT