MRCC.h

 
#ifndef CHIP_9C5F8B7F_C4AD_4DC2_977C_8B6A752259BE
#define CHIP_9C5F8B7F_C4AD_4DC2_977C_8B6A752259BE
 
/* ***************************************************************************************
 * Include
 */
 
//----------------------------------------------------------------------------------------
#include "mframe.h"
 
//----------------------------------------------------------------------------------------
#include "./Count.h"
#include "./Mask.h"
#include "./Register.h"
#include "./Shift.h"
 
/* ***************************************************************************************
 * Namespace
 */
namespace chip::mrcc {
  class MRCC;
  extern Register& MRCC0;
}  // namespace chip::mrcc
 
/* ***************************************************************************************
 * Class/Interface/Struct/Enum
 */
class chip::mrcc::MRCC final : public mframe::lang::Object {
  /* *************************************************************************************
   * Variable
   */
 
  /* *************************************************************************************
   * Abstract Method
   */
 
  /* *************************************************************************************
   * Construct Method
   */
 private:
  MRCC(void);
 
 public:
  virtual ~MRCC(void) override;
 
  /* *************************************************************************************
   * Operator Method
   */
 
  /* *************************************************************************************
   * Public Method <Override>
   */
 
  /* *************************************************************************************
   * Public Method
   */
 
  /* *************************************************************************************
   * Protected Method
   */
 
  /* *************************************************************************************
   * Private Method
   */
 
  /* *************************************************************************************
   * Static Variable
   */
 
  /* *************************************************************************************
   * Static Method
   */
 public:
  static inline constexpr uint32 GLB_RST0_INPUTMUX0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST0_INPUTMUX0) &
            +chip::mrcc::Mask::GLB_RST0_INPUTMUX0);
  }
 
  static inline constexpr uint32 GLB_RST0_I3C0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST0_I3C0) &
            +chip::mrcc::Mask::GLB_RST0_I3C0);
  }
 
  static inline constexpr uint32 GLB_RST0_CTIMER0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST0_CTIMER0) &
            +chip::mrcc::Mask::GLB_RST0_CTIMER0);
  }
 
  static inline constexpr uint32 GLB_RST0_CTIMER1(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST0_CTIMER1) &
            +chip::mrcc::Mask::GLB_RST0_CTIMER1);
  }
 
  static inline constexpr uint32 GLB_RST0_CTIMER2(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST0_CTIMER2) &
            +chip::mrcc::Mask::GLB_RST0_CTIMER2);
  }
 
  static inline constexpr uint32 GLB_RST0_CTIMER3(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST0_CTIMER3) &
            +chip::mrcc::Mask::GLB_RST0_CTIMER3);
  }
 
  static inline constexpr uint32 GLB_RST0_CTIMER4(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST0_CTIMER4) &
            +chip::mrcc::Mask::GLB_RST0_CTIMER4);
  }
 
  static inline constexpr uint32 GLB_RST0_FREQME(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST0_FREQME) &
            +chip::mrcc::Mask::GLB_RST0_FREQME);
  }
 
  static inline constexpr uint32 GLB_RST0_UTICK0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST0_UTICK0) &
            +chip::mrcc::Mask::GLB_RST0_UTICK0);
  }
 
  static inline constexpr uint32 GLB_RST0_DMA(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST0_DMA) &
            +chip::mrcc::Mask::GLB_RST0_DMA);
  }
 
  static inline constexpr uint32 GLB_RST0_AOI0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST0_AOI0) &
            +chip::mrcc::Mask::GLB_RST0_AOI0);
  }
 
  static inline constexpr uint32 GLB_RST0_CRC0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST0_CRC0) &
            +chip::mrcc::Mask::GLB_RST0_CRC0);
  }
 
  static inline constexpr uint32 GLB_RST0_EIM0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST0_EIM0) &
            +chip::mrcc::Mask::GLB_RST0_EIM0);
  }
 
  static inline constexpr uint32 GLB_RST0_ERM0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST0_ERM0) &
            +chip::mrcc::Mask::GLB_RST0_ERM0);
  }
 
  static inline constexpr uint32 GLB_RST0_AOI1(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST0_AOI1) &
            +chip::mrcc::Mask::GLB_RST0_AOI1);
  }
 
  static inline constexpr uint32 GLB_RST0_FLEXIO0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST0_FLEXIO0) &
            +chip::mrcc::Mask::GLB_RST0_FLEXIO0);
  }
 
  static inline constexpr uint32 GLB_RST0_LPI2C0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST0_LPI2C0) &
            +chip::mrcc::Mask::GLB_RST0_LPI2C0);
  }
 
  static inline constexpr uint32 GLB_RST0_LPI2C1(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST0_LPI2C1) &
            +chip::mrcc::Mask::GLB_RST0_LPI2C1);
  }
 
  static inline constexpr uint32 GLB_RST0_LPSPI0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST0_LPSPI0) &
            +chip::mrcc::Mask::GLB_RST0_LPSPI0);
  }
 
  static inline constexpr uint32 GLB_RST0_LPSPI1(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST0_LPSPI1) &
            +chip::mrcc::Mask::GLB_RST0_LPSPI1);
  }
 
  static inline constexpr uint32 GLB_RST0_LPUART0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST0_LPUART0) &
            +chip::mrcc::Mask::GLB_RST0_LPUART0);
  }
 
  static inline constexpr uint32 GLB_RST0_LPUART1(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST0_LPUART1) &
            +chip::mrcc::Mask::GLB_RST0_LPUART1);
  }
 
  static inline constexpr uint32 GLB_RST0_LPUART2(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST0_LPUART2) &
            +chip::mrcc::Mask::GLB_RST0_LPUART2);
  }
 
  static inline constexpr uint32 GLB_RST0_LPUART3(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST0_LPUART3) &
            +chip::mrcc::Mask::GLB_RST0_LPUART3);
  }
 
  static inline constexpr uint32 GLB_RST0_LPUART4(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST0_LPUART4) &
            +chip::mrcc::Mask::GLB_RST0_LPUART4);
  }
 
  static inline constexpr uint32 GLB_RST0_USB0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST0_USB0) &
            +chip::mrcc::Mask::GLB_RST0_USB0);
  }
 
  static inline constexpr uint32 GLB_RST0_QDC0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST0_QDC0) &
            +chip::mrcc::Mask::GLB_RST0_QDC0);
  }
 
  static inline constexpr uint32 GLB_RST0_QDC1(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST0_QDC1) &
            +chip::mrcc::Mask::GLB_RST0_QDC1);
  }
 
  static inline constexpr uint32 GLB_RST0_FLEXPWM0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST0_FLEXPWM0) &
            +chip::mrcc::Mask::GLB_RST0_FLEXPWM0);
  }
 
  static inline constexpr uint32 GLB_RST0_FLEXPWM1(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST0_FLEXPWM1) &
            +chip::mrcc::Mask::GLB_RST0_FLEXPWM1);
  }
 
  static inline constexpr uint32 GLB_RST0_SET_DATA(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST0_SET_DATA) &
            +chip::mrcc::Mask::GLB_RST0_SET_DATA);
  }
 
  static inline constexpr uint32 GLB_RST0_CLR_DATA(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST0_CLR_DATA) &
            +chip::mrcc::Mask::GLB_RST0_CLR_DATA);
  }
 
  static inline constexpr uint32 GLB_RST1_OSTIMER0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST1_OSTIMER0) &
            +chip::mrcc::Mask::GLB_RST1_OSTIMER0);
  }
 
  static inline constexpr uint32 GLB_RST1_ADC0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST1_ADC0) &
            +chip::mrcc::Mask::GLB_RST1_ADC0);
  }
 
  static inline constexpr uint32 GLB_RST1_ADC1(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST1_ADC1) &
            +chip::mrcc::Mask::GLB_RST1_ADC1);
  }
 
  static inline constexpr uint32 GLB_RST1_CMP1(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST1_CMP1) &
            +chip::mrcc::Mask::GLB_RST1_CMP1);
  }
 
  static inline constexpr uint32 GLB_RST1_DAC0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST1_DAC0) &
            +chip::mrcc::Mask::GLB_RST1_DAC0);
  }
 
  static inline constexpr uint32 GLB_RST1_OPAMP0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST1_OPAMP0) &
            +chip::mrcc::Mask::GLB_RST1_OPAMP0);
  }
 
  static inline constexpr uint32 GLB_RST1_PORT0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST1_PORT0) &
            +chip::mrcc::Mask::GLB_RST1_PORT0);
  }
 
  static inline constexpr uint32 GLB_RST1_PORT1(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST1_PORT1) &
            +chip::mrcc::Mask::GLB_RST1_PORT1);
  }
 
  static inline constexpr uint32 GLB_RST1_PORT2(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST1_PORT2) &
            +chip::mrcc::Mask::GLB_RST1_PORT2);
  }
 
  static inline constexpr uint32 GLB_RST1_PORT3(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST1_PORT3) &
            +chip::mrcc::Mask::GLB_RST1_PORT3);
  }
 
  static inline constexpr uint32 GLB_RST1_PORT4(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST1_PORT4) &
            +chip::mrcc::Mask::GLB_RST1_PORT4);
  }
 
  static inline constexpr uint32 GLB_RST1_FLEXCAN0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST1_FLEXCAN0) &
            +chip::mrcc::Mask::GLB_RST1_FLEXCAN0);
  }
 
  static inline constexpr uint32 GLB_RST1_LPI2C2(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST1_LPI2C2) &
            +chip::mrcc::Mask::GLB_RST1_LPI2C2);
  }
 
  static inline constexpr uint32 GLB_RST1_LPI2C3(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST1_LPI2C3) &
            +chip::mrcc::Mask::GLB_RST1_LPI2C3);
  }
 
  static inline constexpr uint32 GLB_RST1_GPIO0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST1_GPIO0) &
            +chip::mrcc::Mask::GLB_RST1_GPIO0);
  }
 
  static inline constexpr uint32 GLB_RST1_GPIO1(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST1_GPIO1) &
            +chip::mrcc::Mask::GLB_RST1_GPIO1);
  }
 
  static inline constexpr uint32 GLB_RST1_GPIO2(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST1_GPIO2) &
            +chip::mrcc::Mask::GLB_RST1_GPIO2);
  }
 
  static inline constexpr uint32 GLB_RST1_GPIO3(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST1_GPIO3) &
            +chip::mrcc::Mask::GLB_RST1_GPIO3);
  }
 
  static inline constexpr uint32 GLB_RST1_GPIO4(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST1_GPIO4) &
            +chip::mrcc::Mask::GLB_RST1_GPIO4);
  }
 
  static inline constexpr uint32 GLB_RST1_SET_DATA(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST1_SET_DATA) &
            +chip::mrcc::Mask::GLB_RST1_SET_DATA);
  }
 
  static inline constexpr uint32 GLB_RST1_CLR_DATA(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_RST1_CLR_DATA) &
            +chip::mrcc::Mask::GLB_RST1_CLR_DATA);
  }
 
  static inline constexpr uint32 GLB_CC0_INPUTMUX0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC0_INPUTMUX0) &
            +chip::mrcc::Mask::GLB_CC0_INPUTMUX0);
  }
 
  static inline constexpr uint32 GLB_CC0_I3C0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC0_I3C0) &
            +chip::mrcc::Mask::GLB_CC0_I3C0);
  }
 
  static inline constexpr uint32 GLB_CC0_CTIMER0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC0_CTIMER0) &
            +chip::mrcc::Mask::GLB_CC0_CTIMER0);
  }
 
  static inline constexpr uint32 GLB_CC0_CTIMER1(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC0_CTIMER1) &
            +chip::mrcc::Mask::GLB_CC0_CTIMER1);
  }
 
  static inline constexpr uint32 GLB_CC0_CTIMER2(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC0_CTIMER2) &
            +chip::mrcc::Mask::GLB_CC0_CTIMER2);
  }
 
  static inline constexpr uint32 GLB_CC0_CTIMER3(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC0_CTIMER3) &
            +chip::mrcc::Mask::GLB_CC0_CTIMER3);
  }
 
  static inline constexpr uint32 GLB_CC0_CTIMER4(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC0_CTIMER4) &
            +chip::mrcc::Mask::GLB_CC0_CTIMER4);
  }
 
  static inline constexpr uint32 GLB_CC0_FREQME(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC0_FREQME) &
            +chip::mrcc::Mask::GLB_CC0_FREQME);
  }
 
  static inline constexpr uint32 GLB_CC0_UTICK0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC0_UTICK0) &
            +chip::mrcc::Mask::GLB_CC0_UTICK0);
  }
 
  static inline constexpr uint32 GLB_CC0_WWDT0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC0_WWDT0) &
            +chip::mrcc::Mask::GLB_CC0_WWDT0);
  }
 
  static inline constexpr uint32 GLB_CC0_DMA(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC0_DMA) &
            +chip::mrcc::Mask::GLB_CC0_DMA);
  }
 
  static inline constexpr uint32 GLB_CC0_AOI0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC0_AOI0) &
            +chip::mrcc::Mask::GLB_CC0_AOI0);
  }
 
  static inline constexpr uint32 GLB_CC0_CRC0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC0_CRC0) &
            +chip::mrcc::Mask::GLB_CC0_CRC0);
  }
 
  static inline constexpr uint32 GLB_CC0_EIM0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC0_EIM0) &
            +chip::mrcc::Mask::GLB_CC0_EIM0);
  }
 
  static inline constexpr uint32 GLB_CC0_ERM0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC0_ERM0) &
            +chip::mrcc::Mask::GLB_CC0_ERM0);
  }
 
  static inline constexpr uint32 GLB_CC0_FMC(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC0_FMC) &
            +chip::mrcc::Mask::GLB_CC0_FMC);
  }
 
  static inline constexpr uint32 GLB_CC0_AOI1(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC0_AOI1) &
            +chip::mrcc::Mask::GLB_CC0_AOI1);
  }
 
  static inline constexpr uint32 GLB_CC0_FLEXIO0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC0_FLEXIO0) &
            +chip::mrcc::Mask::GLB_CC0_FLEXIO0);
  }
 
  static inline constexpr uint32 GLB_CC0_LPI2C0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC0_LPI2C0) &
            +chip::mrcc::Mask::GLB_CC0_LPI2C0);
  }
 
  static inline constexpr uint32 GLB_CC0_LPI2C1(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC0_LPI2C1) &
            +chip::mrcc::Mask::GLB_CC0_LPI2C1);
  }
 
  static inline constexpr uint32 GLB_CC0_LPSPI0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC0_LPSPI0) &
            +chip::mrcc::Mask::GLB_CC0_LPSPI0);
  }
 
  static inline constexpr uint32 GLB_CC0_LPSPI1(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC0_LPSPI1) &
            +chip::mrcc::Mask::GLB_CC0_LPSPI1);
  }
 
  static inline constexpr uint32 GLB_CC0_LPUART0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC0_LPUART0) &
            +chip::mrcc::Mask::GLB_CC0_LPUART0);
  }
 
  static inline constexpr uint32 GLB_CC0_LPUART1(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC0_LPUART1) &
            +chip::mrcc::Mask::GLB_CC0_LPUART1);
  }
 
  static inline constexpr uint32 GLB_CC0_LPUART2(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC0_LPUART2) &
            +chip::mrcc::Mask::GLB_CC0_LPUART2);
  }
 
  static inline constexpr uint32 GLB_CC0_LPUART3(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC0_LPUART3) &
            +chip::mrcc::Mask::GLB_CC0_LPUART3);
  }
 
  static inline constexpr uint32 GLB_CC0_LPUART4(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC0_LPUART4) &
            +chip::mrcc::Mask::GLB_CC0_LPUART4);
  }
 
  static inline constexpr uint32 GLB_CC0_USB0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC0_USB0) &
            +chip::mrcc::Mask::GLB_CC0_USB0);
  }
 
  static inline constexpr uint32 GLB_CC0_QDC0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC0_QDC0) &
            +chip::mrcc::Mask::GLB_CC0_QDC0);
  }
 
  static inline constexpr uint32 GLB_CC0_QDC1(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC0_QDC1) &
            +chip::mrcc::Mask::GLB_CC0_QDC1);
  }
 
  static inline constexpr uint32 GLB_CC0_FLEXPWM0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC0_FLEXPWM0) &
            +chip::mrcc::Mask::GLB_CC0_FLEXPWM0);
  }
 
  static inline constexpr uint32 GLB_CC0_FLEXPWM1(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC0_FLEXPWM1) &
            +chip::mrcc::Mask::GLB_CC0_FLEXPWM1);
  }
 
  static inline constexpr uint32 GLB_CC0_SET_DATA(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC0_SET_DATA) &
            +chip::mrcc::Mask::GLB_CC0_SET_DATA);
  }
 
  static inline constexpr uint32 GLB_CC0_CLR_DATA(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC0_CLR_DATA) &
            +chip::mrcc::Mask::GLB_CC0_CLR_DATA);
  }
 
  static inline constexpr uint32 GLB_CC1_OSTIMER0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC1_OSTIMER0) &
            +chip::mrcc::Mask::GLB_CC1_OSTIMER0);
  }
 
  static inline constexpr uint32 GLB_CC1_ADC0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC1_ADC0) &
            +chip::mrcc::Mask::GLB_CC1_ADC0);
  }
 
  static inline constexpr uint32 GLB_CC1_ADC1(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC1_ADC1) &
            +chip::mrcc::Mask::GLB_CC1_ADC1);
  }
 
  static inline constexpr uint32 GLB_CC1_CMP0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC1_CMP0) &
            +chip::mrcc::Mask::GLB_CC1_CMP0);
  }
 
  static inline constexpr uint32 GLB_CC1_CMP1(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC1_CMP1) &
            +chip::mrcc::Mask::GLB_CC1_CMP1);
  }
 
  static inline constexpr uint32 GLB_CC1_DAC0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC1_DAC0) &
            +chip::mrcc::Mask::GLB_CC1_DAC0);
  }
 
  static inline constexpr uint32 GLB_CC1_OPAMP0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC1_OPAMP0) &
            +chip::mrcc::Mask::GLB_CC1_OPAMP0);
  }
 
  static inline constexpr uint32 GLB_CC1_PORT0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC1_PORT0) &
            +chip::mrcc::Mask::GLB_CC1_PORT0);
  }
 
  static inline constexpr uint32 GLB_CC1_PORT1(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC1_PORT1) &
            +chip::mrcc::Mask::GLB_CC1_PORT1);
  }
 
  static inline constexpr uint32 GLB_CC1_PORT2(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC1_PORT2) &
            +chip::mrcc::Mask::GLB_CC1_PORT2);
  }
 
  static inline constexpr uint32 GLB_CC1_PORT3(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC1_PORT3) &
            +chip::mrcc::Mask::GLB_CC1_PORT3);
  }
 
  static inline constexpr uint32 GLB_CC1_PORT4(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC1_PORT4) &
            +chip::mrcc::Mask::GLB_CC1_PORT4);
  }
 
  static inline constexpr uint32 GLB_CC1_FLEXCAN0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC1_FLEXCAN0) &
            +chip::mrcc::Mask::GLB_CC1_FLEXCAN0);
  }
 
  static inline constexpr uint32 GLB_CC1_LPI2C2(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC1_LPI2C2) &
            +chip::mrcc::Mask::GLB_CC1_LPI2C2);
  }
 
  static inline constexpr uint32 GLB_CC1_LPI2C3(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC1_LPI2C3) &
            +chip::mrcc::Mask::GLB_CC1_LPI2C3);
  }
 
  static inline constexpr uint32 GLB_CC1_RAMA(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC1_RAMA) &
            +chip::mrcc::Mask::GLB_CC1_RAMA);
  }
 
  static inline constexpr uint32 GLB_CC1_RAMB(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC1_RAMB) &
            +chip::mrcc::Mask::GLB_CC1_RAMB);
  }
 
  static inline constexpr uint32 GLB_CC1_GPIO0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC1_GPIO0) &
            +chip::mrcc::Mask::GLB_CC1_GPIO0);
  }
 
  static inline constexpr uint32 GLB_CC1_GPIO1(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC1_GPIO1) &
            +chip::mrcc::Mask::GLB_CC1_GPIO1);
  }
 
  static inline constexpr uint32 GLB_CC1_GPIO2(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC1_GPIO2) &
            +chip::mrcc::Mask::GLB_CC1_GPIO2);
  }
 
  static inline constexpr uint32 GLB_CC1_GPIO3(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC1_GPIO3) &
            +chip::mrcc::Mask::GLB_CC1_GPIO3);
  }
 
  static inline constexpr uint32 GLB_CC1_GPIO4(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC1_GPIO4) &
            +chip::mrcc::Mask::GLB_CC1_GPIO4);
  }
 
  static inline constexpr uint32 GLB_CC1_ROMC(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC1_ROMC) &
            +chip::mrcc::Mask::GLB_CC1_ROMC);
  }
 
  static inline constexpr uint32 GLB_CC_SET_DATA(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC_SET_DATA) &
            +chip::mrcc::Mask::GLB_CC_SET_DATA);
  }
 
  static inline constexpr uint32 GLB_CC_CLR_DATA(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_CC_CLR_DATA) &
            +chip::mrcc::Mask::GLB_CC_CLR_DATA);
  }
 
  static inline constexpr uint32 GLB_ACC0_INPUTMUX0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC0_INPUTMUX0) &
            +chip::mrcc::Mask::GLB_ACC0_INPUTMUX0);
  }
 
  static inline constexpr uint32 GLB_ACC0_I3C0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC0_I3C0) &
            +chip::mrcc::Mask::GLB_ACC0_I3C0);
  }
 
  static inline constexpr uint32 GLB_ACC0_CTIMER0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC0_CTIMER0) &
            +chip::mrcc::Mask::GLB_ACC0_CTIMER0);
  }
 
  static inline constexpr uint32 GLB_ACC0_CTIMER1(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC0_CTIMER1) &
            +chip::mrcc::Mask::GLB_ACC0_CTIMER1);
  }
 
  static inline constexpr uint32 GLB_ACC0_CTIMER2(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC0_CTIMER2) &
            +chip::mrcc::Mask::GLB_ACC0_CTIMER2);
  }
 
  static inline constexpr uint32 GLB_ACC0_CTIMER3(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC0_CTIMER3) &
            +chip::mrcc::Mask::GLB_ACC0_CTIMER3);
  }
 
  static inline constexpr uint32 GLB_ACC0_CTIMER4(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC0_CTIMER4) &
            +chip::mrcc::Mask::GLB_ACC0_CTIMER4);
  }
 
  static inline constexpr uint32 GLB_ACC0_FREQME(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC0_FREQME) &
            +chip::mrcc::Mask::GLB_ACC0_FREQME);
  }
 
  static inline constexpr uint32 GLB_ACC0_UTICK0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC0_UTICK0) &
            +chip::mrcc::Mask::GLB_ACC0_UTICK0);
  }
 
  static inline constexpr uint32 GLB_ACC0_WWDT0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC0_WWDT0) &
            +chip::mrcc::Mask::GLB_ACC0_WWDT0);
  }
 
  static inline constexpr uint32 GLB_ACC0_DMA(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC0_DMA) &
            +chip::mrcc::Mask::GLB_ACC0_DMA);
  }
 
  static inline constexpr uint32 GLB_ACC0_AOI0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC0_AOI0) &
            +chip::mrcc::Mask::GLB_ACC0_AOI0);
  }
 
  static inline constexpr uint32 GLB_ACC0_CRC0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC0_CRC0) &
            +chip::mrcc::Mask::GLB_ACC0_CRC0);
  }
 
  static inline constexpr uint32 GLB_ACC0_EIM0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC0_EIM0) &
            +chip::mrcc::Mask::GLB_ACC0_EIM0);
  }
 
  static inline constexpr uint32 GLB_ACC0_ERM0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC0_ERM0) &
            +chip::mrcc::Mask::GLB_ACC0_ERM0);
  }
 
  static inline constexpr uint32 GLB_ACC0_FMC(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC0_FMC) &
            +chip::mrcc::Mask::GLB_ACC0_FMC);
  }
 
  static inline constexpr uint32 GLB_ACC0_AOI1(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC0_AOI1) &
            +chip::mrcc::Mask::GLB_ACC0_AOI1);
  }
 
  static inline constexpr uint32 GLB_ACC0_FLEXIO0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC0_FLEXIO0) &
            +chip::mrcc::Mask::GLB_ACC0_FLEXIO0);
  }
 
  static inline constexpr uint32 GLB_ACC0_LPI2C0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC0_LPI2C0) &
            +chip::mrcc::Mask::GLB_ACC0_LPI2C0);
  }
 
  static inline constexpr uint32 GLB_ACC0_LPI2C1(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC0_LPI2C1) &
            +chip::mrcc::Mask::GLB_ACC0_LPI2C1);
  }
 
  static inline constexpr uint32 GLB_ACC0_LPSPI0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC0_LPSPI0) &
            +chip::mrcc::Mask::GLB_ACC0_LPSPI0);
  }
 
  static inline constexpr uint32 GLB_ACC0_LPSPI1(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC0_LPSPI1) &
            +chip::mrcc::Mask::GLB_ACC0_LPSPI1);
  }
 
  static inline constexpr uint32 GLB_ACC0_LPUART0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC0_LPUART0) &
            +chip::mrcc::Mask::GLB_ACC0_LPUART0);
  }
 
  static inline constexpr uint32 GLB_ACC0_LPUART1(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC0_LPUART1) &
            +chip::mrcc::Mask::GLB_ACC0_LPUART1);
  }
 
  static inline constexpr uint32 GLB_ACC0_LPUART2(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC0_LPUART2) &
            +chip::mrcc::Mask::GLB_ACC0_LPUART2);
  }
 
  static inline constexpr uint32 GLB_ACC0_LPUART3(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC0_LPUART3) &
            +chip::mrcc::Mask::GLB_ACC0_LPUART3);
  }
 
  static inline constexpr uint32 GLB_ACC0_LPUART4(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC0_LPUART4) &
            +chip::mrcc::Mask::GLB_ACC0_LPUART4);
  }
 
  static inline constexpr uint32 GLB_ACC0_USB0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC0_USB0) &
            +chip::mrcc::Mask::GLB_ACC0_USB0);
  }
 
  static inline constexpr uint32 GLB_ACC0_QDC0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC0_QDC0) &
            +chip::mrcc::Mask::GLB_ACC0_QDC0);
  }
 
  static inline constexpr uint32 GLB_ACC0_QDC1(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC0_QDC1) &
            +chip::mrcc::Mask::GLB_ACC0_QDC1);
  }
 
  static inline constexpr uint32 GLB_ACC0_FLEXPWM0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC0_FLEXPWM0) &
            +chip::mrcc::Mask::GLB_ACC0_FLEXPWM0);
  }
 
  static inline constexpr uint32 GLB_ACC0_FLEXPWM1(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC0_FLEXPWM1) &
            +chip::mrcc::Mask::GLB_ACC0_FLEXPWM1);
  }
 
  static inline constexpr uint32 GLB_ACC1_OSTIMER0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC1_OSTIMER0) &
            +chip::mrcc::Mask::GLB_ACC1_OSTIMER0);
  }
 
  static inline constexpr uint32 GLB_ACC1_ADC0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC1_ADC0) &
            +chip::mrcc::Mask::GLB_ACC1_ADC0);
  }
 
  static inline constexpr uint32 GLB_ACC1_ADC1(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC1_ADC1) &
            +chip::mrcc::Mask::GLB_ACC1_ADC1);
  }
 
  static inline constexpr uint32 GLB_ACC1_CMP0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC1_CMP0) &
            +chip::mrcc::Mask::GLB_ACC1_CMP0);
  }
 
  static inline constexpr uint32 GLB_ACC1_CMP1(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC1_CMP1) &
            +chip::mrcc::Mask::GLB_ACC1_CMP1);
  }
 
  static inline constexpr uint32 GLB_ACC1_DAC0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC1_DAC0) &
            +chip::mrcc::Mask::GLB_ACC1_DAC0);
  }
 
  static inline constexpr uint32 GLB_ACC1_OPAMP0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC1_OPAMP0) &
            +chip::mrcc::Mask::GLB_ACC1_OPAMP0);
  }
 
  static inline constexpr uint32 GLB_ACC1_PORT0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC1_PORT0) &
            +chip::mrcc::Mask::GLB_ACC1_PORT0);
  }
 
  static inline constexpr uint32 GLB_ACC1_PORT1(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC1_PORT1) &
            +chip::mrcc::Mask::GLB_ACC1_PORT1);
  }
 
  static inline constexpr uint32 GLB_ACC1_PORT2(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC1_PORT2) &
            +chip::mrcc::Mask::GLB_ACC1_PORT2);
  }
 
  static inline constexpr uint32 GLB_ACC1_PORT3(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC1_PORT3) &
            +chip::mrcc::Mask::GLB_ACC1_PORT3);
  }
 
  static inline constexpr uint32 GLB_ACC1_PORT4(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC1_PORT4) &
            +chip::mrcc::Mask::GLB_ACC1_PORT4);
  }
 
  static inline constexpr uint32 GLB_ACC1_FLEXCAN0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC1_FLEXCAN0) &
            +chip::mrcc::Mask::GLB_ACC1_FLEXCAN0);
  }
 
  static inline constexpr uint32 GLB_ACC1_LPI2C2(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC1_LPI2C2) &
            +chip::mrcc::Mask::GLB_ACC1_LPI2C2);
  }
 
  static inline constexpr uint32 GLB_ACC1_LPI2C3(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC1_LPI2C3) &
            +chip::mrcc::Mask::GLB_ACC1_LPI2C3);
  }
 
  static inline constexpr uint32 GLB_ACC1_RAMA(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC1_RAMA) &
            +chip::mrcc::Mask::GLB_ACC1_RAMA);
  }
 
  static inline constexpr uint32 GLB_ACC1_RAMB(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC1_RAMB) &
            +chip::mrcc::Mask::GLB_ACC1_RAMB);
  }
 
  static inline constexpr uint32 GLB_ACC1_GPIO0(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC1_GPIO0) &
            +chip::mrcc::Mask::GLB_ACC1_GPIO0);
  }
 
  static inline constexpr uint32 GLB_ACC1_GPIO1(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC1_GPIO1) &
            +chip::mrcc::Mask::GLB_ACC1_GPIO1);
  }
 
  static inline constexpr uint32 GLB_ACC1_GPIO2(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC1_GPIO2) &
            +chip::mrcc::Mask::GLB_ACC1_GPIO2);
  }
 
  static inline constexpr uint32 GLB_ACC1_GPIO3(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC1_GPIO3) &
            +chip::mrcc::Mask::GLB_ACC1_GPIO3);
  }
 
  static inline constexpr uint32 GLB_ACC1_GPIO4(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC1_GPIO4) &
            +chip::mrcc::Mask::GLB_ACC1_GPIO4);
  }
 
  static inline constexpr uint32 GLB_ACC1_ROMC(uint32 value) {
    return ((value << +chip::mrcc::Shift::GLB_ACC1_ROMC) &
            +chip::mrcc::Mask::GLB_ACC1_ROMC);
  }
 
  static inline constexpr uint32 I3C0_FCLK_CLKSEL_MUX(uint32 value) {
    return ((value << +chip::mrcc::Shift::I3C0_FCLK_CLKSEL_MUX) &
            +chip::mrcc::Mask::I3C0_FCLK_CLKSEL_MUX);
  }
 
  static inline constexpr uint32 I3C0_FCLK_CLKDIV_DIV(uint32 value) {
    return ((value << +chip::mrcc::Shift::I3C0_FCLK_CLKDIV_DIV) &
            +chip::mrcc::Mask::I3C0_FCLK_CLKDIV_DIV);
  }
 
  static inline constexpr uint32 I3C0_FCLK_CLKDIV_RESET(uint32 value) {
    return ((value << +chip::mrcc::Shift::I3C0_FCLK_CLKDIV_RESET) &
            +chip::mrcc::Mask::I3C0_FCLK_CLKDIV_RESET);
  }
 
  static inline constexpr uint32 I3C0_FCLK_CLKDIV_HALT(uint32 value) {
    return ((value << +chip::mrcc::Shift::I3C0_FCLK_CLKDIV_HALT) &
            +chip::mrcc::Mask::I3C0_FCLK_CLKDIV_HALT);
  }
 
  static inline constexpr uint32 I3C0_FCLK_CLKDIV_UNSTAB(uint32 value) {
    return ((value << +chip::mrcc::Shift::I3C0_FCLK_CLKDIV_UNSTAB) &
            +chip::mrcc::Mask::I3C0_FCLK_CLKDIV_UNSTAB);
  }
 
  static inline constexpr uint32 CTIMER0_CLKSEL_MUX(uint32 value) {
    return ((value << +chip::mrcc::Shift::CTIMER0_CLKSEL_MUX) &
            +chip::mrcc::Mask::CTIMER0_CLKSEL_MUX);
  }
 
  static inline constexpr uint32 CTIMER0_CLKDIV_DIV(uint32 value) {
    return ((value << +chip::mrcc::Shift::CTIMER0_CLKDIV_DIV) &
            +chip::mrcc::Mask::CTIMER0_CLKDIV_DIV);
  }
 
  static inline constexpr uint32 CTIMER0_CLKDIV_RESET(uint32 value) {
    return ((value << +chip::mrcc::Shift::CTIMER0_CLKDIV_RESET) &
            +chip::mrcc::Mask::CTIMER0_CLKDIV_RESET);
  }
 
  static inline constexpr uint32 CTIMER0_CLKDIV_HALT(uint32 value) {
    return ((value << +chip::mrcc::Shift::CTIMER0_CLKDIV_HALT) &
            +chip::mrcc::Mask::CTIMER0_CLKDIV_HALT);
  }
 
  static inline constexpr uint32 CTIMER0_CLKDIV_UNSTAB(uint32 value) {
    return ((value << +chip::mrcc::Shift::CTIMER0_CLKDIV_UNSTAB) &
            +chip::mrcc::Mask::CTIMER0_CLKDIV_UNSTAB);
  }
 
  static inline constexpr uint32 CTIMER1_CLKSEL_MUX(uint32 value) {
    return ((value << +chip::mrcc::Shift::CTIMER1_CLKSEL_MUX) &
            +chip::mrcc::Mask::CTIMER1_CLKSEL_MUX);
  }
 
  static inline constexpr uint32 CTIMER1_CLKDIV_DIV(uint32 value) {
    return ((value << +chip::mrcc::Shift::CTIMER1_CLKDIV_DIV) &
            +chip::mrcc::Mask::CTIMER1_CLKDIV_DIV);
  }
 
  static inline constexpr uint32 CTIMER1_CLKDIV_RESET(uint32 value) {
    return ((value << +chip::mrcc::Shift::CTIMER1_CLKDIV_RESET) &
            +chip::mrcc::Mask::CTIMER1_CLKDIV_RESET);
  }
 
  static inline constexpr uint32 CTIMER1_CLKDIV_HALT(uint32 value) {
    return ((value << +chip::mrcc::Shift::CTIMER1_CLKDIV_HALT) &
            +chip::mrcc::Mask::CTIMER1_CLKDIV_HALT);
  }
 
  static inline constexpr uint32 CTIMER1_CLKDIV_UNSTAB(uint32 value) {
    return ((value << +chip::mrcc::Shift::CTIMER1_CLKDIV_UNSTAB) &
            +chip::mrcc::Mask::CTIMER1_CLKDIV_UNSTAB);
  }
 
  static inline constexpr uint32 CTIMER2_CLKSEL_MUX(uint32 value) {
    return ((value << +chip::mrcc::Shift::CTIMER2_CLKSEL_MUX) &
            +chip::mrcc::Mask::CTIMER2_CLKSEL_MUX);
  }
 
  static inline constexpr uint32 CTIMER2_CLKDIV_DIV(uint32 value) {
    return ((value << +chip::mrcc::Shift::CTIMER2_CLKDIV_DIV) &
            +chip::mrcc::Mask::CTIMER2_CLKDIV_DIV);
  }
 
  static inline constexpr uint32 CTIMER2_CLKDIV_RESET(uint32 value) {
    return ((value << +chip::mrcc::Shift::CTIMER2_CLKDIV_RESET) &
            +chip::mrcc::Mask::CTIMER2_CLKDIV_RESET);
  }
 
  static inline constexpr uint32 CTIMER2_CLKDIV_HALT(uint32 value) {
    return ((value << +chip::mrcc::Shift::CTIMER2_CLKDIV_HALT) &
            +chip::mrcc::Mask::CTIMER2_CLKDIV_HALT);
  }
 
  static inline constexpr uint32 CTIMER2_CLKDIV_UNSTAB(uint32 value) {
    return ((value << +chip::mrcc::Shift::CTIMER2_CLKDIV_UNSTAB) &
            +chip::mrcc::Mask::CTIMER2_CLKDIV_UNSTAB);
  }
 
  static inline constexpr uint32 CTIMER3_CLKSEL_MUX(uint32 value) {
    return ((value << +chip::mrcc::Shift::CTIMER3_CLKSEL_MUX) &
            +chip::mrcc::Mask::CTIMER3_CLKSEL_MUX);
  }
 
  static inline constexpr uint32 CTIMER3_CLKDIV_DIV(uint32 value) {
    return ((value << +chip::mrcc::Shift::CTIMER3_CLKDIV_DIV) &
            +chip::mrcc::Mask::CTIMER3_CLKDIV_DIV);
  }
 
  static inline constexpr uint32 CTIMER3_CLKDIV_RESET(uint32 value) {
    return ((value << +chip::mrcc::Shift::CTIMER3_CLKDIV_RESET) &
            +chip::mrcc::Mask::CTIMER3_CLKDIV_RESET);
  }
 
  static inline constexpr uint32 CTIMER3_CLKDIV_HALT(uint32 value) {
    return ((value << +chip::mrcc::Shift::CTIMER3_CLKDIV_HALT) &
            +chip::mrcc::Mask::CTIMER3_CLKDIV_HALT);
  }
 
  static inline constexpr uint32 CTIMER3_CLKDIV_UNSTAB(uint32 value) {
    return ((value << +chip::mrcc::Shift::CTIMER3_CLKDIV_UNSTAB) &
            +chip::mrcc::Mask::CTIMER3_CLKDIV_UNSTAB);
  }
 
  static inline constexpr uint32 CTIMER4_CLKSEL_MUX(uint32 value) {
    return ((value << +chip::mrcc::Shift::CTIMER4_CLKSEL_MUX) &
            +chip::mrcc::Mask::CTIMER4_CLKSEL_MUX);
  }
 
  static inline constexpr uint32 CTIMER4_CLKDIV_DIV(uint32 value) {
    return ((value << +chip::mrcc::Shift::CTIMER4_CLKDIV_DIV) &
            +chip::mrcc::Mask::CTIMER4_CLKDIV_DIV);
  }
 
  static inline constexpr uint32 CTIMER4_CLKDIV_RESET(uint32 value) {
    return ((value << +chip::mrcc::Shift::CTIMER4_CLKDIV_RESET) &
            +chip::mrcc::Mask::CTIMER4_CLKDIV_RESET);
  }
 
  static inline constexpr uint32 CTIMER4_CLKDIV_HALT(uint32 value) {
    return ((value << +chip::mrcc::Shift::CTIMER4_CLKDIV_HALT) &
            +chip::mrcc::Mask::CTIMER4_CLKDIV_HALT);
  }
 
  static inline constexpr uint32 CTIMER4_CLKDIV_UNSTAB(uint32 value) {
    return ((value << +chip::mrcc::Shift::CTIMER4_CLKDIV_UNSTAB) &
            +chip::mrcc::Mask::CTIMER4_CLKDIV_UNSTAB);
  }
 
  static inline constexpr uint32 WWDT0_CLKDIV_DIV(uint32 value) {
    return ((value << +chip::mrcc::Shift::WWDT0_CLKDIV_DIV) &
            +chip::mrcc::Mask::WWDT0_CLKDIV_DIV);
  }
 
  static inline constexpr uint32 WWDT0_CLKDIV_RESET(uint32 value) {
    return ((value << +chip::mrcc::Shift::WWDT0_CLKDIV_RESET) &
            +chip::mrcc::Mask::WWDT0_CLKDIV_RESET);
  }
 
  static inline constexpr uint32 WWDT0_CLKDIV_HALT(uint32 value) {
    return ((value << +chip::mrcc::Shift::WWDT0_CLKDIV_HALT) &
            +chip::mrcc::Mask::WWDT0_CLKDIV_HALT);
  }
 
  static inline constexpr uint32 WWDT0_CLKDIV_UNSTAB(uint32 value) {
    return ((value << +chip::mrcc::Shift::WWDT0_CLKDIV_UNSTAB) &
            +chip::mrcc::Mask::WWDT0_CLKDIV_UNSTAB);
  }
 
  static inline constexpr uint32 FLEXIO0_CLKSEL_MUX(uint32 value) {
    return ((value << +chip::mrcc::Shift::FLEXIO0_CLKSEL_MUX) &
            +chip::mrcc::Mask::FLEXIO0_CLKSEL_MUX);
  }
 
  static inline constexpr uint32 FLEXIO0_CLKDIV_DIV(uint32 value) {
    return ((value << +chip::mrcc::Shift::FLEXIO0_CLKDIV_DIV) &
            +chip::mrcc::Mask::FLEXIO0_CLKDIV_DIV);
  }
 
  static inline constexpr uint32 FLEXIO0_CLKDIV_RESET(uint32 value) {
    return ((value << +chip::mrcc::Shift::FLEXIO0_CLKDIV_RESET) &
            +chip::mrcc::Mask::FLEXIO0_CLKDIV_RESET);
  }
 
  static inline constexpr uint32 FLEXIO0_CLKDIV_HALT(uint32 value) {
    return ((value << +chip::mrcc::Shift::FLEXIO0_CLKDIV_HALT) &
            +chip::mrcc::Mask::FLEXIO0_CLKDIV_HALT);
  }
 
  static inline constexpr uint32 FLEXIO0_CLKDIV_UNSTAB(uint32 value) {
    return ((value << +chip::mrcc::Shift::FLEXIO0_CLKDIV_UNSTAB) &
            +chip::mrcc::Mask::FLEXIO0_CLKDIV_UNSTAB);
  }
 
  static inline constexpr uint32 LPI2C0_CLKSEL_MUX(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPI2C0_CLKSEL_MUX) &
            +chip::mrcc::Mask::LPI2C0_CLKSEL_MUX);
  }
 
  static inline constexpr uint32 LPI2C0_CLKDIV_DIV(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPI2C0_CLKDIV_DIV) &
            +chip::mrcc::Mask::LPI2C0_CLKDIV_DIV);
  }
 
  static inline constexpr uint32 LPI2C0_CLKDIV_RESET(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPI2C0_CLKDIV_RESET) &
            +chip::mrcc::Mask::LPI2C0_CLKDIV_RESET);
  }
 
  static inline constexpr uint32 LPI2C0_CLKDIV_HALT(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPI2C0_CLKDIV_HALT) &
            +chip::mrcc::Mask::LPI2C0_CLKDIV_HALT);
  }
 
  static inline constexpr uint32 LPI2C0_CLKDIV_UNSTAB(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPI2C0_CLKDIV_UNSTAB) &
            +chip::mrcc::Mask::LPI2C0_CLKDIV_UNSTAB);
  }
 
  static inline constexpr uint32 LPI2C1_CLKSEL_MUX(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPI2C1_CLKSEL_MUX) &
            +chip::mrcc::Mask::LPI2C1_CLKSEL_MUX);
  }
 
  static inline constexpr uint32 LPI2C1_CLKDIV_DIV(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPI2C1_CLKDIV_DIV) &
            +chip::mrcc::Mask::LPI2C1_CLKDIV_DIV);
  }
 
  static inline constexpr uint32 LPI2C1_CLKDIV_RESET(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPI2C1_CLKDIV_RESET) &
            +chip::mrcc::Mask::LPI2C1_CLKDIV_RESET);
  }
 
  static inline constexpr uint32 LPI2C1_CLKDIV_HALT(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPI2C1_CLKDIV_HALT) &
            +chip::mrcc::Mask::LPI2C1_CLKDIV_HALT);
  }
 
  static inline constexpr uint32 LPI2C1_CLKDIV_UNSTAB(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPI2C1_CLKDIV_UNSTAB) &
            +chip::mrcc::Mask::LPI2C1_CLKDIV_UNSTAB);
  }
 
  static inline constexpr uint32 LPSPI0_CLKSEL_MUX(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPSPI0_CLKSEL_MUX) &
            +chip::mrcc::Mask::LPSPI0_CLKSEL_MUX);
  }
 
  static inline constexpr uint32 LPSPI0_CLKDIV_DIV(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPSPI0_CLKDIV_DIV) &
            +chip::mrcc::Mask::LPSPI0_CLKDIV_DIV);
  }
 
  static inline constexpr uint32 LPSPI0_CLKDIV_RESET(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPSPI0_CLKDIV_RESET) &
            +chip::mrcc::Mask::LPSPI0_CLKDIV_RESET);
  }
 
  static inline constexpr uint32 LPSPI0_CLKDIV_HALT(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPSPI0_CLKDIV_HALT) &
            +chip::mrcc::Mask::LPSPI0_CLKDIV_HALT);
  }
 
  static inline constexpr uint32 LPSPI0_CLKDIV_UNSTAB(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPSPI0_CLKDIV_UNSTAB) &
            +chip::mrcc::Mask::LPSPI0_CLKDIV_UNSTAB);
  }
 
  static inline constexpr uint32 LPSPI1_CLKSEL_MUX(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPSPI1_CLKSEL_MUX) &
            +chip::mrcc::Mask::LPSPI1_CLKSEL_MUX);
  }
 
  static inline constexpr uint32 LPSPI1_CLKDIV_DIV(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPSPI1_CLKDIV_DIV) &
            +chip::mrcc::Mask::LPSPI1_CLKDIV_DIV);
  }
 
  static inline constexpr uint32 LPSPI1_CLKDIV_RESET(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPSPI1_CLKDIV_RESET) &
            +chip::mrcc::Mask::LPSPI1_CLKDIV_RESET);
  }
 
  static inline constexpr uint32 LPSPI1_CLKDIV_HALT(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPSPI1_CLKDIV_HALT) &
            +chip::mrcc::Mask::LPSPI1_CLKDIV_HALT);
  }
 
  static inline constexpr uint32 LPSPI1_CLKDIV_UNSTAB(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPSPI1_CLKDIV_UNSTAB) &
            +chip::mrcc::Mask::LPSPI1_CLKDIV_UNSTAB);
  }
 
  static inline constexpr uint32 LPUART0_CLKSEL_MUX(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPUART0_CLKSEL_MUX) &
            +chip::mrcc::Mask::LPUART0_CLKSEL_MUX);
  }
 
  static inline constexpr uint32 LPUART0_CLKDIV_DIV(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPUART0_CLKDIV_DIV) &
            +chip::mrcc::Mask::LPUART0_CLKDIV_DIV);
  }
 
  static inline constexpr uint32 LPUART0_CLKDIV_RESET(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPUART0_CLKDIV_RESET) &
            +chip::mrcc::Mask::LPUART0_CLKDIV_RESET);
  }
 
  static inline constexpr uint32 LPUART0_CLKDIV_HALT(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPUART0_CLKDIV_HALT) &
            +chip::mrcc::Mask::LPUART0_CLKDIV_HALT);
  }
 
  static inline constexpr uint32 LPUART0_CLKDIV_UNSTAB(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPUART0_CLKDIV_UNSTAB) &
            +chip::mrcc::Mask::LPUART0_CLKDIV_UNSTAB);
  }
 
  static inline constexpr uint32 LPUART1_CLKSEL_MUX(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPUART1_CLKSEL_MUX) &
            +chip::mrcc::Mask::LPUART1_CLKSEL_MUX);
  }
 
  static inline constexpr uint32 LPUART1_CLKDIV_DIV(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPUART1_CLKDIV_DIV) &
            +chip::mrcc::Mask::LPUART1_CLKDIV_DIV);
  }
 
  static inline constexpr uint32 LPUART1_CLKDIV_RESET(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPUART1_CLKDIV_RESET) &
            +chip::mrcc::Mask::LPUART1_CLKDIV_RESET);
  }
 
  static inline constexpr uint32 LPUART1_CLKDIV_HALT(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPUART1_CLKDIV_HALT) &
            +chip::mrcc::Mask::LPUART1_CLKDIV_HALT);
  }
 
  static inline constexpr uint32 LPUART1_CLKDIV_UNSTAB(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPUART1_CLKDIV_UNSTAB) &
            +chip::mrcc::Mask::LPUART1_CLKDIV_UNSTAB);
  }
 
  static inline constexpr uint32 LPUART2_CLKSEL_MUX(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPUART2_CLKSEL_MUX) &
            +chip::mrcc::Mask::LPUART2_CLKSEL_MUX);
  }
 
  static inline constexpr uint32 LPUART2_CLKDIV_DIV(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPUART2_CLKDIV_DIV) &
            +chip::mrcc::Mask::LPUART2_CLKDIV_DIV);
  }
 
  static inline constexpr uint32 LPUART2_CLKDIV_RESET(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPUART2_CLKDIV_RESET) &
            +chip::mrcc::Mask::LPUART2_CLKDIV_RESET);
  }
 
  static inline constexpr uint32 LPUART2_CLKDIV_HALT(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPUART2_CLKDIV_HALT) &
            +chip::mrcc::Mask::LPUART2_CLKDIV_HALT);
  }
 
  static inline constexpr uint32 LPUART2_CLKDIV_UNSTAB(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPUART2_CLKDIV_UNSTAB) &
            +chip::mrcc::Mask::LPUART2_CLKDIV_UNSTAB);
  }
 
  static inline constexpr uint32 LPUART3_CLKSEL_MUX(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPUART3_CLKSEL_MUX) &
            +chip::mrcc::Mask::LPUART3_CLKSEL_MUX);
  }
 
  static inline constexpr uint32 LPUART3_CLKDIV_DIV(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPUART3_CLKDIV_DIV) &
            +chip::mrcc::Mask::LPUART3_CLKDIV_DIV);
  }
 
  static inline constexpr uint32 LPUART3_CLKDIV_RESET(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPUART3_CLKDIV_RESET) &
            +chip::mrcc::Mask::LPUART3_CLKDIV_RESET);
  }
 
  static inline constexpr uint32 LPUART3_CLKDIV_HALT(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPUART3_CLKDIV_HALT) &
            +chip::mrcc::Mask::LPUART3_CLKDIV_HALT);
  }
 
  static inline constexpr uint32 LPUART3_CLKDIV_UNSTAB(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPUART3_CLKDIV_UNSTAB) &
            +chip::mrcc::Mask::LPUART3_CLKDIV_UNSTAB);
  }
 
  static inline constexpr uint32 LPUART4_CLKSEL_MUX(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPUART4_CLKSEL_MUX) &
            +chip::mrcc::Mask::LPUART4_CLKSEL_MUX);
  }
 
  static inline constexpr uint32 LPUART4_CLKDIV_DIV(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPUART4_CLKDIV_DIV) &
            +chip::mrcc::Mask::LPUART4_CLKDIV_DIV);
  }
 
  static inline constexpr uint32 LPUART4_CLKDIV_RESET(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPUART4_CLKDIV_RESET) &
            +chip::mrcc::Mask::LPUART4_CLKDIV_RESET);
  }
 
  static inline constexpr uint32 LPUART4_CLKDIV_HALT(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPUART4_CLKDIV_HALT) &
            +chip::mrcc::Mask::LPUART4_CLKDIV_HALT);
  }
 
  static inline constexpr uint32 LPUART4_CLKDIV_UNSTAB(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPUART4_CLKDIV_UNSTAB) &
            +chip::mrcc::Mask::LPUART4_CLKDIV_UNSTAB);
  }
 
  static inline constexpr uint32 USB0_CLKSEL_MUX(uint32 value) {
    return ((value << +chip::mrcc::Shift::USB0_CLKSEL_MUX) &
            +chip::mrcc::Mask::USB0_CLKSEL_MUX);
  }
 
  static inline constexpr uint32 LPTMR0_CLKSEL_MUX(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPTMR0_CLKSEL_MUX) &
            +chip::mrcc::Mask::LPTMR0_CLKSEL_MUX);
  }
 
  static inline constexpr uint32 LPTMR0_CLKDIV_DIV(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPTMR0_CLKDIV_DIV) &
            +chip::mrcc::Mask::LPTMR0_CLKDIV_DIV);
  }
 
  static inline constexpr uint32 LPTMR0_CLKDIV_RESET(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPTMR0_CLKDIV_RESET) &
            +chip::mrcc::Mask::LPTMR0_CLKDIV_RESET);
  }
 
  static inline constexpr uint32 LPTMR0_CLKDIV_HALT(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPTMR0_CLKDIV_HALT) &
            +chip::mrcc::Mask::LPTMR0_CLKDIV_HALT);
  }
 
  static inline constexpr uint32 LPTMR0_CLKDIV_UNSTAB(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPTMR0_CLKDIV_UNSTAB) &
            +chip::mrcc::Mask::LPTMR0_CLKDIV_UNSTAB);
  }
 
  static inline constexpr uint32 OSTIMER0_CLKSEL_MUX(uint32 value) {
    return ((value << +chip::mrcc::Shift::OSTIMER0_CLKSEL_MUX) &
            +chip::mrcc::Mask::OSTIMER0_CLKSEL_MUX);
  }
 
  static inline constexpr uint32 ADC0_CLKSEL_MUX(uint32 value) {
    return ((value << +chip::mrcc::Shift::ADC0_CLKSEL_MUX) &
            +chip::mrcc::Mask::ADC0_CLKSEL_MUX);
  }
 
  static inline constexpr uint32 ADC0_CLKDIV_DIV(uint32 value) {
    return ((value << +chip::mrcc::Shift::ADC0_CLKDIV_DIV) &
            +chip::mrcc::Mask::ADC0_CLKDIV_DIV);
  }
 
  static inline constexpr uint32 ADC0_CLKDIV_RESET(uint32 value) {
    return ((value << +chip::mrcc::Shift::ADC0_CLKDIV_RESET) &
            +chip::mrcc::Mask::ADC0_CLKDIV_RESET);
  }
 
  static inline constexpr uint32 ADC0_CLKDIV_HALT(uint32 value) {
    return ((value << +chip::mrcc::Shift::ADC0_CLKDIV_HALT) &
            +chip::mrcc::Mask::ADC0_CLKDIV_HALT);
  }
 
  static inline constexpr uint32 ADC0_CLKDIV_UNSTAB(uint32 value) {
    return ((value << +chip::mrcc::Shift::ADC0_CLKDIV_UNSTAB) &
            +chip::mrcc::Mask::ADC0_CLKDIV_UNSTAB);
  }
 
  static inline constexpr uint32 ADC1_CLKSEL_MUX(uint32 value) {
    return ((value << +chip::mrcc::Shift::ADC1_CLKSEL_MUX) &
            +chip::mrcc::Mask::ADC1_CLKSEL_MUX);
  }
 
  static inline constexpr uint32 ADC1_CLKDIV_DIV(uint32 value) {
    return ((value << +chip::mrcc::Shift::ADC1_CLKDIV_DIV) &
            +chip::mrcc::Mask::ADC1_CLKDIV_DIV);
  }
 
  static inline constexpr uint32 ADC1_CLKDIV_RESET(uint32 value) {
    return ((value << +chip::mrcc::Shift::ADC1_CLKDIV_RESET) &
            +chip::mrcc::Mask::ADC1_CLKDIV_RESET);
  }
 
  static inline constexpr uint32 ADC1_CLKDIV_HALT(uint32 value) {
    return ((value << +chip::mrcc::Shift::ADC1_CLKDIV_HALT) &
            +chip::mrcc::Mask::ADC1_CLKDIV_HALT);
  }
 
  static inline constexpr uint32 ADC1_CLKDIV_UNSTAB(uint32 value) {
    return ((value << +chip::mrcc::Shift::ADC1_CLKDIV_UNSTAB) &
            +chip::mrcc::Mask::ADC1_CLKDIV_UNSTAB);
  }
 
  static inline constexpr uint32 CMP0_FUNC_CLKDIV_DIV(uint32 value) {
    return ((value << +chip::mrcc::Shift::CMP0_FUNC_CLKDIV_DIV) &
            +chip::mrcc::Mask::CMP0_FUNC_CLKDIV_DIV);
  }
 
  static inline constexpr uint32 CMP0_FUNC_CLKDIV_RESET(uint32 value) {
    return ((value << +chip::mrcc::Shift::CMP0_FUNC_CLKDIV_RESET) &
            +chip::mrcc::Mask::CMP0_FUNC_CLKDIV_RESET);
  }
 
  static inline constexpr uint32 CMP0_FUNC_CLKDIV_HALT(uint32 value) {
    return ((value << +chip::mrcc::Shift::CMP0_FUNC_CLKDIV_HALT) &
            +chip::mrcc::Mask::CMP0_FUNC_CLKDIV_HALT);
  }
 
  static inline constexpr uint32 CMP0_FUNC_CLKDIV_UNSTAB(uint32 value) {
    return ((value << +chip::mrcc::Shift::CMP0_FUNC_CLKDIV_UNSTAB) &
            +chip::mrcc::Mask::CMP0_FUNC_CLKDIV_UNSTAB);
  }
 
  static inline constexpr uint32 CMP0_RR_CLKSEL_MUX(uint32 value) {
    return ((value << +chip::mrcc::Shift::CMP0_RR_CLKSEL_MUX) &
            +chip::mrcc::Mask::CMP0_RR_CLKSEL_MUX);
  }
 
  static inline constexpr uint32 CMP0_RR_CLKDIV_DIV(uint32 value) {
    return ((value << +chip::mrcc::Shift::CMP0_RR_CLKDIV_DIV) &
            +chip::mrcc::Mask::CMP0_RR_CLKDIV_DIV);
  }
 
  static inline constexpr uint32 CMP0_RR_CLKDIV_RESET(uint32 value) {
    return ((value << +chip::mrcc::Shift::CMP0_RR_CLKDIV_RESET) &
            +chip::mrcc::Mask::CMP0_RR_CLKDIV_RESET);
  }
 
  static inline constexpr uint32 CMP0_RR_CLKDIV_HALT(uint32 value) {
    return ((value << +chip::mrcc::Shift::CMP0_RR_CLKDIV_HALT) &
            +chip::mrcc::Mask::CMP0_RR_CLKDIV_HALT);
  }
 
  static inline constexpr uint32 CMP0_RR_CLKDIV_UNSTAB(uint32 value) {
    return ((value << +chip::mrcc::Shift::CMP0_RR_CLKDIV_UNSTAB) &
            +chip::mrcc::Mask::CMP0_RR_CLKDIV_UNSTAB);
  }
 
  static inline constexpr uint32 CMP1_FUNC_CLKDIV_DIV(uint32 value) {
    return ((value << +chip::mrcc::Shift::CMP1_FUNC_CLKDIV_DIV) &
            +chip::mrcc::Mask::CMP1_FUNC_CLKDIV_DIV);
  }
 
  static inline constexpr uint32 CMP1_FUNC_CLKDIV_RESET(uint32 value) {
    return ((value << +chip::mrcc::Shift::CMP1_FUNC_CLKDIV_RESET) &
            +chip::mrcc::Mask::CMP1_FUNC_CLKDIV_RESET);
  }
 
  static inline constexpr uint32 CMP1_FUNC_CLKDIV_HALT(uint32 value) {
    return ((value << +chip::mrcc::Shift::CMP1_FUNC_CLKDIV_HALT) &
            +chip::mrcc::Mask::CMP1_FUNC_CLKDIV_HALT);
  }
 
  static inline constexpr uint32 CMP1_FUNC_CLKDIV_UNSTAB(uint32 value) {
    return ((value << +chip::mrcc::Shift::CMP1_FUNC_CLKDIV_UNSTAB) &
            +chip::mrcc::Mask::CMP1_FUNC_CLKDIV_UNSTAB);
  }
 
  static inline constexpr uint32 CMP1_RR_CLKSEL_MUX(uint32 value) {
    return ((value << +chip::mrcc::Shift::CMP1_RR_CLKSEL_MUX) &
            +chip::mrcc::Mask::CMP1_RR_CLKSEL_MUX);
  }
 
  static inline constexpr uint32 CMP1_RR_CLKDIV_DIV(uint32 value) {
    return ((value << +chip::mrcc::Shift::CMP1_RR_CLKDIV_DIV) &
            +chip::mrcc::Mask::CMP1_RR_CLKDIV_DIV);
  }
 
  static inline constexpr uint32 CMP1_RR_CLKDIV_RESET(uint32 value) {
    return ((value << +chip::mrcc::Shift::CMP1_RR_CLKDIV_RESET) &
            +chip::mrcc::Mask::CMP1_RR_CLKDIV_RESET);
  }
 
  static inline constexpr uint32 CMP1_RR_CLKDIV_HALT(uint32 value) {
    return ((value << +chip::mrcc::Shift::CMP1_RR_CLKDIV_HALT) &
            +chip::mrcc::Mask::CMP1_RR_CLKDIV_HALT);
  }
 
  static inline constexpr uint32 CMP1_RR_CLKDIV_UNSTAB(uint32 value) {
    return ((value << +chip::mrcc::Shift::CMP1_RR_CLKDIV_UNSTAB) &
            +chip::mrcc::Mask::CMP1_RR_CLKDIV_UNSTAB);
  }
 
  static inline constexpr uint32 DAC0_CLKSEL_MUX(uint32 value) {
    return ((value << +chip::mrcc::Shift::DAC0_CLKSEL_MUX) &
            +chip::mrcc::Mask::DAC0_CLKSEL_MUX);
  }
 
  static inline constexpr uint32 DAC0_CLKDIV_DIV(uint32 value) {
    return ((value << +chip::mrcc::Shift::DAC0_CLKDIV_DIV) &
            +chip::mrcc::Mask::DAC0_CLKDIV_DIV);
  }
 
  static inline constexpr uint32 DAC0_CLKDIV_RESET(uint32 value) {
    return ((value << +chip::mrcc::Shift::DAC0_CLKDIV_RESET) &
            +chip::mrcc::Mask::DAC0_CLKDIV_RESET);
  }
 
  static inline constexpr uint32 DAC0_CLKDIV_HALT(uint32 value) {
    return ((value << +chip::mrcc::Shift::DAC0_CLKDIV_HALT) &
            +chip::mrcc::Mask::DAC0_CLKDIV_HALT);
  }
 
  static inline constexpr uint32 DAC0_CLKDIV_UNSTAB(uint32 value) {
    return ((value << +chip::mrcc::Shift::DAC0_CLKDIV_UNSTAB) &
            +chip::mrcc::Mask::DAC0_CLKDIV_UNSTAB);
  }
 
  static inline constexpr uint32 FLEXCAN0_CLKSEL_MUX(uint32 value) {
    return ((value << +chip::mrcc::Shift::FLEXCAN0_CLKSEL_MUX) &
            +chip::mrcc::Mask::FLEXCAN0_CLKSEL_MUX);
  }
 
  static inline constexpr uint32 FLEXCAN0_CLKDIV_DIV(uint32 value) {
    return ((value << +chip::mrcc::Shift::FLEXCAN0_CLKDIV_DIV) &
            +chip::mrcc::Mask::FLEXCAN0_CLKDIV_DIV);
  }
 
  static inline constexpr uint32 FLEXCAN0_CLKDIV_RESET(uint32 value) {
    return ((value << +chip::mrcc::Shift::FLEXCAN0_CLKDIV_RESET) &
            +chip::mrcc::Mask::FLEXCAN0_CLKDIV_RESET);
  }
 
  static inline constexpr uint32 FLEXCAN0_CLKDIV_HALT(uint32 value) {
    return ((value << +chip::mrcc::Shift::FLEXCAN0_CLKDIV_HALT) &
            +chip::mrcc::Mask::FLEXCAN0_CLKDIV_HALT);
  }
 
  static inline constexpr uint32 FLEXCAN0_CLKDIV_UNSTAB(uint32 value) {
    return ((value << +chip::mrcc::Shift::FLEXCAN0_CLKDIV_UNSTAB) &
            +chip::mrcc::Mask::FLEXCAN0_CLKDIV_UNSTAB);
  }
 
  static inline constexpr uint32 LPI2C2_CLKSEL_MUX(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPI2C2_CLKSEL_MUX) &
            +chip::mrcc::Mask::LPI2C2_CLKSEL_MUX);
  }
 
  static inline constexpr uint32 LPI2C2_CLKDIV_DIV(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPI2C2_CLKDIV_DIV) &
            +chip::mrcc::Mask::LPI2C2_CLKDIV_DIV);
  }
 
  static inline constexpr uint32 LPI2C2_CLKDIV_RESET(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPI2C2_CLKDIV_RESET) &
            +chip::mrcc::Mask::LPI2C2_CLKDIV_RESET);
  }
 
  static inline constexpr uint32 LPI2C2_CLKDIV_HALT(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPI2C2_CLKDIV_HALT) &
            +chip::mrcc::Mask::LPI2C2_CLKDIV_HALT);
  }
 
  static inline constexpr uint32 LPI2C2_CLKDIV_UNSTAB(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPI2C2_CLKDIV_UNSTAB) &
            +chip::mrcc::Mask::LPI2C2_CLKDIV_UNSTAB);
  }
 
  static inline constexpr uint32 LPI2C3_CLKSEL_MUX(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPI2C3_CLKSEL_MUX) &
            +chip::mrcc::Mask::LPI2C3_CLKSEL_MUX);
  }
 
  static inline constexpr uint32 LPI2C3_CLKDIV_DIV(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPI2C3_CLKDIV_DIV) &
            +chip::mrcc::Mask::LPI2C3_CLKDIV_DIV);
  }
 
  static inline constexpr uint32 LPI2C3_CLKDIV_RESET(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPI2C3_CLKDIV_RESET) &
            +chip::mrcc::Mask::LPI2C3_CLKDIV_RESET);
  }
 
  static inline constexpr uint32 LPI2C3_CLKDIV_HALT(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPI2C3_CLKDIV_HALT) &
            +chip::mrcc::Mask::LPI2C3_CLKDIV_HALT);
  }
 
  static inline constexpr uint32 LPI2C3_CLKDIV_UNSTAB(uint32 value) {
    return ((value << +chip::mrcc::Shift::LPI2C3_CLKDIV_UNSTAB) &
            +chip::mrcc::Mask::LPI2C3_CLKDIV_UNSTAB);
  }
 
  static inline constexpr uint32 DBG_TRACE_CLKSEL_MUX(uint32 value) {
    return ((value << +chip::mrcc::Shift::DBG_TRACE_CLKSEL_MUX) &
            +chip::mrcc::Mask::DBG_TRACE_CLKSEL_MUX);
  }
 
  static inline constexpr uint32 DBG_TRACE_CLKDIV_DIV(uint32 value) {
    return ((value << +chip::mrcc::Shift::DBG_TRACE_CLKDIV_DIV) &
            +chip::mrcc::Mask::DBG_TRACE_CLKDIV_DIV);
  }
 
  static inline constexpr uint32 DBG_TRACE_CLKDIV_RESET(uint32 value) {
    return ((value << +chip::mrcc::Shift::DBG_TRACE_CLKDIV_RESET) &
            +chip::mrcc::Mask::DBG_TRACE_CLKDIV_RESET);
  }
 
  static inline constexpr uint32 DBG_TRACE_CLKDIV_HALT(uint32 value) {
    return ((value << +chip::mrcc::Shift::DBG_TRACE_CLKDIV_HALT) &
            +chip::mrcc::Mask::DBG_TRACE_CLKDIV_HALT);
  }
 
  static inline constexpr uint32 DBG_TRACE_CLKDIV_UNSTAB(uint32 value) {
    return ((value << +chip::mrcc::Shift::DBG_TRACE_CLKDIV_UNSTAB) &
            +chip::mrcc::Mask::DBG_TRACE_CLKDIV_UNSTAB);
  }
 
  static inline constexpr uint32 CLKOUT_CLKSEL_MUX(uint32 value) {
    return ((value << +chip::mrcc::Shift::CLKOUT_CLKSEL_MUX) &
            +chip::mrcc::Mask::CLKOUT_CLKSEL_MUX);
  }
 
  static inline constexpr uint32 CLKOUT_CLKDIV_DIV(uint32 value) {
    return ((value << +chip::mrcc::Shift::CLKOUT_CLKDIV_DIV) &
            +chip::mrcc::Mask::CLKOUT_CLKDIV_DIV);
  }
 
  static inline constexpr uint32 CLKOUT_CLKDIV_RESET(uint32 value) {
    return ((value << +chip::mrcc::Shift::CLKOUT_CLKDIV_RESET) &
            +chip::mrcc::Mask::CLKOUT_CLKDIV_RESET);
  }
 
  static inline constexpr uint32 CLKOUT_CLKDIV_HALT(uint32 value) {
    return ((value << +chip::mrcc::Shift::CLKOUT_CLKDIV_HALT) &
            +chip::mrcc::Mask::CLKOUT_CLKDIV_HALT);
  }
 
  static inline constexpr uint32 CLKOUT_CLKDIV_UNSTAB(uint32 value) {
    return ((value << +chip::mrcc::Shift::CLKOUT_CLKDIV_UNSTAB) &
            +chip::mrcc::Mask::CLKOUT_CLKDIV_UNSTAB);
  }
 
  static inline constexpr uint32 SYSTICK_CLKSEL_MUX(uint32 value) {
    return ((value << +chip::mrcc::Shift::SYSTICK_CLKSEL_MUX) &
            +chip::mrcc::Mask::SYSTICK_CLKSEL_MUX);
  }
 
  static inline constexpr uint32 SYSTICK_CLKDIV_DIV(uint32 value) {
    return ((value << +chip::mrcc::Shift::SYSTICK_CLKDIV_DIV) &
            +chip::mrcc::Mask::SYSTICK_CLKDIV_DIV);
  }
 
  static inline constexpr uint32 SYSTICK_CLKDIV_RESET(uint32 value) {
    return ((value << +chip::mrcc::Shift::SYSTICK_CLKDIV_RESET) &
            +chip::mrcc::Mask::SYSTICK_CLKDIV_RESET);
  }
 
  static inline constexpr uint32 SYSTICK_CLKDIV_HALT(uint32 value) {
    return ((value << +chip::mrcc::Shift::SYSTICK_CLKDIV_HALT) &
            +chip::mrcc::Mask::SYSTICK_CLKDIV_HALT);
  }
 
  static inline constexpr uint32 SYSTICK_CLKDIV_UNSTAB(uint32 value) {
    return ((value << +chip::mrcc::Shift::SYSTICK_CLKDIV_UNSTAB) &
            +chip::mrcc::Mask::SYSTICK_CLKDIV_UNSTAB);
  }
 
  static inline constexpr uint32 FRO_HF_DIV_CLKDIV_DIV(uint32 value) {
    return ((value << +chip::mrcc::Shift::FRO_HF_DIV_CLKDIV_DIV) &
            +chip::mrcc::Mask::FRO_HF_DIV_CLKDIV_DIV);
  }
 
  static inline constexpr uint32 FRO_HF_DIV_CLKDIV_UNSTAB(uint32 value) {
    return ((value << +chip::mrcc::Shift::FRO_HF_DIV_CLKDIV_UNSTAB) &
            +chip::mrcc::Mask::FRO_HF_DIV_CLKDIV_UNSTAB);
  }
};
 
/* ***************************************************************************************
 * End of file
 */
 
#endif /* CHIP_9C5F8B7F_C4AD_4DC2_977C_8B6A752259BE */