- 產生者:
1.11.0
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mFrame
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#include <Register.h>
公開屬性 | ||
| union { | ||
| __IO uint32 ctrl0 | ||
| CTRL_0[0h] <RW> 更多... | ||
| struct { | ||
| __IO uint32 write_index: 8 | ||
| WRITE_INDEX[0-7] <RW> 更多... | ||
| __I uint32 reserved0: 8 | ||
| RESERVED15[8-15] <RESV> 更多... | ||
| __IO uint32 wr_en_0: 2 | ||
| WR_EN_0[16-17] <RW> 更多... | ||
| __IO uint32 sft_rst: 1 | ||
| SFT_RST[18] <RW> 更多... | ||
| __I uint32 reserved1: 13 | ||
| RESERVED31[19-31] <RESV> 更多... | ||
| } ctrl0_bit | ||
| CTRL_0[0h] <RW> 更多... | ||
| }; | ||
| union { | ||
| __IO uint32 ctrl1 | ||
| CTRL1[0x04] <RW> 更多... | ||
| struct { | ||
| __IO uint32 read_index: 8 | ||
| READ_INDEX[0-7] <RW> 更多... | ||
| __I uint32 reserved0: 8 | ||
| RESERVED15[8-15] <RESV> 更多... | ||
| __IO uint32 wr_en_1: 2 | ||
| WR_EN_1[16-17] <RW> 更多... | ||
| __IO uint32 sfr_lock: 4 | ||
| SFR_LOCK[18-21] <RW> 更多... | ||
| __I uint32 reserved1: 10 | ||
| RESERVED31[22-31] <RESV> 更多... | ||
| } ctrl1_bit | ||
| CTRL1[0x04] <RW> 更多... | ||
| }; | ||
| union { | ||
| __IO uint32 intr_ctrl | ||
| INTR_CTRL[0x08] <RW> 更多... | ||
| struct { | ||
| __IO uint32 int_en: 1 | ||
| INT_EN[0] <RW> 更多... | ||
| __IO uint32 int_clr: 1 | ||
| INT_CLR[1] <RW> 更多... | ||
| __IO uint32 int_set: 1 | ||
| INT_SET[1] <RW> 更多... | ||
| __I uint32 reserved0: 29 | ||
| RESERVED31[2-31] <RESV> 更多... | ||
| } intr_ctrl_bit | ||
| INTR_CTRL[0x08] <RW> 更多... | ||
| }; | ||
| union { | ||
| __I uint32 status | ||
| STATUS[0x0C] <RO> 更多... | ||
| struct { | ||
| __I uint32 int_status: 1 | ||
| INT_STATUS[0] <RO> 更多... | ||
| __I uint32 lock_status: 1 | ||
| LOCK_STATUS[1] <RO> 更多... | ||
| __I uint32 error_status: 3 | ||
| ERROR_STATUS[2-4] <RO> 更多... | ||
| __I uint32 reserved0: 14 | ||
| RESERVED18[5-18] <RESV> 更多... | ||
| __I uint32 fsm_state: 13 | ||
| FSM_STATE[19-31] <RO> 更多... | ||
| } status_bit | ||
| }; | ||
| uint8 | reserved [236] | |
| union { | ||
| __I uint32 version | ||
| VERSION[0xFFC] <RO> 更多... | ||
| struct { | ||
| __I uint32 reserved3: 4 | ||
| Reserved3[0-3] <RESV> 更多... | ||
| __I uint32 reserved7: 4 | ||
| Reserved7[4-7] <RESV> 更多... | ||
| __I uint32 reserved11: 4 | ||
| Reserved3[8-11] <RESV> 更多... | ||
| __I uint32 reserved15: 4 | ||
| Reserved3[12-15] <RESV> 更多... | ||
| __I uint32 milestone: 2 | ||
| MILESTONE[16-17] <RO> 更多... | ||
| __I uint32 fsm_config: 1 | ||
| FSM_CONFIG[18] <RO> 更多... | ||
| __I uint32 index_config: 8 | ||
| INDEX_CONFIG[19-26] <RO> 更多... | ||
| __I uint32 reserved31: 5 | ||
| Reserved31[27-31] <RESV> 更多... | ||
| } version_bit | ||
| }; | ||
Glikey IP provides a mechanism to safely access security-sensitive registers. The write-enable and reset's of these registers are controlled via GLIKEY.
Integrity protection of security-sensitive registers during write and at rest against power glitch attacks.
Integrity protection of security-sensitive registers at rest against privilege escalation.
Error Management.
GLIKEY can be configured in following ways:
GLIKEY controls the write-enables and resets for the SSR's through FSM. Software has to follow strict procedure to enable the write-enables and resets for SSR.
GLIKEY safe guards against attacks by constantly monitoring the state which the FSM is in and the expected SW procedure for the current state. If fault is found, then an interrupt is raised and the FSM goes to secure state. Procedure cannot continue until SW resets the GLIKEY.
Progressing through the FSM is done through writing to SFR registers: CTRL_0[WR_EN_0] and CTRL_1[WR_EN_1].
Any misconfiguration will lead to the FSM entering the WR_DISABLED state that would require a reset, either a soft reset or a hard reset.
The current state of FSM is read out by reading STATUS[FSM_STATE].
The sequence of progressing through the FSM can be seen in STATUS[FSM_STATE]. If the integrity of FSM encodings is compromised, then the error_o will be triggered.
Upon reset (either triggered through hardware or software) FSM will enter the INIT state.
The reset value for the CTRL_0[WRITE_INDEX] is 0x0. If software reset is triggered and CTRL_0[WRITE_INDEX] was previously locked, then the FSM enters into the LOCKED state. To progress, the software needs to update the CTRL_0[WRITE_INDEX] to an index that is currently not locked.
In the INIT state if CTRL_0[WRITE_INDEX] is written that is currently LOCKED, then the FSM will enter the LOCKED state irrespective of CTRL_0[WR_EN_0] and CTRL_1[WR_EN_1].
For example, when in the INIT state, one write to the CTRL_0 happens that updates the CTRL_0[WR_EN_0] = 2'b01 and the CTRL_0[WRITE_INDEX] to a locked index, the FSM will enter the LOCKED state. In this case, software must update the CTRL_0[WR_EN_0] = 2'b10 and the CTRL_0[WRITE_INDEX] to an unlocked value to move back into the INIT state.
For normal operation while in the INIT state and CTRL_0[WRITE_INDEX] is written that is not locked and the CTRL_0[WR_EN_0] is set to 2'b01 or 2'b11 the FSM will either enter STEP1 or SSR_RESET and continue normal operation.
WR_DISABLED state is considered a secured state.
Any misconfiguration of the FSM will lead to this state. Incorrect addressing of the index through CTRL_0[WRITE_INDEX] will also lead to this state.
The FSM monitors the current state of which it is in, if the control signals change and do not match the expected next state encodings the error state is entered.
To leave the WR_DISABLED state, software must perform a soft (Writing one to CTRL_0[SFT_RST]) or hard reset of GLIKEY.
The NON-Secure state is considered a state in which the SSR can be accessed (this is the WR_EN state). This access is allowed via the write-enable outputs of GLIKEY. GLIKEY can enter only the NON-Secure state when the full software procedure has occurred.
Trigger a write-enable out The write-enable output for any given index is only asserted when the FSM is in WR_ENABLED state.
When the FSM moves out of this state then it is de-asserted. The output wr_en_o[*] outputs are not registered and are driven directly by FSM.
Upon entering the WR_DIS state, all bits of the output rst_o will assert to high causing reset of all SSRs
The reset output for any given index is asserted while the FSM is in SSR_RESET state.
When the FSM moves out of this state, then it is de-asserted.
The output rst_o[*] outputs are not registered and are driven directly by the FSM.
After accessing the WR_ENABLE state for any given index, further access to this index can be locked. This causes the GLIKEY to lock access for this. If addressed again, FSM jumps to the LOCKED state and cannot trigger a write-enable or reset for this index.
The locked indexes can only be reset by a hardware reset. The lock registers are protected against integrity errors with replication.
In case the lock and the inverse lock registers are not matching the error_o port is triggered.
Example:
Assuming software is in the WR_EN state with WRITE_INDEX =1, software writes 2'b11 to CTRL_0[WR_EN_0] and enters the LOCKED State. This Index is now considered locked. To enter back into INIT state, software writes 2'b10 to CTRL_0[WR_EN_0] and the WRITE_INDEX is updated to a WRITE_INDEX not previously locked. If software updates WRITE_INDEX that is previously locked, then the software remains in LOCKED STATE.
This means when all the indexes are locked, software remains in the LOCKED state upon entering the last index that is locked.
To read the status of WRITE_INDEX that are locked, software needs to write the corresponding WRITE_INDEX number to the STATUS[INDEX_STATUS] to know the lock status. Software then reads STATUS[LOCK_STATUS] to know the status. 1 = Theindex is locked, 0 = The index is not locked.
Software has the ability to reset the FSM. Writing one to CTRL_0[SFT_RST] brings the FSM into INIT state. This can be triggered while in any state.
Resetting the FSM will cause the current procedure to be restarted. Resetting the FSM will not reset the indexes that have been locked previously. When all WRITE_INDEX's are locked then the FSM will stay in the LOCKED State and cannot be moved from.
Triggering the CTRL_0[SFT_RST] will also reset the following registers to their reset values:
CTRL_0[SFT_RST] takes priority if CTRL_0[WRITE_INDEX] and CTRL_0[WR_EN_0] are written in the same bus access, resulting in these being reset.
GLIKEY can be disabled by writing the value 4'h5 to CTRL_1[SFR_LOCK]. Only hardware reset can re-enable GLIKEY.Once the GLIKEY is disabled, software has no write permissions to the SFR's only read permissions.
GLIKEY cannot perform any accesses to the security sensitive registers.
| __IO uint32 chip::glikey::Register::ctrl0 |
| struct { ... } chip::glikey::Register::ctrl0_bit |
| __IO uint32 chip::glikey::Register::ctrl1 |
| struct { ... } chip::glikey::Register::ctrl1_bit |
| __I uint32 chip::glikey::Register::error_status |
ERROR_STATUS[2-4] <RO>
Status of the Error
Reports the status of error in GLIKEY, where Bit 0 (1 at position 0) indicates that an FSM occurred.
Bit 1 (1 at position 1) indicates that software tried to address write index greater than the available value.
Bit 2 (1 at position 2) indicates that software tried to address read index greater than the available value.
| __I uint32 chip::glikey::Register::fsm_config |
FSM_CONFIG[18] <RO>
| __I uint32 chip::glikey::Register::fsm_state |
FSM_STATE[19-31] <RO>
Status of FSM
| __I uint32 chip::glikey::Register::index_config |
INDEX_CONFIG[19-26] <RO>
Configured number of addressable indexes
| __IO uint32 chip::glikey::Register::int_clr |
INT_CLR[1] <RW>
Interrupt Clear. Writing a 1 to this register creates a single interrupt clear pulse. This register reads as 0
When the interrupt is set, use this field to clear this interrupt by writing 1 to this register.
| __IO uint32 chip::glikey::Register::int_en |
INT_EN[0] <RW>
Interrupt Enable. Writing a 1, Interrupt asserts on Interrupt output port Use this field to control whether to trigger an interrupt.
| __IO uint32 chip::glikey::Register::int_set |
INT_SET[1] <RW>
Interrupt Set. Writing a 1 to this register asserts the interrupt. This register reads as 0
Use this field to set interrupt.
| __I uint32 chip::glikey::Register::int_status |
INT_STATUS[0] <RO>
Interrupt Status.
Reflects the current status of interrupt.
| __IO uint32 chip::glikey::Register::intr_ctrl |
INTR_CTRL[0x08] <RW>
Interrupt Control Register.
| struct { ... } chip::glikey::Register::intr_ctrl_bit |
INTR_CTRL[0x08] <RW>
Interrupt Control Register.
| __I uint32 chip::glikey::Register::lock_status |
LOCK_STATUS[1] <RO>
Provides the current lock status of indexes.
| __I uint32 chip::glikey::Register::milestone |
MILESTONE[16-17] <RO>
Release milestone.
[00b]PREL
[01b]BR
[10b]SI
[11b]GO.
| __IO uint32 chip::glikey::Register::read_index |
READ_INDEX[0-7] <RW>
Index status, Writing an index value to this register will request the block to return the lock status of this index.
Use this field to read the status of a target index.
| __I uint32 chip::glikey::Register::reserved0 |
RESERVED15[8-15] <RESV>
RESERVED18[5-18] <RESV>
RESERVED31[2-31] <RESV>
Reserved for Future Use.
| __I uint32 chip::glikey::Register::reserved1 |
RESERVED31[19-31] <RESV>
RESERVED31[22-31] <RESV>
Reserved for Future Use.
| __I uint32 chip::glikey::Register::reserved11 |
Reserved3[8-11] <RESV>
Reserved.
| __I uint32 chip::glikey::Register::reserved15 |
Reserved3[12-15] <RESV>
Reserved.
| __I uint32 chip::glikey::Register::reserved3 |
Reserved3[0-3] <RESV>
Reserved.
| __I uint32 chip::glikey::Register::reserved31 |
Reserved31[27-31] <RESV>
Reserved for Future Use.
| __I uint32 chip::glikey::Register::reserved7 |
Reserved7[4-7] <RESV>
Reserved.
| __IO uint32 chip::glikey::Register::sfr_lock |
SFR_LOCK[18-21] <RW>
LOCK register for GLIKEY
Note: When IP is locked, Write access to SFR is invalid.
| __IO uint32 chip::glikey::Register::sft_rst |
SFT_RST[18] <RW>
Soft reset for the core reset (SFR configuration will be preseved).This register reads as 0 Use this field to bring the logic into a known state.
| __I uint32 chip::glikey::Register::status |
| __I uint32 chip::glikey::Register::version |
VERSION[0xFFC] <RO>
IP Version register
| __IO uint32 chip::glikey::Register::wr_en_0 |
WR_EN_0[16-17] <RW>
Write Enable 0
Controls the state of FSM. Use these bits with Write Enable 1.
| __IO uint32 chip::glikey::Register::wr_en_1 |
WR_EN_1[16-17] <RW>
Write Enable One.
| __IO uint32 chip::glikey::Register::write_index |
WRITE_INDEX[0-7] <RW>
Write Index
Targets given index for SSR.
1.11.0