spc/Shift.h

 
#ifndef CHIP_794372AA_D3F1_46AE_A274_6FD59B184B6E
#define CHIP_794372AA_D3F1_46AE_A274_6FD59B184B6E
 
/* ***************************************************************************************
 * Include
 */
 
//----------------------------------------------------------------------------------------
#include "mframe.h"
 
//----------------------------------------------------------------------------------------
 
/* ***************************************************************************************
 * Namespace
 */
namespace chip::spc {
  enum struct Shift : unsigned int;
 
  constexpr unsigned int operator+(Shift e) {
    return static_cast<unsigned int>(e);
  }
}  // namespace chip::spc
 
/* ***************************************************************************************
 * Class/Interface/Struct/Enum
 */
enum struct chip::spc::Shift : unsigned int {
 
  VERID_FEATURE = 0U,
 
  VERID_MINOR = 16U,
 
  VERID_MAJOR = 24U,
 
  SC_BUSY = 0U,
 
  SC_SPC_LP_REQ = 1U,
 
  SC_SPC_LP_MODE = 4U,
 
  SC_ISO_CLR = 16U,
 
  SC_SWITCH_STATE = 31U,
 
  LPREQ_CFG_LPREQOE = 0U,
 
  LPREQ_CFG_LPREQPOL = 1U,
 
  LPREQ_CFG_LPREQOV = 2U,
 
  CFG_INTG_PWSWTCH_SLEEP_EN = 0U,
 
  CFG_INTG_PWSWTCH_WKUP_EN = 1U,
 
  CFG_INTG_PWSWTCH_SLEEP_ACTIVE_EN = 2U,
 
  CFG_INTG_PWSWTCH_WKUP_ACTIVE_EN = 3U,
 
  PD_STATUS_PWR_REQ_STATUS = 0U,
 
  PD_STATUS_PD_LP_REQ = 4U,
 
  PD_STATUS_LP_MODE = 8U,
 
  SRAMCTL_VSM = 0U,
 
  SRAMCTL_REQ = 30U,
 
  SRAMCTL_ACK = 31U,
 
  SRAMRETLDO_REFTRIM_REFTRIM = 0U,
 
  SRAMRETLDO_CNTRL_SRAMLDO_ON = 0U,
 
  SRAMRETLDO_CNTRL_SRAM_RET_EN = 8U,
 
  ACTIVE_CFG_CORELDO_VDD_DS = 0U,
 
  ACTIVE_CFG_CORELDO_VDD_LVL = 2U,
 
  ACTIVE_CFG_BGMODE = 20U,
 
  ACTIVE_CFG_VDD_VD_DISABLE = 23U,
 
  ACTIVE_CFG_CORE_LVDE = 24U,
 
  ACTIVE_CFG_SYS_LVDE = 25U,
 
  ACTIVE_CFG_SYS_HVDE = 28U,
 
  ACTIVE_CFG1_SOC_CNTRL = 0U,
 
  LP_CFG_CORELDO_VDD_DS = 0U,
 
  LP_CFG_CORELDO_VDD_LVL = 2U,
 
  LP_CFG_SRAMLDO_DPD_ON = 19U,
 
  LP_CFG_BGMODE = 20U,
 
  LP_CFG_LP_IREFEN = 23U,
 
  LP_CFG_CORE_LVDE = 24U,
 
  LP_CFG_SYS_LVDE = 25U,
 
  LP_CFG_SYS_HVDE = 28U,
 
  LP_CFG1_SOC_CNTRL = 0U,
 
  LPWKUP_DELAY_LPWKUP_DELAY = 0U,
 
  ACTIVE_VDELAY_ACTIVE_VDELAY = 0U,
 
  VD_STAT_COREVDD_LVDF = 0U,
 
  VD_STAT_SYSVDD_LVDF = 1U,
 
  VD_STAT_SYSVDD_HVDF = 5U,
 
  VD_CORE_CFG_LVDRE = 0U,
 
  VD_CORE_CFG_LVDIE = 1U,
 
  VD_CORE_CFG_LOCK = 16U,
 
  VD_SYS_CFG_LVDRE = 0U,
 
  VD_SYS_CFG_LVDIE = 1U,
 
  VD_SYS_CFG_HVDRE = 2U,
 
  VD_SYS_CFG_HVDIE = 3U,
 
  VD_SYS_CFG_LVSEL = 8U,
 
  VD_SYS_CFG_LOCK = 16U,
 
  EVD_CFG_EVDISO = 0U,
 
  EVD_CFG_EVDLPISO = 8U,
 
  EVD_CFG_EVDSTAT = 16U,
 
  EVD_CFG_REG_EVDISO   = 0U,
  EVD_CFG_REG_EVDLPISO = 8U,
  EVD_CFG_REG_EVDSTAT  = 16U
};
 
/* ***************************************************************************************
 * End of file
 */
 
#endif /* CHIP_794372AA_D3F1_46AE_A274_6FD59B184B6E */