spc/Mask.h

 
#ifndef CHIP_3300676D_5504_42B1_B31E_8E1C3015A319
#define CHIP_3300676D_5504_42B1_B31E_8E1C3015A319
 
/* ***************************************************************************************
 * Include
 */
 
//----------------------------------------------------------------------------------------
#include "mframe.h"
 
//----------------------------------------------------------------------------------------
 
/* ***************************************************************************************
 * Namespace
 */
namespace chip::spc {
  enum struct Mask : unsigned int;
 
  constexpr unsigned int operator+(Mask e) {
    return static_cast<unsigned int>(e);
  }
}  // namespace chip::spc
 
/* ***************************************************************************************
 * Class/Interface/Struct/Enum
 */
 
enum struct chip::spc::Mask : unsigned int {
 
  VERID_FEATURE = 0x0000FFFFU,
 
  VERID_MINOR = 0x00FF0000U,
 
  VERID_MAJOR = 0xFF000000U,
 
  SC_BUSY = 0x00000001U,
 
  SC_SPC_LP_REQ = 0x00000002U,
 
  SC_SPC_LP_MODE = 0x000000F0U,
 
  SC_ISO_CLR = 0x00010000U,
 
  SC_SWITCH_STATE = 0x80000000U,
 
  LPREQ_CFG_LPREQOE = 0x00000001U,
 
  LPREQ_CFG_LPREQPOL = 0x00000002U,
 
  LPREQ_CFG_LPREQOV = 0x0000000CU,
 
  CFG_INTG_PWSWTCH_SLEEP_EN = 0x00000001U,
 
  CFG_INTG_PWSWTCH_WKUP_EN = 0x00000002U,
 
  CFG_INTG_PWSWTCH_SLEEP_ACTIVE_EN = 0x00000004U,
 
  CFG_INTG_PWSWTCH_WKUP_ACTIVE_EN = 0x00000008U,
 
  PD_STATUS_PWR_REQ_STATUS = 0x00000001U,
 
  PD_STATUS_PD_LP_REQ = 0x00000010U,
 
  PD_STATUS_LP_MODE = 0x00000F00U,
 
  SRAMCTL_VSM = 0x00000003U,
 
  SRAMCTL_REQ = 0x40000000U,
 
  SRAMCTL_ACK = 0x80000000U,
 
  SRAMRETLDO_REFTRIM_REFTRIM = 0x0000001FU,
 
  SRAMRETLDO_CNTRL_SRAMLDO_ON = 0x00000001U,
 
  SRAMRETLDO_CNTRL_SRAM_RET_EN = 0x00000F00U,
 
  ACTIVE_CFG_CORELDO_VDD_DS = 0x00000001U,
 
  ACTIVE_CFG_CORELDO_VDD_LVL = 0x0000000CU,
 
  ACTIVE_CFG_BGMODE = 0x00300000U,
 
  ACTIVE_CFG_VDD_VD_DISABLE = 0x00800000U,
 
  ACTIVE_CFG_CORE_LVDE = 0x01000000U,
 
  ACTIVE_CFG_SYS_LVDE = 0x02000000U,
 
  ACTIVE_CFG_SYS_HVDE = 0x10000000U,
 
  ACTIVE_CFG1_SOC_CNTRL = 0xFFFFFFFFU,
 
  LP_CFG_CORELDO_VDD_DS = 0x00000001U,
 
  LP_CFG_CORELDO_VDD_LVL = 0x0000000CU,
 
  LP_CFG_SRAMLDO_DPD_ON = 0x00080000U,
 
  LP_CFG_BGMODE = 0x00300000U,
 
  LP_CFG_LP_IREFEN = 0x00800000U,
 
  LP_CFG_CORE_LVDE = 0x01000000U,
 
  LP_CFG_SYS_LVDE = 0x02000000U,
 
  LP_CFG_SYS_HVDE = 0x10000000U,
 
  LP_CFG1_SOC_CNTRL = 0xFFFFFFFFU,
 
  LPWKUP_DELAY_LPWKUP_DELAY = 0x0000FFFFU,
 
  ACTIVE_VDELAY_ACTIVE_VDELAY = 0x0000FFFFU,
 
  VD_STAT_COREVDD_LVDF = 0x00000001U,
 
  VD_STAT_SYSVDD_LVDF = 0x00000002U,
 
  VD_STAT_SYSVDD_HVDF = 0x00000020U,
 
  VD_CORE_CFG_LVDRE = 0x00000001U,
 
  VD_CORE_CFG_LVDIE = 0x00000002U,
 
  VD_CORE_CFG_LOCK = 0x00010000U,
 
  VD_SYS_CFG_LVDRE = 0x00000001U,
 
  VD_SYS_CFG_LVDIE = 0x00000002U,
 
  VD_SYS_CFG_HVDRE = 0x00000004U,
 
  VD_SYS_CFG_HVDIE = 0x00000008U,
 
  VD_SYS_CFG_LVSEL = 0x00000100U,
 
  VD_SYS_CFG_LOCK = 0x00010000U,
 
  EVD_CFG_EVDISO = 0x00000007U,
 
  EVD_CFG_EVDLPISO = 0x00000700U,
 
  EVD_CFG_EVDSTAT = 0x00070000U
};
 
/* ***************************************************************************************
 * End of file
 */
 
#endif /* CHIP_3300676D_5504_42B1_B31E_8E1C3015A319 */