scg/Shift.h

 
#ifndef CHIP_BDCC7239_C3B0_4242_9168_7D89254297C7
#define CHIP_BDCC7239_C3B0_4242_9168_7D89254297C7
 
/* ***************************************************************************************
 * Include
 */
 
//----------------------------------------------------------------------------------------
#include "mframe.h"
 
//----------------------------------------------------------------------------------------
 
/* ***************************************************************************************
 * Namespace
 */
namespace chip::scg {
  enum struct Shift : unsigned int;
 
  constexpr unsigned int operator+(Shift e) {
    return static_cast<unsigned int>(e);
  }
}  // namespace chip::scg
 
/* ***************************************************************************************
 * Class/Interface/Struct/Enum
 */
enum struct chip::scg::Shift : unsigned int {
  VERID_VERSION = 0U,
 
  PARAM_SOSCCLKPRES = 1U,
 
  PARAM_SIRCCLKPRES = 2U,
 
  PARAM_FIRCCLKPRES = 3U,
 
  PARAM_ROSCCLKPRES = 4U,
 
  TRIM_LOCK_TRIM_UNLOCK = 0U,
 
  TRIM_LOCK_IFR_DISABLE = 1U,
 
  TRIM_LOCK_TRIM_LOCK_KEY = 16U,
 
  CSR_SCS = 24U,
 
  RCCR_SCS = 24U,
 
  SOSCCSR_SOSCEN = 0U,
 
  SOSCCSR_SOSCSTEN = 1U,
 
  SOSCCSR_SOSCCM = 16U,
 
  SOSCCSR_SOSCCMRE = 17U,
 
  SOSCCSR_LK = 23U,
 
  SOSCCSR_SOSCVLD = 24U,
 
  SOSCCSR_SOSCSEL = 25U,
 
  SOSCCSR_SOSCERR = 26U,
 
  SOSCCSR_SOSCVLD_IE = 30U,
 
  SOSCCFG_EREFS = 2U,
 
  SOSCCFG_RANGE = 4U,
 
  SIRCCSR_SIRCSTEN = 1U,
 
  SIRCCSR_SIRC_CLK_PERIPH_EN = 5U,
 
  SIRCCSR_SIRCTREN = 8U,
 
  SIRCCSR_SIRCTRUP = 9U,
 
  SIRCCSR_TRIM_LOCK = 10U,
 
  SIRCCSR_COARSE_TRIM_BYPASS = 11U,
 
  SIRCCSR_LK = 23U,
 
  SIRCCSR_SIRCVLD = 24U,
 
  SIRCCSR_SIRCSEL = 25U,
 
  SIRCCSR_SIRCERR = 26U,
 
  SIRCCSR_SIRCERR_IE = 27U,
 
  SIRCTCFG_TRIMSRC = 0U,
 
  SIRCTCFG_TRIMDIV = 16U,
 
  SIRCTRIM_CCOTRIM = 0U,
 
  SIRCTRIM_CLTRIM = 8U,
 
  SIRCTRIM_TCTRIM = 16U,
 
  SIRCTRIM_FVCHTRIM = 24U,
 
  SIRCSTAT_CCOTRIM = 0U,
 
  SIRCSTAT_CLTRIM = 8U,
 
  FIRCCSR_FIRCEN = 0U,
 
  FIRCCSR_FIRCSTEN = 1U,
 
  FIRCCSR_FIRC_SCLK_PERIPH_EN = 4U,
 
  FIRCCSR_FIRC_FCLK_PERIPH_EN = 5U,
 
  FIRCCSR_FIRCTREN = 8U,
 
  FIRCCSR_FIRCTRUP = 9U,
 
  FIRCCSR_TRIM_LOCK = 10U,
 
  FIRCCSR_COARSE_TRIM_BYPASS = 11U,
 
  FIRCCSR_LK = 23U,
 
  FIRCCSR_FIRCVLD = 24U,
 
  FIRCCSR_FIRCSEL = 25U,
 
  FIRCCSR_FIRCERR = 26U,
 
  FIRCCSR_FIRCERR_IE = 27U,
 
  FIRCCSR_FIRCACC_IE = 30U,
 
  FIRCCSR_FIRCACC = 31U,
 
  FIRCCFG_FREQ_SEL = 1U,
 
  FIRCTCFG_TRIMSRC = 0U,
 
  FIRCTCFG_TRIMDIV = 16U,
 
  FIRCTRIM_TRIMFINE = 0U,
 
  FIRCTRIM_TRIMCOAR = 8U,
 
  FIRCTRIM_TRIMTEMP2 = 18U,
 
  FIRCTRIM_TRIMSTART = 24U,
 
  FIRCSTAT_TRIMFINE = 0U,
 
  FIRCSTAT_TRIMCOAR = 8U,
 
  FIRCATC1_IDEALC = 0U,
 
  FIRCATC2_COARMINC = 0U,
 
  FIRCATC2_COARMAXC = 16U,
 
  FIRCATC3_FINEMINC = 0U,
 
  FIRCATC3_FINEMAXC = 16U,
 
  ROSCCSR_LK = 23U,
 
  ROSCCSR_ROSCVLD = 24U,
 
  ROSCCSR_ROSCSEL = 25U,
 
  ROSCCSR_ROSCERR = 26U
};
 
/* ***************************************************************************************
 * End of file
 */
 
#endif /* CHIP_BDCC7239_C3B0_4242_9168_7D89254297C7 */