scg/Mask.h

 
#ifndef CHIP_115BE7EB_5F4D_4553_86C7_3F52C2F9CC43
#define CHIP_115BE7EB_5F4D_4553_86C7_3F52C2F9CC43
 
/* ***************************************************************************************
 * Include
 */
 
//----------------------------------------------------------------------------------------
#include "mframe.h"
 
//----------------------------------------------------------------------------------------
 
/* ***************************************************************************************
 * Namespace
 */
namespace chip::scg {
  enum struct Mask : unsigned int;
 
  constexpr unsigned int operator+(Mask e) {
    return static_cast<unsigned int>(e);
  }
}  // namespace chip::scg
 
/* ***************************************************************************************
 * Class/Interface/Struct/Enum
 */
enum struct chip::scg::Mask : unsigned int {
  VERID_VERSION = 0xFFFFFFFFU,
 
  PARAM_SOSCCLKPRES = 0x00000002U,
 
  PARAM_SIRCCLKPRES = 0x00000004U,
 
  PARAM_FIRCCLKPRES = 0x00000008U,
 
  PARAM_ROSCCLKPRES = 0x00000010U,
 
  TRIM_LOCK_TRIM_UNLOCK = 0x00000001U,
 
  TRIM_LOCK_IFR_DISABLE = 0x00000002U,
 
  TRIM_LOCK_TRIM_LOCK_KEY = 0xFFFF0000U,
 
  CSR_SCS = 0x07000000U,
 
  RCCR_SCS = 0x07000000U,
 
  SOSCCSR_SOSCEN = 0x00000001U,
 
  SOSCCSR_SOSCSTEN = 0x00000002U,
 
  SOSCCSR_SOSCCM = 0x00010000U,
 
  SOSCCSR_SOSCCMRE = 0x00020000U,
 
  SOSCCSR_LK = 0x00800000U,
 
  SOSCCSR_SOSCVLD = 0x01000000U,
 
  SOSCCSR_SOSCSEL = 0x02000000U,
 
  SOSCCSR_SOSCERR = 0x04000000U,
 
  SOSCCSR_SOSCVLD_IE = 0x40000000U,
 
  SOSCCFG_EREFS = 0x00000004U,
 
  SOSCCFG_RANGE = 0x00000030U,
 
  SIRCCSR_SIRCSTEN = 0x00000002U,
 
  SIRCCSR_SIRC_CLK_PERIPH_EN = 0x00000020U,
 
  SIRCCSR_SIRCTREN = 0x00000100U,
 
  SIRCCSR_SIRCTRUP = 0x00000200U,
 
  SIRCCSR_TRIM_LOCK = 0x00000400U,
 
  SIRCCSR_COARSE_TRIM_BYPASS = 0x00000800U,
 
  SIRCCSR_LK = 0x0800000U,
 
  SIRCCSR_SIRCVLD = 0x01000000U,
 
  SIRCCSR_SIRCSEL = 0x02000000U,
 
  SIRCCSR_SIRCERR = 0x04000000U,
 
  SIRCCSR_SIRCERR_IE = 0x08000000U,
 
  SIRCTCFG_TRIMSRC = 0x00000003U,
 
  SIRCTCFG_TRIMDIV = 0x007F0000U,
 
  SIRCTRIM_CCOTRIM = 0x0000003FU,
 
  SIRCTRIM_CLTRIM = 0x00003F00U,
 
  SIRCTRIM_TCTRIM = 0x001F0000U,
 
  SIRCTRIM_FVCHTRIM = 0x1F000000U,
 
  SIRCSTAT_CCOTRIM = 0x00000003FU,
 
  SIRCSTAT_CLTRIM = 0x00003F00U,
 
  FIRCCSR_FIRCEN = 0x00000001U,
 
  FIRCCSR_FIRCSTEN = 0x00000002U,
 
  FIRCCSR_FIRC_SCLK_PERIPH_EN = 0x00000010U,
 
  FIRCCSR_FIRC_FCLK_PERIPH_EN = 0x00000020U,
 
  FIRCCSR_FIRCTREN = 0x00000100U,
 
  FIRCCSR_FIRCTRUP = 0x00000200U,
 
  FIRCCSR_TRIM_LOCK = 0x00000400U,
 
  FIRCCSR_COARSE_TRIM_BYPASS = 0x00000800U,
 
  FIRCCSR_LK = 0x00800000U,
 
  FIRCCSR_FIRCVLD = 0x01000000U,
 
  FIRCCSR_FIRCSEL = 0x02000000U,
 
  FIRCCSR_FIRCERR = 0x04000000U,
 
  FIRCCSR_FIRCERR_IE = 0x08000000U,
 
  FIRCCSR_FIRCACC_IE = 0x40000000U,
 
  FIRCCSR_FIRCACC = 0x80000000U,
 
  FIRCCFG_FREQ_SEL = 0x0000000EU,
 
  FIRCTCFG_TRIMSRC = 0x00000003U,
 
  FIRCTCFG_TRIMDIV = 0x07F00000U,
 
  FIRCTRIM_TRIMFINE = 0x000000FFU,
 
  FIRCTRIM_TRIMCOAR = 0x00003F00U,
 
  FIRCTRIM_TRIMTEMP2 = 0x000C0000U,
 
  FIRCTRIM_TRIMSTART = 0x3F000000U,
 
  FIRCSTAT_TRIMFINE = 0x000000FFU,
 
  FIRCSTAT_TRIMCOAR = 0x00003F00U,
 
  FIRCATC1_IDEALC = 0x0000FFFFU,
 
  FIRCATC2_COARMINC = 0x0000FFFFU,
 
  FIRCATC2_COARMAXC = 0xFFFF0000U,
 
  FIRCATC3_FINEMINC = 0x0000FFFFU,
 
  FIRCATC3_FINEMAXC = 0xFFFF0000U,
 
  ROSCCSR_LK = 0x00800000U,
 
  ROSCCSR_ROSCVLD = 0x01000000U,
 
  ROSCCSR_ROSCSEL = 0x02000000U,
 
  ROSCCSR_ROSCERR = 0x04000000U
};
 
/* ***************************************************************************************
 * End of file
 */
 
#endif /* CHIP_115BE7EB_5F4D_4553_86C7_3F52C2F9CC43 */