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port/Shift.h
1
7#ifndef CHIP_BBD6B536_1670_42A7_8CD2_2C94F33F057D
8#define CHIP_BBD6B536_1670_42A7_8CD2_2C94F33F057D
9
10/* ***************************************************************************************
11 * Include
12 */
13
14//----------------------------------------------------------------------------------------
15#include "mframe.h"
16
17//----------------------------------------------------------------------------------------
18
19/* ***************************************************************************************
20 * Namespace
21 */
22namespace chip::port {
23 enum struct Shift : unsigned int;
24
25 constexpr unsigned int operator+(Shift e) {
26 return static_cast<unsigned int>(e);
27 }
28} // namespace chip::port
29
30/* ***************************************************************************************
31 * Class/Interface/Struct/Enum
32 */
33
38enum struct chip::port::Shift : unsigned int {
45 VERID_FEATURE = 0U,
46
51 VERID_MINOR = 16U,
52
57 VERID_MAJOR = 24U,
58
63 GPCLR_GPWD = 0U,
64
73 GPCLR_GPWE0 = 16U,
74
83 GPCLR_GPWE1 = 17U,
84
93 GPCLR_GPWE2 = 18U,
94
103 GPCLR_GPWE3 = 19U,
104
113 GPCLR_GPWE4 = 20U,
114
123 GPCLR_GPWE5 = 21U,
124
133 GPCLR_GPWE6 = 22U,
134
143 GPCLR_GPWE7 = 23U,
144
153 GPCLR_GPWE8 = 24U,
154
163 GPCLR_GPWE9 = 25U,
164
173 GPCLR_GPWE10 = 26U,
174
183 GPCLR_GPWE11 = 27U,
184
193 GPCLR_GPWE12 = 28U,
194
203 GPCLR_GPWE13 = 29U,
204
213 GPCLR_GPWE14 = 30U,
214
223 GPCLR_GPWE15 = 31U,
224
229 GPCHR_GPWD = 0U,
230
239 GPCHR_GPWE16 = 16U,
240
249 GPCHR_GPWE17 = 17U,
250
259 GPCHR_GPWE18 = 18U,
260
269 GPCHR_GPWE19 = 19U,
270
279 GPCHR_GPWE20 = 20U,
280
289 GPCHR_GPWE21 = 21U,
290
299 GPCHR_GPWE22 = 22U,
300
309 GPCHR_GPWE23 = 23U,
310
319 GPCHR_GPWE24 = 24U,
320
329 GPCHR_GPWE25 = 25U,
330
339 GPCHR_GPWE26 = 26U,
340
349 GPCHR_GPWE27 = 27U,
350
359 GPCHR_GPWE28 = 28U,
360
369 GPCHR_GPWE29 = 29U,
370
379 GPCHR_GPWE30 = 30U,
380
389 GPCHR_GPWE31 = 31U,
390
399 CONFIG_RANGE = 0U,
400
405 CALIB0_NCAL = 0U,
406
411 CALIB0_PCAL = 16U,
412
417 CALIB1_NCAL = 0U,
418
422 CALIB1_PCAL = 16U,
423
432 PCR_PS = 0U,
433
442 PCR_PE = 1U,
443
452 PCR_PV = 2U,
453
462 PCR_SRE = 3U,
463
472 PCR_PFE = 4U,
473
482 PCR_ODE = 5U,
483
492 PCR_DSE = 6U,
493
502 PCR_DSE1 = 7U,
503
536 PCR_MUX = 8U,
537
546 PCR_IBE = 12U,
547
556 PCR_INV = 13U,
557
566 PCR_LK = 15U
567
568};
569
570/* ***************************************************************************************
571 * End of file
572 */
573
574#endif /* CHIP_BBD6B536_1670_42A7_8CD2_2C94F33F057D */
Definition Config.h:36
Shift
PORT_Register_Masks PORT Register Shift.
Definition port/Shift.h:38
@ GPCLR_GPWE13
GPCLR - GPWE13.
@ PCR_IBE
PCR - IBE.
@ GPCLR_GPWE15
GPCLR - GPWE15.
@ GPCLR_GPWE8
GPCLR - GPWE8.
@ PCR_DSE
PCR - DSE.
@ GPCLR_GPWE3
GPCLR - GPWE3.
@ PCR_PFE
PCR - PFE.
@ GPCHR_GPWE25
GPCHR - GPWE25.
@ GPCHR_GPWE23
GPCHR - GPWE23.
@ PCR_PS
PCR - PS.
@ GPCLR_GPWE5
GPCLR - GPWE5.
@ GPCHR_GPWE24
GPCHR - GPWE24.
@ GPCHR_GPWE22
GPCHR - GPWE22.
@ CALIB1_NCAL
CALIB1 - NCAL.
@ GPCLR_GPWE10
GPCLR - GPWE10.
@ GPCHR_GPWE30
GPCHR - GPWE30.
@ GPCHR_GPWD
GPCHR - GPWD.
@ CALIB0_PCAL
CALIB0 - PCAL.
@ GPCHR_GPWE20
GPCHR - GPWE20.
@ PCR_INV
PCR - INV.
@ GPCHR_GPWE31
GPCHR - GPWE31.
@ GPCLR_GPWE2
GPCLR - GPWE2.
@ PCR_ODE
PCR - ODE.
@ GPCLR_GPWE1
GPCLR - GPWE1.
@ GPCLR_GPWE11
GPCLR - GPWE11.
@ GPCLR_GPWE7
GPCLR - GPWE7.
@ PCR_SRE
PCR - SRE.
@ GPCLR_GPWE12
GPCLR - GPWE12.
@ GPCLR_GPWE14
GPCLR - GPWE14.
@ PCR_PV
PCR - PV.
@ PCR_MUX
PCR - MUX.
@ GPCHR_GPWE28
GPCHR - GPWE28.
@ GPCHR_GPWE27
GPCHR - GPWE27.
@ GPCHR_GPWE16
GPCHR - GPWE16.
@ GPCHR_GPWE19
GPCHR - GPWE19.
@ CALIB0_NCAL
CALIB0 - NCAL.
@ GPCLR_GPWD
GPCLR - GPWD.
@ GPCHR_GPWE18
GPCHR - GPWE18.
@ GPCLR_GPWE0
GPCLR - GPWE0.
@ CALIB1_PCAL
CALIB1 - PCAL.
@ GPCHR_GPWE17
GPCHR - GPWE17.
@ GPCLR_GPWE9
GPCLR - GPWE9.
@ PCR_LK
PCR - LK.
@ GPCLR_GPWE4
GPCLR - GPWE4.
@ PCR_DSE1
PCR - DSE1.
@ PCR_PE
PCR - PE.
@ GPCHR_GPWE26
GPCHR - GPWE26.
@ CONFIG_RANGE
CONFIG - RANGE.
@ GPCHR_GPWE29
GPCHR - GPWE29.
@ GPCHR_GPWE21
GPCHR - GPWE21.
@ GPCLR_GPWE6
GPCLR - GPWE6.