port/Mask.h

 
#ifndef CHIP_E0E221F1_26AA_4FC3_B814_47C6226935B0
#define CHIP_E0E221F1_26AA_4FC3_B814_47C6226935B0
 
/* ***************************************************************************************
 * Include
 */
 
//----------------------------------------------------------------------------------------
#include "mframe.h"
 
//----------------------------------------------------------------------------------------
 
/* ***************************************************************************************
 * Namespace
 */
namespace chip::port {
  enum struct Mask : unsigned int;
 
  constexpr unsigned int operator+(Mask e) {
    return static_cast<unsigned int>(e);
  }
}  // namespace chip::port
 
/* ***************************************************************************************
 * Class/Interface/Struct/Enum
 */
 
enum struct chip::port::Mask : unsigned int {
 
  VERID_FEATURE = 0xFFFFU,
 
  VERID_MINOR = 0xFF0000U,
 
  VERID_MAJOR = 0xFF000000U,
 
  GPCLR_GPWD = 0xFFFFU,
 
  GPCLR_GPWE0 = 0x10000U,
 
  GPCLR_GPWE1 = 0x20000U,
 
  GPCLR_GPWE2 = 0x40000U,
 
  GPCLR_GPWE3 = 0x80000U,
 
  GPCLR_GPWE4 = 0x100000U,
 
  GPCLR_GPWE5 = 0x200000U,
 
  GPCLR_GPWE6 = 0x400000U,
 
  GPCLR_GPWE7 = 0x800000U,
 
  GPCLR_GPWE8 = 0x1000000U,
 
  GPCLR_GPWE9 = 0x2000000U,
 
  GPCLR_GPWE10 = 0x4000000U,
 
  GPCLR_GPWE11 = 0x8000000U,
 
  GPCLR_GPWE12 = 0x10000000U,
 
  GPCLR_GPWE13 = 0x20000000U,
 
  GPCLR_GPWE14 = 0x40000000U,
 
  GPCLR_GPWE15 = 0x80000000U,
 
  GPCHR_GPWD = 0xFFFFU,
 
  GPCHR_GPWE16 = 0x10000U,
 
  GPCHR_GPWE17 = 0x20000U,
 
  GPCHR_GPWE18 = 0x40000U,
 
  GPCHR_GPWE19 = 0x80000U,
 
  GPCHR_GPWE20 = 0x100000U,
 
  GPCHR_GPWE21 = 0x200000U,
 
  GPCHR_GPWE22 = 0x400000U,
 
  GPCHR_GPWE23 = 0x800000U,
 
  GPCHR_GPWE24 = 0x1000000U,
 
  GPCHR_GPWE25 = 0x2000000U,
 
  GPCHR_GPWE26 = 0x4000000U,
 
  GPCHR_GPWE27 = 0x8000000U,
 
  GPCHR_GPWE28 = 0x10000000U,
 
  GPCHR_GPWE29 = 0x20000000U,
 
  GPCHR_GPWE30 = 0x40000000U,
 
  GPCHR_GPWE31 = 0x80000000U,
 
  CONFIG_RANGE = 0x1U,
 
  CALIB0_NCAL = 0x3FU,
 
  CALIB0_PCAL = 0x3F0000U,
 
  CALIB1_NCAL = 0x3FU,
 
  CALIB1_PCAL = 0x3F0000U,
 
  PCR_PS = 0x1U,
 
  PCR_PE = 0x2U,
 
  PCR_PV = 0x4U,
 
  PCR_SRE = 0x8U,
 
  PCR_PFE = 0x10U,
 
  PCR_ODE = 0x20U,
 
  PCR_DSE = 0x40U,
 
  PCR_DSE1 = 0x80U,
 
  PCR_MUX = 0xF00U,
  /* Merged from fields with different position or width, of widths (2, 3, 4), largest definition used */
  PCR_IBE = 0x1000U,
 
  PCR_INV = 0x2000U,
 
  PCR_LK = 0x8000U
};
 
/* ***************************************************************************************
 * End of file
 */
 
#endif /* CHIP_E0E221F1_26AA_4FC3_B814_47C6226935B0 */