chip::lpuart 命名空間(Namespace)參考文件

複合項目
class	LPUART
struct	Register

列舉型態
enum struct	Mask : unsigned int {   VERID_FEATURE = 0xFFFFU , VERID_MINOR = 0xFF0000U , VERID_MAJOR = 0xFF000000U , PARAM_TXFIFO = 0xFFU ,   PARAM_RXFIFO = 0xFF00U , GLOBAL_RST = 0x2U , PINCFG_TRGSEL = 0x3U , BAUD_SBR = 0x1FFFU ,   BAUD_SBNS = 0x2000U , BAUD_RXEDGIE = 0x4000U , BAUD_LBKDIE = 0x8000U , BAUD_RESYNCDIS = 0x10000U ,   BAUD_BOTHEDGE = 0x20000U , BAUD_MATCFG = 0xC0000U , BAUD_RIDMAE = 0x100000U , BAUD_RDMAE = 0x200000U ,   BAUD_TDMAE = 0x800000U , BAUD_OSR = 0x1F000000U , BAUD_M10 = 0x20000000U , BAUD_MAEN2 = 0x40000000U ,   BAUD_MAEN1 = 0x80000000U , STAT_LBKFE = 0x1U , STAT_AME = 0x2U , STAT_MA2F = 0x4000U ,   STAT_MA1F = 0x8000U , STAT_PF = 0x10000U , STAT_FE = 0x20000U , STAT_NF = 0x40000U ,   STAT_OR = 0x80000U , STAT_IDLE = 0x100000U , STAT_RDRF = 0x200000U , STAT_TC = 0x400000U ,   STAT_TDRE = 0x800000U , STAT_RAF = 0x1000000U , STAT_LBKDE = 0x2000000U , STAT_BRK13 = 0x4000000U ,   STAT_RWUID = 0x8000000U , STAT_RXINV = 0x10000000U , STAT_MSBF = 0x20000000U , STAT_RXEDGIF = 0x40000000U ,   STAT_LBKDIF = 0x80000000U , CTRL_PT = 0x1U , CTRL_PE = 0x2U , CTRL_ILT = 0x4U ,   CTRL_WAKE = 0x8U , CTRL_M = 0x10U , CTRL_RSRC = 0x20U , CTRL_DOZEEN = 0x40U ,   CTRL_LOOPS = 0x80U , CTRL_IDLECFG = 0x700U , CTRL_M7 = 0x800U , CTRL_MA2IE = 0x4000U ,   CTRL_MA1IE = 0x8000U , CTRL_SBK = 0x10000U , CTRL_RWU = 0x20000U , CTRL_RE = 0x40000U ,   CTRL_TE = 0x80000U , CTRL_ILIE = 0x100000U , CTRL_RIE = 0x200000U , CTRL_TCIE = 0x400000U ,   CTRL_TIE = 0x800000U , CTRL_PEIE = 0x1000000U , CTRL_FEIE = 0x2000000U , CTRL_NEIE = 0x4000000U ,   CTRL_ORIE = 0x8000000U , CTRL_TXINV = 0x10000000U , CTRL_TXDIR = 0x20000000U , CTRL_R9T8 = 0x40000000U ,   CTRL_R8T9 = 0x80000000U , DATA_R0T0 = 0x1U , DATA_R1T1 = 0x2U , DATA_R2T2 = 0x4U ,   DATA_R3T3 = 0x8U , DATA_R4T4 = 0x10U , DATA_R5T5 = 0x20U , DATA_R6T6 = 0x40U ,   DATA_R7T7 = 0x80U , DATA_R8T8 = 0x100U , DATA_R9T9 = 0x200U , DATA_LINBRK = 0x400U ,   DATA_IDLINE = 0x800U , DATA_RXEMPT = 0x1000U , DATA_FRETSC = 0x2000U , DATA_PARITYE = 0x4000U ,   DATA_NOISY = 0x8000U , MATCH_MA1 = 0x3FFU , MATCH_MA2 = 0x3FF0000U , MODIR_TXCTSE = 0x1U ,   MODIR_TXRTSE = 0x2U , MODIR_TXRTSPOL = 0x4U , MODIR_RXRTSE = 0x8U , MODIR_TXCTSC = 0x10U ,   MODIR_TXCTSSRC = 0x20U , MODIR_RTSWATER = 0x300U , MODIR_TNP = 0x30000U , MODIR_IREN = 0x40000U ,   FIFO_RXFIFOSIZE = 0x7U , FIFO_RXFE = 0x8U , FIFO_TXFIFOSIZE = 0x70U , FIFO_TXFE = 0x80U ,   FIFO_RXUFE = 0x100U , FIFO_TXOFE = 0x200U , FIFO_RXIDEN = 0x1C00U , FIFO_RXFLUSH = 0x4000U ,   FIFO_TXFLUSH = 0x8000U , FIFO_RXUF = 0x10000U , FIFO_TXOF = 0x20000U , FIFO_RXEMPT = 0x400000U ,   FIFO_TXEMPT = 0x800000U , WATER_TXWATER = 0x3U , WATER_TXCOUNT = 0x700U , WATER_RXWATER = 0x30000U ,   WATER_RXCOUNT = 0x7000000U , DATARO_DATA = 0xFFFFU }
	LPUART_Register_Masks LPUART Register Masks. 更多...
enum struct	Shift : unsigned int {   VERID_FEATURE = 0U , VERID_MINOR = 16U , VERID_MAJOR = 24U , PARAM_TXFIFO = 0U ,   PARAM_RXFIFO = 8U , GLOBAL_RST = 1U , PINCFG_TRGSEL = 0U , BAUD_SBR = 0U ,   BAUD_SBNS = 13U , BAUD_RXEDGIE = 14U , BAUD_LBKDIE = 15U , BAUD_RESYNCDIS = 16U ,   BAUD_BOTHEDGE = 17U , BAUD_MATCFG = 18U , BAUD_RIDMAE = 20U , BAUD_RDMAE = 21U ,   BAUD_TDMAE = 23U , BAUD_OSR = 24U , BAUD_M10 = 29U , BAUD_MAEN2 = 30U ,   BAUD_MAEN1 = 31U , STAT_LBKFE = 0U , STAT_AME = 1U , STAT_MA2F = 14U ,   STAT_MA1F = 15U , STAT_PF = 16U , STAT_FE = 17U , STAT_NF = 18U ,   STAT_OR = 19U , STAT_IDLE = 20U , STAT_RDRF = 21U , STAT_TC = 22U ,   STAT_TDRE = 23U , STAT_RAF = 24U , STAT_LBKDE = 25U , STAT_BRK13 = 26U ,   STAT_RWUID = 27U , STAT_RXINV = 28U , STAT_MSBF = 29U , STAT_RXEDGIF = 30U ,   STAT_LBKDIF = 31U , CTRL_PT = 0U , CTRL_PE = 1U , CTRL_ILT = 2U ,   CTRL_WAKE = 3U , CTRL_M = 4U , CTRL_RSRC = 5U , CTRL_DOZEEN = 6U ,   CTRL_LOOPS = 7U , CTRL_IDLECFG = 8U , CTRL_M7 = 11U , CTRL_MA2IE = 14U ,   CTRL_MA1IE = 15U , CTRL_SBK = 16U , CTRL_RWU = 17U , CTRL_RE = 18U ,   CTRL_TE = 19U , CTRL_ILIE = 20U , CTRL_RIE = 21U , CTRL_TCIE = 22U ,   CTRL_TIE = 23U , CTRL_PEIE = 24U , CTRL_FEIE = 25U , CTRL_NEIE = 26U ,   CTRL_ORIE = 27U , CTRL_TXINV = 28U , CTRL_TXDIR = 29U , CTRL_R9T8 = 30U ,   CTRL_R8T9 = 31U , DATA_R0T0 = 0U , DATA_R1T1 = 1U , DATA_R2T2 = 2U ,   DATA_R3T3 = 3U , DATA_R4T4 = 4U , DATA_R5T5 = 5U , DATA_R6T6 = 6U ,   DATA_R7T7 = 7U , DATA_R8T8 = 8U , DATA_R9T9 = 9U , DATA_LINBRK = 10U ,   DATA_IDLINE = 11U , DATA_RXEMPT = 12U , DATA_FRETSC = 13U , DATA_PARITYE = 14U ,   DATA_NOISY = 15U , MATCH_MA1 = 0U , MATCH_MA2 = 16U , MODIR_TXCTSE = 0U ,   MODIR_TXRTSE = 1U , MODIR_TXRTSPOL = 2U , MODIR_RXRTSE = 3U , MODIR_TXCTSC = 4U ,   MODIR_TXCTSSRC = 5U , MODIR_RTSWATER = 8U , MODIR_TNP = 16U , MODIR_IREN = 18U ,   FIFO_RXFIFOSIZE = 0U , FIFO_RXFE = 3U , FIFO_TXFIFOSIZE = 4U , FIFO_TXFE = 7U ,   FIFO_RXUFE = 8U , FIFO_TXOFE = 9U , FIFO_RXIDEN = 10U , FIFO_RXFLUSH = 14U ,   FIFO_TXFLUSH = 15U , FIFO_RXUF = 16U , FIFO_TXOF = 17U , FIFO_RXEMPT = 22U ,   FIFO_TXEMPT = 23U , WATER_TXWATER = 0U , WATER_TXCOUNT = 8U , WATER_RXWATER = 16U ,   WATER_RXCOUNT = 24U , DATARO_DATA = 0U }

函式
constexpr unsigned int	operator+ (Mask e)
constexpr unsigned int	operator+ (Shift e)

變數
Register &	LPUART0
Register &	LPUART1
Register &	LPUART2
Register *const	LPUART [3]

詳細描述

Copyright (c) 2020 ZxyKira All rights reserved.

SPDX-License-Identifier: MIT

列舉型態說明文件

Mask

enum struct chip::lpuart::Mask : unsigned int

strong

LPUART_Register_Masks LPUART Register Masks.

列舉值
VERID_FEATURE	VERID - FEATURE. Version ID - Feature Identification Number [0b0000000000000001]Standard feature set [0b0000000000000011]Standard feature set with MODEM and IrDA support
VERID_MINOR	VERID - MINOR. Version ID - Minor Version Number
VERID_MAJOR	VERID - MAJOR. Version ID - Major Version Number
PARAM_TXFIFO	PARAM - TXFIFO. Parameter - Transmit FIFO Size
PARAM_RXFIFO	PARAM - RXFIFO. Parameter - Receive FIFO Size
GLOBAL_RST	GLOBAL - RST. Global - Software Reset [0b0]Not reset [0b1]Reset
PINCFG_TRGSEL	PINCFG - TRGSEL. Pin Configuration - Trigger Select [0b00]Input trigger disabled [0b01]Input trigger used instead of the RXD pin input [0b10]Input trigger used instead of the CTS_B pin input [0b11]Input trigger used to modulate the TXD pin output, which (after TXINV configuration) is internally ANDed with the input trigger
BAUD_SBR	BAUD - SBR. Baud Rate - Baud Rate Modulo Divisor
BAUD_SBNS	BAUD - SBNS. Baud Rate - Stop Bit Number Select [0b0]One stop bit [0b1]Two stop bits
BAUD_RXEDGIE	BAUD - RXEDGIE. Baud Rate - RX Input Active Edge Interrupt Enable [0b0]Disable [0b1]Enable
BAUD_LBKDIE	BAUD - LBKDIE. Baud Rate - LIN Break Detect Interrupt Enable [0b0]Disable [0b1]Enable
BAUD_RESYNCDIS	BAUD - RESYNCDIS. Baud Rate - Resynchronization Disable [0b0]Enable [0b1]Disable
BAUD_BOTHEDGE	BAUD - BOTHEDGE. Baud Rate - Both Edge Sampling [0b0]Rising edge [0b1]Both rising and falling edges
BAUD_MATCFG	BAUD - MATCFG. Baud Rate - Match Configuration [0b00]Address match wake-up [0b01]Idle match wake-up [0b10]Match on and match off [0b11]Enables RWU on data match and match on or off for the transmitter CTS input
BAUD_RIDMAE	BAUD - RIDMAE. Baud Rate - Receiver Idle DMA Enable [0b0]Disable [0b1]Enable
BAUD_RDMAE	BAUD - RDMAE. Baud Rate - Receiver Full DMA Enable [0b0]Disable [0b1]Enable
BAUD_TDMAE	BAUD - TDMAE. Baud Rate - Transmitter DMA Enable [0b0]Disable [0b1]Enable
BAUD_OSR	BAUD - OSR. Baud Rate - Oversampling Ratio [0b00000]Results in an OSR of 16 [0b00001]Reserved [0b00010]Reserved [0b00011]Results in an OSR of 4 (requires BAUD[BOTHEDGE] to be 1) [0b00100]Results in an OSR of 5 (requires BAUD[BOTHEDGE] to be 1) [0b00101]Results in an OSR of 6 (requires BAUD[BOTHEDGE] to be 1) [0b00110]Results in an OSR of 7 (requires BAUD[BOTHEDGE] to be 1) [0b00111]Results in an OSR of 8 [0b01000]Results in an OSR of 9 [0b01001]Results in an OSR of 10 [0b01010]Results in an OSR of 11 [0b01011]Results in an OSR of 12 [0b01100]Results in an OSR of 13 [0b01101]Results in an OSR of 14 [0b01110]Results in an OSR of 15 [0b01111]Results in an OSR of 16 [0b10000]Results in an OSR of 17 [0b10001]Results in an OSR of 18 [0b10010]Results in an OSR of 19 [0b10011]Results in an OSR of 20 [0b10100]Results in an OSR of 21 [0b10101]Results in an OSR of 22 [0b10110]Results in an OSR of 23 [0b10111]Results in an OSR of 24 [0b11000]Results in an OSR of 25 [0b11001]Results in an OSR of 26 [0b11010]Results in an OSR of 27 [0b11011]Results in an OSR of 28 [0b11100]Results in an OSR of 29 [0b11101]Results in an OSR of 30 [0b11110]Results in an OSR of 31 [0b11111]Results in an OSR of 32
BAUD_M10	BAUD - M10. Baud Rate - 10-Bit Mode Select [0b0]Receiver and transmitter use 7-bit to 9-bit data characters [0b1]Receiver and transmitter use 10-bit data characters
BAUD_MAEN2	BAUD - MAEN2. Baud Rate - Match Address Mode Enable 2 [0b0]Disable [0b1]Enable
BAUD_MAEN1	BAUD - MAEN1. Baud Rate - Match Address Mode Enable 1 [0b0]Disable [0b1]Enable
STAT_LBKFE	STAT - LBKFE. Status - LIN Break Flag Enable [0b0]Disable [0b1]Enable
STAT_AME	STAT - AME. Status - Address Mark Enable [0b0]Disable [0b1]Enable
STAT_MA2F	STAT - MA2F. Status - Match 2 Flag [0b0]Not equal to MA2 [0b1]Equal to MA2 [0b0]No effect [0b1]Clear the flag
STAT_MA1F	STAT - MA1F. Status - Match 1 Flag [0b0]Not equal to MA1 [0b1]Equal to MA1 [0b0]No effect [0b1]Clear the flag
STAT_PF	STAT - PF. Status - Parity Error Flag [0b0]No parity error detected [0b1]Parity error detected [0b0]No effect [0b1]Clear the flag
STAT_FE	STAT - FE. Status - Framing Error Flag [0b0]No framing error detected (this does not guarantee that the framing is correct) [0b1]Framing error detected [0b0]No effect [0b1]Clear the flag
STAT_NF	STAT - NF. Status - Noise Flag [0b0]No noise detected [0b1]Noise detected [0b0]No effect [0b1]Clear the flag
STAT_OR	STAT - OR. Status - Receiver Overrun Flag [0b0]No overrun [0b1]Receive overrun (new LPUART data is lost) [0b0]No effect [0b1]Clear the flag
STAT_IDLE	STAT - IDLE. Status - Idle Line Flag [0b0]Idle line detected [0b1]Idle line not detected [0b0]No effect [0b1]Clear the flag
STAT_RDRF	STAT - RDRF. Status - Receive Data Register Full Flag [0b0]Equal to or less than watermark [0b1]Greater than watermark
STAT_TC	STAT - TC. Status - Transmission Complete Flag [0b0]Transmitter active [0b1]Transmitter idle
STAT_TDRE	STAT - TDRE. Status - Transmit Data Register Empty Flag [0b0]Greater than watermark [0b1]Equal to or less than watermark
STAT_RAF	STAT - RAF - Receiver Active Flag. [0b0]Idle, waiting for a start bit [0b1]Receiver active (RXD pin input not idle)
STAT_LBKDE	STAT - LBKDE. Status - LIN Break Detection Enable [0b0]Disable [0b1]Enable
STAT_BRK13	STAT - BRK13. Status - Break Character Generation Length [0b0]9 to 13 bit times [0b1]12 to 15 bit times
STAT_RWUID	STAT - RWUID. Status - Receive Wake Up Idle Detect [0b0]STAT[IDLE] does not become 1 [0b1]STAT[IDLE] becomes 1
STAT_RXINV	STAT - RXINV. Status - Receive Data Inversion [0b0]Inverted [0b1]Not inverted
STAT_MSBF	STAT - MSBF. Status - MSB First [0b0]LSB [0b1]MSB
STAT_RXEDGIF	STAT - RXEDGIF. Status - RXD Pin Active Edge Interrupt Flag [0b0]Not occurred [0b1]Occurred [0b0]No effect [0b1]Clear the flag
STAT_LBKDIF	STAT - LBKDIF. Status - LIN Break Detect Interrupt Flag [0b0]Not detected [0b1]Detected [0b0]No effect [0b1]Clear the flag
CTRL_PT	CTRL - PT. Control - Parity Type [0b0]Even parity [0b1]Odd parity
CTRL_PE	CTRL - PE. Control - Parity Enable [0b0]Disable [0b1]Enable
CTRL_ILT	CTRL - ILT. Control - Idle Line Type Select [0b0]After the start bit [0b1]After the stop bit
CTRL_WAKE	CTRL - WAKE. Control - Receiver Wake-Up Method Select [0b0]Idle [0b1]Mark
CTRL_M	CTRL - M. Control - 9-Bit Or 8-Bit Mode Select [0b0]8-bit [0b1]9-bit
CTRL_RSRC	CTRL - RSRC. Control - Receiver Source Select [0b0]Internal Loopback mode [0b1]Single-wire mode
CTRL_DOZEEN	CTRL - DOZEEN. Control - Doze Mode [0b0]Enable [0b1]Disable
CTRL_LOOPS	CTRL - LOOPS. Control - Loop Mode Select [0b0]Normal operation: RXD and TXD use separate pins [0b1]Loop mode or Single-Wire mode
CTRL_IDLECFG	CTRL - IDLECFG. Control - Idle Configuration [0b000]1 [0b001]2 [0b010]4 [0b011]8 [0b100]16 [0b101]32 [0b110]64 [0b111]128
CTRL_M7	CTRL - M7. Control - 7-Bit Mode Select [0b0]8-bit to 10-bit [0b1]7-bit
CTRL_MA2IE	CTRL - MA2IE. Control - Match 2 (MA2F) Interrupt Enable [0b0]Disable [0b1]Enable
CTRL_MA1IE	CTRL - MA1IE. Control - Match 1 (MA1F) Interrupt Enable [0b0]Disable [0b1]Enable
CTRL_SBK	CTRL - SBK. Control - Send Break [0b0]Normal transmitter operation [0b1]Queue break character(s) to be sent
CTRL_RWU	CTRL - RWU. Control - Receiver Wake-Up Control [0b0]Normal receiver operation [0b1]LPUART receiver in standby, waiting for a wake-up condition
CTRL_RE	CTRL - RE. Control - Receiver Enable [0b0]Disable [0b1]Enable
CTRL_TE	CTRL - TE. Control - Transmitter Enable [0b0]Disable [0b1]Enable
CTRL_ILIE	CTRL - ILIE. Control - Idle Line Interrupt Enable [0b0]Disable [0b1]Enable
CTRL_RIE	CTRL - RIE. Control - Receiver Interrupt Enable [0b0]Disable [0b1]Enable
CTRL_TCIE	CTRL - TCIE. Control - Transmission Complete Interrupt Enable [0b0]Disable [0b1]Enable
CTRL_TIE	CTRL - TIE. Control - Transmit Interrupt Enable [0b0]Disable [0b1]Enable
CTRL_PEIE	CTRL - PEIE. Control - Parity Error Interrupt Enable [0b0]Disable [0b1]Enable
CTRL_FEIE	CTRL - FEIE. Control - Framing Error Interrupt Enable [0b0]Disable [0b1]Enable
CTRL_NEIE	CTRL - NEIE. Control - Noise Error Interrupt Enable [0b0]Disable [0b1]Enable
CTRL_ORIE	CTRL - ORIE. Control - Overrun Interrupt Enable [0b0]Disable [0b1]Enable
CTRL_TXINV	CTRL - TXINV. Control - Transmit Data Inversion [0b0]Not inverted [0b1]Inverted
CTRL_TXDIR	CTRL - TXDIR. Control - TXD Pin Direction in Single-Wire Mode [0b0]Input [0b1]Output
CTRL_R9T8	CTRL - R9T8. Control - Receive Bit 9 Transmit Bit 8
CTRL_R8T9	CTRL - R8T9. Control - Receive Bit 8 Transmit Bit 9
DATA_R0T0	DATA - R0T0. Data - Read receive FIFO bit 0 or write transmit FIFO bit 0
DATA_R1T1	DATA - R1T1. Data - Read receive FIFO bit 1 or write transmit FIFO bit 1
DATA_R2T2	DATA - R2T2. Data - Read receive FIFO bit 2 or write transmit FIFO bit 2
DATA_R3T3	DATA - R3T3. Data - Read receive FIFO bit 3 or write transmit FIFO bit 3
DATA_R4T4	DATA - R4T4. Data - Read receive FIFO bit 4 or write transmit FIFO bit 4
DATA_R5T5	DATA - R5T5. Data - Read receive FIFO bit 5 or write transmit FIFO bit 5
DATA_R6T6	DATA - R6T6. Data - Read receive FIFO bit 6 or write transmit FIFO bit 6
DATA_R7T7	DATA - R7T7. Data - Read receive FIFO bit 7 or write transmit FIFO bit 7
DATA_R8T8	DATA - R8T8. Data - Read receive FIFO bit 8 or write transmit FIFO bit 8
DATA_R9T9	DATA - R9T9. Data - Read receive FIFO bit 9 or write transmit FIFO bit 9
DATA_LINBRK	DATA - LINBRK. Data - LIN Break [0b0]Not detected [0b1]Detected
DATA_IDLINE	DATA - IDLINE. Data - Idle Line [0b0]Not idle [0b1]Idle
DATA_RXEMPT	DATA - RXEMPT. Data - Receive Buffer Empty [0b0]Valid data [0b1]Invalid data and empty
DATA_FRETSC	DATA - FRETSC. Data - Frame Error Transmit Special Character [0b0]Received without a frame error on reads or transmits a normal character on writes [0b1]Received with a frame error on reads or transmits an idle or break character on writes
DATA_PARITYE	DATA - PARITYE. Data - Parity Error [0b0]Received without a parity error [0b1]Received with a parity error
DATA_NOISY	DATA - NOISY. Data - Noisy Data Received [0b0]Received without noise [0b1]Received with noise
MATCH_MA1	MATCH - MA1. Match Address - Match Address 1
MATCH_MA2	MATCH - MA2. Match Address - Match Address 2
MODIR_TXCTSE	MODIR - TXCTSE. MODEM IrDA - Transmitter CTS Enable [0b0]Disable [0b1]Enable
MODIR_TXRTSE	MODIR - TXRTSE. MODEM IrDA - Transmitter RTS Enable [0b0]Disable [0b1]Enable
MODIR_TXRTSPOL	MODIR - TXRTSPOL. MODEM IrDA - Transmitter RTS Polarity [0b0]Active low [0b1]Active high
MODIR_RXRTSE	MODIR - RXRTSE. MODEM IrDA - Receiver RTS Enable [0b0]Disable [0b1]Enable
MODIR_TXCTSC	MODIR - TXCTSC. MODEM IrDA - Transmit CTS Configuration [0b0]Sampled at the start of each character [0b1]Sampled when the transmitter is idle
MODIR_TXCTSSRC	MODIR - TXCTSSRC. MODEM IrDA - Transmit CTS Source [0b0]The CTS_B pin [0b1]An internal connection to the receiver address match result
MODIR_RTSWATER	MODIR - RTSWATER. MODEM IrDA - Receive RTS Configuration
MODIR_TNP	MODIR - TNP. MODEM IrDA - Transmitter Narrow Pulse [0b00]1 / OSR [0b01]2 / OSR [0b10]3 / OSR [0b11]4 / OSR
MODIR_IREN	MODIR - IREN. MODEM IrDA - IR Enable [0b0]Disable [0b1]Enable
FIFO_RXFIFOSIZE	FIFO - RXFIFOSIZE. FIFO - Receive FIFO Buffer Depth [0b000]1 [0b001]4 [0b010]8 [0b011]16 [0b100]32 [0b101]64 [0b110]128 [0b111]256
FIFO_RXFE	FIFO - RXFE. FIFO - Receive FIFO Enable [0b0]Disable [0b1]Enable
FIFO_TXFIFOSIZE	FIFO - TXFIFOSIZE. FIFO - Transmit FIFO Buffer Depth [0b000]1 [0b001]4 [0b010]8 [0b011]16 [0b100]32 [0b101]64 [0b110]128 [0b111]256
FIFO_TXFE	FIFO - TXFE. FIFO - Transmit FIFO Enable [0b0]Disable [0b1]Enable
FIFO_RXUFE	FIFO - RXUFE. FIFO - Receive FIFO Underflow Interrupt Enable [0b0]Disable [0b1]Enable
FIFO_TXOFE	FIFO - TXOFE. FIFO - Transmit FIFO Overflow Interrupt Enable [0b0]Disable [0b1]Enable
FIFO_RXIDEN	FIFO - RXIDEN. FIFO - Receiver Idle Empty Enable [0b000]Disable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle [0b001]Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for one character [0b010]Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for two characters [0b011]Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for four characters [0b100]Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for eight characters [0b101]Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 16 characters [0b110]Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 32 characters [0b111]Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 64 characters
FIFO_RXFLUSH	FIFO - RXFLUSH. FIFO - Receive FIFO Flush [0b0]No effect [0b1]All data flushed out
FIFO_TXFLUSH	FIFO - TXFLUSH. FIFO - Transmit FIFO Flush [0b0]No effect [0b1]All data flushed out
FIFO_RXUF	FIFO - RXUF. FIFO - Receiver FIFO Underflow Flag [0b0]No underflow [0b1]Underflow [0b0]No effect [0b1]Clear the flag
FIFO_TXOF	FIFO - TXOF. FIFO - Transmitter FIFO Overflow Flag [0b0]No overflow [0b1]Overflow [0b0]No effect [0b1]Clear the flag
FIFO_RXEMPT	FIFO - RXEMPT. FIFO - Receive FIFO Or Buffer Empty [0b0]Not empty [0b1]Empty
FIFO_TXEMPT	FIFO - TXEMPT. FIFO - Transmit FIFO Or Buffer Empty [0b0]Not empty [0b1]Empty
WATER_TXWATER	WATER - TXWATER. Watermark - Transmit Watermark
WATER_TXCOUNT	WATER - TXCOUNT. Watermark - Transmit Counter
WATER_RXWATER	WATER - RXWATER. Watermark - Receive Watermark
WATER_RXCOUNT	WATER - RXCOUNT. Watermark - Receive Counter
DATARO_DATA	DATARO - DATA. Data Read-Only - Receive Data

Shift

enum struct chip::lpuart::Shift : unsigned int

strong

列舉值
VERID_FEATURE	VERID - FEATURE. Version ID - Feature Identification Number [0b0000000000000001]Standard feature set [0b0000000000000011]Standard feature set with MODEM and IrDA support
VERID_MINOR	VERID - MINOR. Version ID - Minor Version Number
VERID_MAJOR	VERID - MAJOR. Version ID - Major Version Number
PARAM_TXFIFO	PARAM - TXFIFO. Parameter - Transmit FIFO Size
PARAM_RXFIFO	PARAM - RXFIFO. Parameter - Receive FIFO Size
GLOBAL_RST	GLOBAL - RST. Global - Software Reset [0b0]Not reset [0b1]Reset
PINCFG_TRGSEL	PINCFG - TRGSEL. Pin Configuration - Trigger Select [0b00]Input trigger disabled [0b01]Input trigger used instead of the RXD pin input [0b10]Input trigger used instead of the CTS_B pin input [0b11]Input trigger used to modulate the TXD pin output, which (after TXINV configuration) is internally ANDed with the input trigger
BAUD_SBR	BAUD - SBR. Baud Rate - Baud Rate Modulo Divisor
BAUD_SBNS	BAUD - SBNS. Baud Rate - Stop Bit Number Select [0b0]One stop bit [0b1]Two stop bits
BAUD_RXEDGIE	BAUD - RXEDGIE. Baud Rate - RX Input Active Edge Interrupt Enable [0b0]Disable [0b1]Enable
BAUD_LBKDIE	BAUD - LBKDIE. Baud Rate - LIN Break Detect Interrupt Enable [0b0]Disable [0b1]Enable
BAUD_RESYNCDIS	BAUD - RESYNCDIS. Baud Rate - Resynchronization Disable [0b0]Enable [0b1]Disable
BAUD_BOTHEDGE	BAUD - BOTHEDGE. Baud Rate - Both Edge Sampling [0b0]Rising edge [0b1]Both rising and falling edges
BAUD_MATCFG	BAUD - MATCFG. Baud Rate - Match Configuration [0b00]Address match wake-up [0b01]Idle match wake-up [0b10]Match on and match off [0b11]Enables RWU on data match and match on or off for the transmitter CTS input
BAUD_RIDMAE	BAUD - RIDMAE. Baud Rate - Receiver Idle DMA Enable [0b0]Disable [0b1]Enable
BAUD_RDMAE	BAUD - RDMAE. Baud Rate - Receiver Full DMA Enable [0b0]Disable [0b1]Enable
BAUD_TDMAE	BAUD - TDMAE. Baud Rate - Transmitter DMA Enable [0b0]Disable [0b1]Enable
BAUD_OSR	BAUD - OSR. Baud Rate - Oversampling Ratio [0b00000]Results in an OSR of 16 [0b00001]Reserved [0b00010]Reserved [0b00011]Results in an OSR of 4 (requires BAUD[BOTHEDGE] to be 1) [0b00100]Results in an OSR of 5 (requires BAUD[BOTHEDGE] to be 1) [0b00101]Results in an OSR of 6 (requires BAUD[BOTHEDGE] to be 1) [0b00110]Results in an OSR of 7 (requires BAUD[BOTHEDGE] to be 1) [0b00111]Results in an OSR of 8 [0b01000]Results in an OSR of 9 [0b01001]Results in an OSR of 10 [0b01010]Results in an OSR of 11 [0b01011]Results in an OSR of 12 [0b01100]Results in an OSR of 13 [0b01101]Results in an OSR of 14 [0b01110]Results in an OSR of 15 [0b01111]Results in an OSR of 16 [0b10000]Results in an OSR of 17 [0b10001]Results in an OSR of 18 [0b10010]Results in an OSR of 19 [0b10011]Results in an OSR of 20 [0b10100]Results in an OSR of 21 [0b10101]Results in an OSR of 22 [0b10110]Results in an OSR of 23 [0b10111]Results in an OSR of 24 [0b11000]Results in an OSR of 25 [0b11001]Results in an OSR of 26 [0b11010]Results in an OSR of 27 [0b11011]Results in an OSR of 28 [0b11100]Results in an OSR of 29 [0b11101]Results in an OSR of 30 [0b11110]Results in an OSR of 31 [0b11111]Results in an OSR of 32
BAUD_M10	BAUD - M10. Baud Rate - 10-Bit Mode Select [0b0]Receiver and transmitter use 7-bit to 9-bit data characters [0b1]Receiver and transmitter use 10-bit data characters
BAUD_MAEN2	BAUD - MAEN2. Baud Rate - Match Address Mode Enable 2 [0b0]Disable [0b1]Enable
BAUD_MAEN1	BAUD - MAEN1. Baud Rate - Match Address Mode Enable 1 [0b0]Disable [0b1]Enable
STAT_LBKFE	STAT - LBKFE. Status - LIN Break Flag Enable [0b0]Disable [0b1]Enable
STAT_AME	STAT - AME. Status - Address Mark Enable [0b0]Disable [0b1]Enable
STAT_MA2F	STAT - MA2F. Status - Match 2 Flag [0b0]Not equal to MA2 [0b1]Equal to MA2 [0b0]No effect [0b1]Clear the flag
STAT_MA1F	STAT - MA1F. Status - Match 1 Flag [0b0]Not equal to MA1 [0b1]Equal to MA1 [0b0]No effect [0b1]Clear the flag
STAT_PF	STAT - PF. Status - Parity Error Flag [0b0]No parity error detected [0b1]Parity error detected [0b0]No effect [0b1]Clear the flag
STAT_FE	STAT - FE. Status - Framing Error Flag [0b0]No framing error detected (this does not guarantee that the framing is correct) [0b1]Framing error detected [0b0]No effect [0b1]Clear the flag
STAT_NF	STAT - NF. Status - Noise Flag [0b0]No noise detected [0b1]Noise detected [0b0]No effect [0b1]Clear the flag
STAT_OR	STAT - OR. Status - Receiver Overrun Flag [0b0]No overrun [0b1]Receive overrun (new LPUART data is lost) [0b0]No effect [0b1]Clear the flag
STAT_IDLE	STAT - IDLE. Status - Idle Line Flag [0b0]Idle line detected [0b1]Idle line not detected [0b0]No effect [0b1]Clear the flag
STAT_RDRF	STAT - RDRF. Status - Receive Data Register Full Flag [0b0]Equal to or less than watermark [0b1]Greater than watermark
STAT_TC	STAT - TC. Status - Transmission Complete Flag [0b0]Transmitter active [0b1]Transmitter idle
STAT_TDRE	STAT - TDRE. Status - Transmit Data Register Empty Flag [0b0]Greater than watermark [0b1]Equal to or less than watermark
STAT_RAF	STAT - RAF - Receiver Active Flag. [0b0]Idle, waiting for a start bit [0b1]Receiver active (RXD pin input not idle)
STAT_LBKDE	STAT - LBKDE. Status - LIN Break Detection Enable [0b0]Disable [0b1]Enable
STAT_BRK13	STAT - BRK13. Status - Break Character Generation Length [0b0]9 to 13 bit times [0b1]12 to 15 bit times
STAT_RWUID	STAT - RWUID. Status - Receive Wake Up Idle Detect [0b0]STAT[IDLE] does not become 1 [0b1]STAT[IDLE] becomes 1
STAT_RXINV	STAT - RXINV. Status - Receive Data Inversion [0b0]Inverted [0b1]Not inverted
STAT_MSBF	STAT - MSBF. Status - MSB First [0b0]LSB [0b1]MSB
STAT_RXEDGIF	STAT - RXEDGIF. Status - RXD Pin Active Edge Interrupt Flag [0b0]Not occurred [0b1]Occurred [0b0]No effect [0b1]Clear the flag
STAT_LBKDIF	STAT - LBKDIF. Status - LIN Break Detect Interrupt Flag [0b0]Not detected [0b1]Detected [0b0]No effect [0b1]Clear the flag
CTRL_PT	CTRL - PT. Control - Parity Type [0b0]Even parity [0b1]Odd parity
CTRL_PE	CTRL - PE. Control - Parity Enable [0b0]Disable [0b1]Enable
CTRL_ILT	CTRL - ILT. Control - Idle Line Type Select [0b0]After the start bit [0b1]After the stop bit
CTRL_WAKE	CTRL - WAKE. Control - Receiver Wake-Up Method Select [0b0]Idle [0b1]Mark
CTRL_M	CTRL - M. Control - 9-Bit Or 8-Bit Mode Select [0b0]8-bit [0b1]9-bit
CTRL_RSRC	CTRL - RSRC. Control - Receiver Source Select [0b0]Internal Loopback mode [0b1]Single-wire mode
CTRL_DOZEEN	CTRL - DOZEEN. Control - Doze Mode [0b0]Enable [0b1]Disable
CTRL_LOOPS	CTRL - LOOPS. Control - Loop Mode Select [0b0]Normal operation: RXD and TXD use separate pins [0b1]Loop mode or Single-Wire mode
CTRL_IDLECFG	CTRL - IDLECFG. Control - Idle Configuration [0b000]1 [0b001]2 [0b010]4 [0b011]8 [0b100]16 [0b101]32 [0b110]64 [0b111]128
CTRL_M7	CTRL - M7. Control - 7-Bit Mode Select [0b0]8-bit to 10-bit [0b1]7-bit
CTRL_MA2IE	CTRL - MA2IE. Control - Match 2 (MA2F) Interrupt Enable [0b0]Disable [0b1]Enable
CTRL_MA1IE	CTRL - MA1IE. Control - Match 1 (MA1F) Interrupt Enable [0b0]Disable [0b1]Enable
CTRL_SBK	CTRL - SBK. Control - Send Break [0b0]Normal transmitter operation [0b1]Queue break character(s) to be sent
CTRL_RWU	CTRL - RWU. Control - Receiver Wake-Up Control [0b0]Normal receiver operation [0b1]LPUART receiver in standby, waiting for a wake-up condition
CTRL_RE	CTRL - RE. Control - Receiver Enable [0b0]Disable [0b1]Enable
CTRL_TE	CTRL - TE. Control - Transmitter Enable [0b0]Disable [0b1]Enable
CTRL_ILIE	CTRL - ILIE. Control - Idle Line Interrupt Enable [0b0]Disable [0b1]Enable
CTRL_RIE	CTRL - RIE. Control - Receiver Interrupt Enable [0b0]Disable [0b1]Enable
CTRL_TCIE	CTRL - TCIE. Control - Transmission Complete Interrupt Enable [0b0]Disable [0b1]Enable
CTRL_TIE	CTRL - TIE. Control - Transmit Interrupt Enable [0b0]Disable [0b1]Enable
CTRL_PEIE	CTRL - PEIE. Control - Parity Error Interrupt Enable [0b0]Disable [0b1]Enable
CTRL_FEIE	CTRL - FEIE. Control - Framing Error Interrupt Enable [0b0]Disable [0b1]Enable
CTRL_NEIE	CTRL - NEIE. Control - Noise Error Interrupt Enable [0b0]Disable [0b1]Enable
CTRL_ORIE	CTRL - ORIE. Control - Overrun Interrupt Enable [0b0]Disable [0b1]Enable
CTRL_TXINV	CTRL - TXINV. Control - Transmit Data Inversion [0b0]Not inverted [0b1]Inverted
CTRL_TXDIR	CTRL - TXDIR. Control - TXD Pin Direction in Single-Wire Mode [0b0]Input [0b1]Output
CTRL_R9T8	CTRL - R9T8. Control - Receive Bit 9 Transmit Bit 8
CTRL_R8T9	CTRL - R8T9. Control - Receive Bit 8 Transmit Bit 9
DATA_R0T0	DATA - R0T0. Data - Read receive FIFO bit 0 or write transmit FIFO bit 0
DATA_R1T1	DATA - R1T1. Data - Read receive FIFO bit 1 or write transmit FIFO bit 1
DATA_R2T2	DATA - R2T2. Data - Read receive FIFO bit 2 or write transmit FIFO bit 2
DATA_R3T3	DATA - R3T3. Data - Read receive FIFO bit 3 or write transmit FIFO bit 3
DATA_R4T4	DATA - R4T4. Data - Read receive FIFO bit 4 or write transmit FIFO bit 4
DATA_R5T5	DATA - R5T5. Data - Read receive FIFO bit 5 or write transmit FIFO bit 5
DATA_R6T6	DATA - R6T6. Data - Read receive FIFO bit 6 or write transmit FIFO bit 6
DATA_R7T7	DATA - R7T7. Data - Read receive FIFO bit 7 or write transmit FIFO bit 7
DATA_R8T8	DATA - R8T8. Data - Read receive FIFO bit 8 or write transmit FIFO bit 8
DATA_R9T9	DATA - R9T9. Data - Read receive FIFO bit 9 or write transmit FIFO bit 9
DATA_LINBRK	DATA - LINBRK. Data - LIN Break [0b0]Not detected [0b1]Detected
DATA_IDLINE	DATA - IDLINE. Data - Idle Line [0b0]Not idle [0b1]Idle
DATA_RXEMPT	DATA - RXEMPT. Data - Receive Buffer Empty [0b0]Valid data [0b1]Invalid data and empty
DATA_FRETSC	DATA - FRETSC. Data - Frame Error Transmit Special Character [0b0]Received without a frame error on reads or transmits a normal character on writes [0b1]Received with a frame error on reads or transmits an idle or break character on writes
DATA_PARITYE	DATA - PARITYE. Data - Parity Error [0b0]Received without a parity error [0b1]Received with a parity error
DATA_NOISY	DATA - NOISY. Data - Noisy Data Received [0b0]Received without noise [0b1]Received with noise
MATCH_MA1	MATCH - MA1. Match Address - Match Address 1
MATCH_MA2	MATCH - MA2. Match Address - Match Address 2
MODIR_TXCTSE	MODIR - TXCTSE. MODEM IrDA - Transmitter CTS Enable [0b0]Disable [0b1]Enable
MODIR_TXRTSE	MODIR - TXRTSE. MODEM IrDA - Transmitter RTS Enable [0b0]Disable [0b1]Enable
MODIR_TXRTSPOL	MODIR - TXRTSPOL. MODEM IrDA - Transmitter RTS Polarity [0b0]Active low [0b1]Active high
MODIR_RXRTSE	MODIR - RXRTSE. MODEM IrDA - Receiver RTS Enable [0b0]Disable [0b1]Enable
MODIR_TXCTSC	MODIR - TXCTSC. MODEM IrDA - Transmit CTS Configuration [0b0]Sampled at the start of each character [0b1]Sampled when the transmitter is idle
MODIR_TXCTSSRC	MODIR - TXCTSSRC. MODEM IrDA - Transmit CTS Source [0b0]The CTS_B pin [0b1]An internal connection to the receiver address match result
MODIR_RTSWATER	MODIR - RTSWATER. MODEM IrDA - Receive RTS Configuration
MODIR_TNP	MODIR - TNP. MODEM IrDA - Transmitter Narrow Pulse [0b00]1 / OSR [0b01]2 / OSR [0b10]3 / OSR [0b11]4 / OSR
MODIR_IREN	MODIR - IREN. MODEM IrDA - IR Enable [0b0]Disable [0b1]Enable
FIFO_RXFIFOSIZE	FIFO - RXFIFOSIZE. FIFO - Receive FIFO Buffer Depth [0b000]1 [0b001]4 [0b010]8 [0b011]16 [0b100]32 [0b101]64 [0b110]128 [0b111]256
FIFO_RXFE	FIFO - RXFE. FIFO - Receive FIFO Enable [0b0]Disable [0b1]Enable
FIFO_TXFIFOSIZE	FIFO - TXFIFOSIZE. FIFO - Transmit FIFO Buffer Depth [0b000]1 [0b001]4 [0b010]8 [0b011]16 [0b100]32 [0b101]64 [0b110]128 [0b111]256
FIFO_TXFE	FIFO - TXFE. FIFO - Transmit FIFO Enable [0b0]Disable [0b1]Enable
FIFO_RXUFE	FIFO - RXUFE. FIFO - Receive FIFO Underflow Interrupt Enable [0b0]Disable [0b1]Enable
FIFO_TXOFE	FIFO - TXOFE. FIFO - Transmit FIFO Overflow Interrupt Enable [0b0]Disable [0b1]Enable
FIFO_RXIDEN	FIFO - RXIDEN. FIFO - Receiver Idle Empty Enable [0b000]Disable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle [0b001]Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for one character [0b010]Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for two characters [0b011]Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for four characters [0b100]Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for eight characters [0b101]Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 16 characters [0b110]Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 32 characters [0b111]Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 64 characters
FIFO_RXFLUSH	FIFO - RXFLUSH. FIFO - Receive FIFO Flush [0b0]No effect [0b1]All data flushed out
FIFO_TXFLUSH	FIFO - TXFLUSH. FIFO - Transmit FIFO Flush [0b0]No effect [0b1]All data flushed out
FIFO_RXUF	FIFO - RXUF. FIFO - Receiver FIFO Underflow Flag [0b0]No underflow [0b1]Underflow [0b0]No effect [0b1]Clear the flag
FIFO_TXOF	FIFO - TXOF. FIFO - Transmitter FIFO Overflow Flag [0b0]No overflow [0b1]Overflow [0b0]No effect [0b1]Clear the flag
FIFO_RXEMPT	FIFO - RXEMPT. FIFO - Receive FIFO Or Buffer Empty [0b0]Not empty [0b1]Empty
FIFO_TXEMPT	FIFO - TXEMPT. FIFO - Transmit FIFO Or Buffer Empty [0b0]Not empty [0b1]Empty
WATER_TXWATER	WATER - TXWATER. Watermark - Transmit Watermark
WATER_TXCOUNT	WATER - TXCOUNT. Watermark - Transmit Counter
WATER_RXWATER	WATER - RXWATER. Watermark - Receive Watermark
WATER_RXCOUNT	WATER - RXCOUNT. Watermark - Receive Counter
DATARO_DATA	DATARO - DATA. Data Read-Only - Receive Data