chip::ctimer 命名空間(Namespace)參考文件

複合項目
class	CTIMER
struct	Register
	CTIMER - Register Layout Typedef. 更多...

列舉型態
enum struct	Count : unsigned int { CR = 4U , MR = 4U , MSR = 4U }
enum struct	Mask : unsigned int {   IR_MR0INT = 0x1U , IR_MR1INT = 0x2U , IR_MR2INT = 0x4U , IR_MR3INT = 0x8U ,   IR_CR0INT = 0x10U , IR_CR1INT = 0x20U , IR_CR2INT = 0x40U , IR_CR3INT = 0x80U ,   TCR_CEN = 0x1U , TCR_CRST = 0x2U , TCR_AGCEN = 0x10U , TCR_ATCEN = 0x20U ,   TC_TCVAL = 0xFFFFFFFFU , PR_PRVAL = 0xFFFFFFFFU , PC_PCVAL = 0xFFFFFFFFU , MCR_MR0I = 0x1U ,   MCR_MR0R = 0x2U , MCR_MR0S = 0x4U , MCR_MR1I = 0x8U , MCR_MR1R = 0x10U ,   MCR_MR1S = 0x20U , MCR_MR2I = 0x40U , MCR_MR2R = 0x80U , MCR_MR2S = 0x100U ,   MCR_MR3I = 0x200U , MCR_MR3R = 0x400U , MCR_MR3S = 0x800U , MCR_MR0RL = 0x1000000U ,   MCR_MR1RL = 0x2000000U , MCR_MR2RL = 0x4000000U , MCR_MR3RL = 0x8000000U , MR_MATCH = 0xFFFFFFFFU ,   CCR_CAP0RE = 0x1U , CCR_CAP0FE = 0x2U , CCR_CAP0I = 0x4U , CCR_CAP1RE = 0x8U ,   CCR_CAP1FE = 0x10U , CCR_CAP1I = 0x20U , CCR_CAP2RE = 0x40U , CCR_CAP2FE = 0x80U ,   CCR_CAP2I = 0x100U , CCR_CAP3RE = 0x200U , CCR_CAP3FE = 0x400U , CCR_CAP3I = 0x800U ,   CR_CAP = 0xFFFFFFFFU , EMR_EM0 = 0x1U , EMR_EM1 = 0x2U , EMR_EM2 = 0x4U ,   EMR_EM3 = 0x8U , EMR_EMC0 = 0x30U , EMR_EMC1 = 0xC0U , EMR_EMC2 = 0x300U ,   EMR_EMC3 = 0xC00U , CTCR_CTMODE = 0x3U , CTCR_CINSEL = 0xCU , CTCR_ENCC = 0x10U ,   CTCR_SELCC = 0xE0U , PWMC_PWMEN0 = 0x1U , PWMC_PWMEN1 = 0x2U , PWMC_PWMEN2 = 0x4U ,   PWMC_PWMEN3 = 0x8U , MSR_MATCH_SHADOW = 0xFFFFFFFFU }
enum struct	Shift : unsigned int {   IR_MR0INT = 0U , IR_MR1INT = 1U , IR_MR2INT = 2U , IR_MR3INT = 3U ,   IR_CR0INT = 4U , IR_CR1INT = 5U , IR_CR2INT = 6U , IR_CR3INT = 7U ,   TCR_CEN = 0U , TCR_CRST = 1U , TCR_AGCEN = 4U , TCR_ATCEN = 5U ,   TC_TCVAL = 0U , PR_PRVAL = 0U , PC_PCVAL = 0U , MCR_MR0I = 0U ,   MCR_MR0R = 1U , MCR_MR0S = 2U , MCR_MR1I = 3U , MCR_MR1R = 4U ,   MCR_MR1S = 5U , MCR_MR2I = 6U , MCR_MR2R = 7U , MCR_MR2S = 8U ,   MCR_MR3I = 9U , MCR_MR3R = 10U , MCR_MR3S = 11U , MCR_MR0RL = 24U ,   MCR_MR1RL = 25U , MCR_MR2RL = 26U , MCR_MR3RL = 27U , MR_MATCH = 0U ,   CCR_CAP0RE = 0U , CCR_CAP0FE = 1U , CCR_CAP0I = 2U , CCR_CAP1RE = 3U ,   CCR_CAP1FE = 4U , CCR_CAP1I = 5U , CCR_CAP2RE = 6U , CCR_CAP2FE = 7U ,   CCR_CAP2I = 8U , CCR_CAP3RE = 9U , CCR_CAP3FE = 10U , CCR_CAP3I = 11U ,   CR_CAP = 0U , EMR_EM0 = 0U , EMR_EM1 = 1U , EMR_EM2 = 2U ,   EMR_EM3 = 3U , EMR_EMC0 = 4U , EMR_EMC1 = 6U , EMR_EMC2 = 8U ,   EMR_EMC3 = 10U , CTCR_CTMODE = 0U , CTCR_CINSEL = 2U , CTCR_ENCC = 4U ,   CTCR_SELCC = 5U , PWMC_PWMEN0 = 0U , PWMC_PWMEN1 = 1U , PWMC_PWMEN2 = 2U ,   PWMC_PWMEN3 = 3U , MSR_MATCH_SHADOW = 0U }

函式
constexpr unsigned int	operator+ (Mask e)
constexpr unsigned int	operator+ (Shift e)

變數
Register &	CTIMER0
Register &	CTIMER1
Register &	CTIMER2
Register *const	CTIMER [3]

詳細描述

Copyright (c) 2020 ZxyKira All rights reserved.

SPDX-License-Identifier: MIT

列舉型態說明文件

Mask

enum struct chip::ctimer::Mask : unsigned int

strong

列舉值
IR_MR0INT	IR - MR0INT. Interrupt Flag for Match Channel 0 Event
IR_MR1INT	IR - MR1INT. Interrupt Flag for Match Channel 1 Event
IR_MR2INT	IR - MR2INT. Interrupt Flag for Match Channel 2 Event
IR_MR3INT	IR - MR3INT. Interrupt Flag for Match Channel 3 Event
IR_CR0INT	IR - CR0INT. Interrupt Flag for Capture Channel 0 Event
IR_CR1INT	IR - CR1INT. Interrupt Flag for Capture Channel 1 Event
IR_CR2INT	IR - CR2INT. Interrupt Flag for Capture Channel 2 Event
IR_CR3INT	IR - CR3INT. Interrupt Flag for Capture Channel 3 Event
TCR_CEN	TCR - CEN. Counter Enable [0b0] Disable [0b1] Enable
TCR_CRST	TCR - CRST. Counter Reset Enable [0b0] Disable [0b1] Enable
TCR_AGCEN	TCR - AGCEN. Allow Global Count Enable [0b0] Disable [0b1] Enable
TCR_ATCEN	TCR - ATCEN. Allow Trigger Count Enable [0b0] Disable [0b1] Enable
TC_TCVAL	TC - TCVAL. Timer Counter Value
PR_PRVAL	PR - PRVAL. Prescale Reload Value
PC_PCVAL	PC - PCVAL. Prescale Counter Value
MCR_MR0I	MCR - MR0I. Interrupt on MR0 [0b0] Does not generate [0b1] Generates
MCR_MR0R	MCR - MR0R. Reset on MR0 [0b0] Does not reset [0b1] Resets
MCR_MR0S	MCR - MR0S. Stop on MR0 [0b0] Does not stop [0b1] Stops
MCR_MR1I	MCR - MR1I. Interrupt on MR1 [0b0] Does not generate [0b1] Generates
MCR_MR1R	MCR - MR1R. Reset on MR1 [0b0] Does not reset [0b1] Resets
MCR_MR1S	MCR - MR1S. Stop on MR1 [0b0] Does not stop [0b1] Stops
MCR_MR2I	MCR - MR2I. Interrupt on MR2 [0b0] Does not generate [0b1] Generates
MCR_MR2R	MCR - MR2R. Reset on MR2 [0b0] Does not reset [0b1] Resets
MCR_MR2S	MCR - MR2S. Stop on MR2 [0b0] Does not stop [0b1] Stops
MCR_MR3I	MCR - MR3I. Interrupt on MR3 [0b0] Does not generate [0b1] Generates
MCR_MR3R	MCR - MR3R. Reset on MR3 [0b0] Does not reset [0b1] Resets
MCR_MR3S	MCR - MR3S. Stop on MR3 [0b0] Does not stop [0b1] Stops
MCR_MR0RL	MCR - MR0RL. Reload MR [0b0] Does not reload [0b1] Reloads
MCR_MR1RL	MCR - MR1RL. Reload MR [0b0] Does not reload [0b1] Reloads
MCR_MR2RL	MCR - MR2RL. Reload MR [0b0] Does not reload [0b1] Reloads
MCR_MR3RL	MCR - MR3RL. Reload MR [0b0] Does not reload [0b1] Reloads
MR_MATCH	MR - MATCH. Timer Counter Match Value
CCR_CAP0RE	CCR - CAP0RE. Rising Edge of Capture Channel 0 [0b0] Does not load [0b1] Loads
CCR_CAP0FE	CCR - CAP0FE. Falling Edge of Capture Channel 0 [0b0] Does not load [0b1] Loads
CCR_CAP0I	CCR - CAP0I. Generate Interrupt on Channel 0 Capture Event [0b0] Does not generate [0b1] Generates
CCR_CAP1RE	CCR - CAP1RE. Rising Edge of Capture Channel 1 [0b0] Does not load [0b1] Loads
CCR_CAP1FE	CCR - CAP1FE. Falling Edge of Capture Channel 1 [0b0] Does not load [0b1] Loads
CCR_CAP1I	CCR - CAP1I. Generate Interrupt on Channel 1 Capture Event [0b0] Does not generates [0b1] Generates
CCR_CAP2RE	CCR - CAP2RE. Rising Edge of Capture Channel 2 [0b0] Does not load [0b1] Loads
CCR_CAP2FE	CCR - CAP2FE. Falling Edge of Capture Channel 2 [0b0] Does not load [0b1] Loads
CCR_CAP2I	CCR - CAP2I. Generate Interrupt on Channel 2 Capture Event [0b0] Does not generate [0b1] Generates
CCR_CAP3RE	CCR - CAP3RE. Rising Edge of Capture Channel 3 [0b0] Does not load [0b1] Loads
CCR_CAP3FE	CCR - CAP3FE. Falling Edge of Capture Channel 3 [0b0] Does not load [0b1] Loads
CCR_CAP3I	CCR - CAP3I. Generate Interrupt on Channel 3 Capture Event [0b0] Does not generate [0b1] Generates
CR_CAP	CR - CAP. Timer Counter Capture Value
EMR_EM0	EMR - EM0. External Match 0 [0b0] Low [0b1] High
EMR_EM1	EMR - EM1. External Match 1 [0b0] Low [0b1] High
EMR_EM2	EMR - EM2. External Match 2 [0b0] Low [0b1] High
EMR_EM3	EMR - EM3. External Match 3 [0b0] Low [0b1] High
EMR_EMC0	EMR - EMC0. External Match Control 0 [0b00] Does nothing [0b01] Goes low [0b10] Goes high [0b11] Toggles
EMR_EMC1	EMR - EMC1. External Match Control 1 [0b00] Does nothing [0b01] Goes low [0b10] Goes high [0b11] Toggles
EMR_EMC2	EMR - EMC2. External Match Control 2 [0b00] Does nothing [0b01] Goes low [0b10] Goes high [0b11] Toggles
EMR_EMC3	EMR - EMC3. External Match Control 3 [0b00] Does nothing [0b01] Goes low [0b10] Goes high [0b11] Toggles
CTCR_CTMODE	CTCR - CTMODE. Counter Timer Mode [0b00] Timer mode [0b01] Counter mode rising edge [0b10] Counter mode falling edge [0b11] Counter mode dual edge
CTCR_CINSEL	CTCR - CINSEL. Count Input Select [0b00] Channel 0, CAPn[0] for CTIMERn [0b01] Channel 1, CAPn[1] for CTIMERn [0b10] Channel 2, CAPn[2] for CTIMERn [0b11] Channel 3, CAPn[3] for CTIMERn
CTCR_ENCC	CTCR - ENCC. Capture Channel Enable
CTCR_SELCC	CTCR - SELCC. Edge Select [0b000] Capture channel 0 rising edge [0b001] Capture channel 0 falling edge [0b010] Capture channel 1 rising edge [0b011] Capture channel 1 falling edge [0b100] Capture channel 2 rising edge [0b101] Capture channel 2 falling edge
PWMC_PWMEN0	PWMC - PWMEN0. PWM Mode Enable for Channel 0 [0b0] Disable [0b1] Enable
PWMC_PWMEN1	PWMC - PWMEN1. PWM Mode Enable for Channel 1 [0b0] Disable [0b1] Enable
PWMC_PWMEN2	PWMC - PWMEN2. PWM Mode Enable for Channel 2 [0b0] Disable [0b1] Enable
PWMC_PWMEN3	PWMC - PWMEN3. PWM Mode Enable for Channel 3 [0b0] Disable [0b1] Enable
MSR_MATCH_SHADOW	MSR - MATCH_SHADOW. Timer Counter Match Shadow Value

Shift

enum struct chip::ctimer::Shift : unsigned int

strong

列舉值
IR_MR0INT	IR - MR0INT. Interrupt Flag for Match Channel 0 Event
IR_MR1INT	IR - MR1INT. Interrupt Flag for Match Channel 1 Event
IR_MR2INT	IR - MR2INT. Interrupt Flag for Match Channel 2 Event
IR_MR3INT	IR - MR3INT. Interrupt Flag for Match Channel 3 Event
IR_CR0INT	IR - CR0INT. Interrupt Flag for Capture Channel 0 Event
IR_CR1INT	IR - CR1INT. Interrupt Flag for Capture Channel 1 Event
IR_CR2INT	IR - CR2INT. Interrupt Flag for Capture Channel 2 Event
IR_CR3INT	IR - CR3INT. Interrupt Flag for Capture Channel 3 Event
TCR_CEN	TCR - CEN. Counter Enable [0b0] Disable [0b1] Enable
TCR_CRST	TCR - CRST. Counter Reset Enable [0b0] Disable [0b1] Enable
TCR_AGCEN	TCR - AGCEN. Allow Global Count Enable [0b0] Disable [0b1] Enable
TCR_ATCEN	TCR - ATCEN. Allow Trigger Count Enable [0b0] Disable [0b1] Enable
TC_TCVAL	TC - TCVAL. Timer Counter Value
PR_PRVAL	PR - PRVAL. Prescale Reload Value
PC_PCVAL	PC - PCVAL. Prescale Counter Value
MCR_MR0I	MCR - MR0I. Interrupt on MR0 [0b0] Does not generate [0b1] Generates
MCR_MR0R	MCR - MR0R. Reset on MR0 [0b0] Does not reset [0b1] Resets
MCR_MR0S	MCR - MR0S. Stop on MR0 [0b0] Does not stop [0b1] Stops
MCR_MR1I	MCR - MR1I. Interrupt on MR1 [0b0] Does not generate [0b1] Generates
MCR_MR1R	MCR - MR1R. Reset on MR1 [0b0] Does not reset [0b1] Resets
MCR_MR1S	MCR - MR1S. Stop on MR1 [0b0] Does not stop [0b1] Stops
MCR_MR2I	MCR - MR2I. Interrupt on MR2 [0b0] Does not generate [0b1] Generates
MCR_MR2R	MCR - MR2R. Reset on MR2 [0b0] Does not reset [0b1] Resets
MCR_MR2S	MCR - MR2S. Stop on MR2 [0b0] Does not stop [0b1] Stops
MCR_MR3I	MCR - MR3I. Interrupt on MR3 [0b0] Does not generate [0b1] Generates
MCR_MR3R	MCR - MR3R. Reset on MR3 [0b0] Does not reset [0b1] Resets
MCR_MR3S	MCR - MR3S. Stop on MR3 [0b0] Does not stop [0b1] Stops
MCR_MR0RL	MCR - MR0RL. Reload MR [0b0] Does not reload [0b1] Reloads
MCR_MR1RL	MCR - MR1RL. Reload MR [0b0] Does not reload [0b1] Reloads
MCR_MR2RL	MCR - MR2RL. Reload MR [0b0] Does not reload [0b1] Reloads
MCR_MR3RL	MCR - MR3RL. Reload MR [0b0] Does not reload [0b1] Reloads
MR_MATCH	MR - MATCH. Timer Counter Match Value
CCR_CAP0RE	CCR - CAP0RE. Rising Edge of Capture Channel 0 [0b0] Does not load [0b1] Loads
CCR_CAP0FE	CCR - CAP0FE. Falling Edge of Capture Channel 0 [0b0] Does not load [0b1] Loads
CCR_CAP0I	CCR - CAP0I. Generate Interrupt on Channel 0 Capture Event [0b0] Does not generate [0b1] Generates
CCR_CAP1RE	CCR - CAP1RE. Rising Edge of Capture Channel 1 [0b0] Does not load [0b1] Loads
CCR_CAP1FE	CCR - CAP1FE. Falling Edge of Capture Channel 1 [0b0] Does not load [0b1] Loads
CCR_CAP1I	CCR - CAP1I. Generate Interrupt on Channel 1 Capture Event [0b0] Does not generates [0b1] Generates
CCR_CAP2RE	CCR - CAP2RE. Rising Edge of Capture Channel 2 [0b0] Does not load [0b1] Loads
CCR_CAP2FE	CCR - CAP2FE. Falling Edge of Capture Channel 2 [0b0] Does not load [0b1] Loads
CCR_CAP2I	CCR - CAP2I. Generate Interrupt on Channel 2 Capture Event [0b0] Does not generate [0b1] Generates
CCR_CAP3RE	CCR - CAP3RE. Rising Edge of Capture Channel 3 [0b0] Does not load [0b1] Loads
CCR_CAP3FE	CCR - CAP3FE. Falling Edge of Capture Channel 3 [0b0] Does not load [0b1] Loads
CCR_CAP3I	CCR - CAP3I. Generate Interrupt on Channel 3 Capture Event [0b0] Does not generate [0b1] Generates
CR_CAP	CR - CAP. Timer Counter Capture Value
EMR_EM0	EMR - EM0. External Match 0 [0b0] Low [0b1] High
EMR_EM1	EMR - EM1. External Match 1 [0b0] Low [0b1] High
EMR_EM2	EMR - EM2. External Match 2 [0b0] Low [0b1] High
EMR_EM3	EMR - EM3. External Match 3 [0b0] Low [0b1] High
EMR_EMC0	EMR - EMC0. External Match Control 0 [0b00] Does nothing [0b01] Goes low [0b10] Goes high [0b11] Toggles
EMR_EMC1	EMR - EMC1. External Match Control 1 [0b00] Does nothing [0b01] Goes low [0b10] Goes high [0b11] Toggles
EMR_EMC2	EMR - EMC2. External Match Control 2 [0b00] Does nothing [0b01] Goes low [0b10] Goes high [0b11] Toggles
EMR_EMC3	EMR - EMC3. External Match Control 3 [0b00] Does nothing [0b01] Goes low [0b10] Goes high [0b11] Toggles
CTCR_CTMODE	CTCR - CTMODE. Counter Timer Mode [0b00] Timer mode [0b01] Counter mode rising edge [0b10] Counter mode falling edge [0b11] Counter mode dual edge
CTCR_CINSEL	CTCR - CINSEL. Count Input Select [0b00] Channel 0, CAPn[0] for CTIMERn [0b01] Channel 1, CAPn[1] for CTIMERn [0b10] Channel 2, CAPn[2] for CTIMERn [0b11] Channel 3, CAPn[3] for CTIMERn
CTCR_ENCC	CTCR - ENCC. Capture Channel Enable
CTCR_SELCC	CTCR - SELCC. Edge Select [0b000] Capture channel 0 rising edge [0b001] Capture channel 0 falling edge [0b010] Capture channel 1 rising edge [0b011] Capture channel 1 falling edge [0b100] Capture channel 2 rising edge [0b101] Capture channel 2 falling edge
PWMC_PWMEN0	PWMC - PWMEN0. PWM Mode Enable for Channel 0 [0b0] Disable [0b1] Enable
PWMC_PWMEN1	PWMC - PWMEN1. PWM Mode Enable for Channel 1 [0b0] Disable [0b1] Enable
PWMC_PWMEN2	PWMC - PWMEN2. PWM Mode Enable for Channel 2 [0b0] Disable [0b1] Enable
PWMC_PWMEN3	PWMC - PWMEN3. PWM Mode Enable for Channel 3 [0b0] Disable [0b1] Enable
MSR_MATCH_SHADOW	MSR - MATCH_SHADOW. Timer Counter Match Shadow Value