chip::clock 命名空間(Namespace)參考文件

複合項目
class	Clock
struct	FircTrimConfig
struct	SircTrimConfig

列舉型態
enum struct	AttachID : unsigned int {   CLK_IN_TO_MAIN_CLK = CLK_ATTACH_MUX(SelectName::SCGSCS, 1U) , FRO12M_TO_MAIN_CLK = CLK_ATTACH_MUX(SelectName::SCGSCS, 2U) , FRO_HF_TO_MAIN_CLK = CLK_ATTACH_MUX(SelectName::SCGSCS, 3U) , CLK_16K_TO_MAIN_CLK = CLK_ATTACH_MUX(SelectName::SCGSCS, 4U) ,   NONE_TO_MAIN_CLK = CLK_ATTACH_MUX(SelectName::SCGSCS, 7U) , FRO12M_TO_I3C0FCLK = CLK_ATTACH_MUX(SelectName::I3C0_FCLK, 0U) , FRO_HF_DIV_TO_I3C0FCLK = CLK_ATTACH_MUX(SelectName::I3C0_FCLK, 2U) , CLK_IN_TO_I3C0FCLK = CLK_ATTACH_MUX(SelectName::I3C0_FCLK, 3U) ,   CLK_1M_TO_I3C0FCLK = CLK_ATTACH_MUX(SelectName::I3C0_FCLK, 5U) , NONE_TO_I3C0FCLK = CLK_ATTACH_MUX(SelectName::I3C0_FCLK, 7U) , FRO12M_TO_CTIMER0 = CLK_ATTACH_MUX(SelectName::CTIMER0, 0U) , FRO_HF_TO_CTIMER0 = CLK_ATTACH_MUX(SelectName::CTIMER0, 1U) ,   CLK_IN_TO_CTIMER0 = CLK_ATTACH_MUX(SelectName::CTIMER0, 3U) , CLK_16K_TO_CTIMER0 = CLK_ATTACH_MUX(SelectName::CTIMER0, 4U) , CLK_1M_TO_CTIMER0 = CLK_ATTACH_MUX(SelectName::CTIMER0, 5U) , NONE_TO_CTIMER0 = CLK_ATTACH_MUX(SelectName::CTIMER0, 7U) ,   FRO12M_TO_CTIMER1 = CLK_ATTACH_MUX(SelectName::CTIMER1, 0U) , FRO_HF_TO_CTIMER1 = CLK_ATTACH_MUX(SelectName::CTIMER1, 1U) , CLK_IN_TO_CTIMER1 = CLK_ATTACH_MUX(SelectName::CTIMER1, 3U) , CLK_16K_TO_CTIMER1 = CLK_ATTACH_MUX(SelectName::CTIMER1, 4U) ,   CLK_1M_TO_CTIMER1 = CLK_ATTACH_MUX(SelectName::CTIMER1, 5U) , NONE_TO_CTIMER1 = CLK_ATTACH_MUX(SelectName::CTIMER1, 7U) , FRO12M_TO_CTIMER2 = CLK_ATTACH_MUX(SelectName::CTIMER2, 0U) , FRO_HF_TO_CTIMER2 = CLK_ATTACH_MUX(SelectName::CTIMER2, 1U) ,   CLK_IN_TO_CTIMER2 = CLK_ATTACH_MUX(SelectName::CTIMER2, 3U) , CLK_16K_TO_CTIMER2 = CLK_ATTACH_MUX(SelectName::CTIMER2, 4U) , CLK_1M_TO_CTIMER2 = CLK_ATTACH_MUX(SelectName::CTIMER2, 5U) , NONE_TO_CTIMER2 = CLK_ATTACH_MUX(SelectName::CTIMER2, 7U) ,   FRO12M_TO_LPI2C0 = CLK_ATTACH_MUX(SelectName::LPI2C0, 0U) , FRO_HF_DIV_TO_LPI2C0 = CLK_ATTACH_MUX(SelectName::LPI2C0, 2U) , CLK_IN_TO_LPI2C0 = CLK_ATTACH_MUX(SelectName::LPI2C0, 3U) , CLK_1M_TO_LPI2C0 = CLK_ATTACH_MUX(SelectName::LPI2C0, 5U) ,   NONE_TO_LPI2C0 = CLK_ATTACH_MUX(SelectName::LPI2C0, 7U) , FRO12M_TO_LPSPI0 = CLK_ATTACH_MUX(SelectName::LPSPI0, 0U) , FRO_HF_DIV_TO_LPSPI0 = CLK_ATTACH_MUX(SelectName::LPSPI0, 2U) , CLK_IN_TO_LPSPI0 = CLK_ATTACH_MUX(SelectName::LPSPI0, 3U) ,   CLK_1M_TO_LPSPI0 = CLK_ATTACH_MUX(SelectName::LPSPI0, 5U) , NONE_TO_LPSPI0 = CLK_ATTACH_MUX(SelectName::LPSPI0, 7U) , FRO12M_TO_LPSPI1 = CLK_ATTACH_MUX(SelectName::LPSPI1, 0U) , FRO_HF_DIV_TO_LPSPI1 = CLK_ATTACH_MUX(SelectName::LPSPI1, 2U) ,   CLK_IN_TO_LPSPI1 = CLK_ATTACH_MUX(SelectName::LPSPI1, 3U) , CLK_1M_TO_LPSPI1 = CLK_ATTACH_MUX(SelectName::LPSPI1, 5U) , NONE_TO_LPSPI1 = CLK_ATTACH_MUX(SelectName::LPSPI1, 7U) , FRO12M_TO_LPUART0 = CLK_ATTACH_MUX(SelectName::LPUART0, 0U) ,   FRO_HF_DIV_TO_LPUART0 = CLK_ATTACH_MUX(SelectName::LPUART0, 2U) , CLK_IN_TO_LPUART0 = CLK_ATTACH_MUX(SelectName::LPUART0, 3U) , CLK_16K_TO_LPUART0 = CLK_ATTACH_MUX(SelectName::LPUART0, 4U) , CLK_1M_TO_LPUART0 = CLK_ATTACH_MUX(SelectName::LPUART0, 5U) ,   NONE_TO_LPUART0 = CLK_ATTACH_MUX(SelectName::LPUART0, 7U) , FRO12M_TO_LPUART1 = CLK_ATTACH_MUX(SelectName::LPUART1, 0U) , FRO_HF_DIV_TO_LPUART1 = CLK_ATTACH_MUX(SelectName::LPUART1, 2U) , CLK_IN_TO_LPUART1 = CLK_ATTACH_MUX(SelectName::LPUART1, 3U) ,   CLK_16K_TO_LPUART1 = CLK_ATTACH_MUX(SelectName::LPUART1, 4U) , CLK_1M_TO_LPUART1 = CLK_ATTACH_MUX(SelectName::LPUART1, 5U) , NONE_TO_LPUART1 = CLK_ATTACH_MUX(SelectName::LPUART1, 7U) , FRO12M_TO_LPUART2 = CLK_ATTACH_MUX(SelectName::LPUART2, 0U) ,   FRO_HF_DIV_TO_LPUART2 = CLK_ATTACH_MUX(SelectName::LPUART2, 2U) , CLK_IN_TO_LPUART2 = CLK_ATTACH_MUX(SelectName::LPUART2, 3U) , CLK_16K_TO_LPUART2 = CLK_ATTACH_MUX(SelectName::LPUART2, 4U) , CLK_1M_TO_LPUART2 = CLK_ATTACH_MUX(SelectName::LPUART2, 5U) ,   NONE_TO_LPUART2 = CLK_ATTACH_MUX(SelectName::LPUART2, 7U) , CLK_48M_TO_USB0 = CLK_ATTACH_MUX(SelectName::USB0, 1U) , CLK_IN_TO_USB0 = CLK_ATTACH_MUX(SelectName::USB0, 2U) , NONE_TO_USB0 = CLK_ATTACH_MUX(SelectName::USB0, 3U) ,   FRO12M_TO_LPTMR0 = CLK_ATTACH_MUX(SelectName::LPTMR0, 0U) , FRO_HF_DIV_TO_LPTMR0 = CLK_ATTACH_MUX(SelectName::LPTMR0, 2U) , CLK_IN_TO_LPTMR0 = CLK_ATTACH_MUX(SelectName::LPTMR0, 3U) , CLK_1M_TO_LPTMR0 = CLK_ATTACH_MUX(SelectName::LPTMR0, 5U) ,   NONE_TO_LPTMR0 = CLK_ATTACH_MUX(SelectName::LPTMR0, 7U) , CLK_16K_TO_OSTIMER = CLK_ATTACH_MUX(SelectName::OSTIMER0, 0U) , CLK_1M_TO_OSTIMER = CLK_ATTACH_MUX(SelectName::OSTIMER0, 2U) , NONE_TO_OSTIMER = CLK_ATTACH_MUX(SelectName::OSTIMER0, 3U) ,   FRO12M_TO_ADC0 = CLK_ATTACH_MUX(SelectName::ADC0, 0U) , FRO_HF_TO_ADC0 = CLK_ATTACH_MUX(SelectName::ADC0, 1U) , CLK_IN_TO_ADC0 = CLK_ATTACH_MUX(SelectName::ADC0, 3U) , CLK_1M_TO_ADC0 = CLK_ATTACH_MUX(SelectName::ADC0, 5U) ,   NONE_TO_ADC0 = CLK_ATTACH_MUX(SelectName::ADC0, 7U) , FRO12M_TO_CMP0 = CLK_ATTACH_MUX(SelectName::CMP0_RR, 0U) , FRO_HF_DIV_TO_CMP0 = CLK_ATTACH_MUX(SelectName::CMP0_RR, 2U) , CLK_IN_TO_CMP0 = CLK_ATTACH_MUX(SelectName::CMP0_RR, 3U) ,   CLK_1M_TO_CMP0 = CLK_ATTACH_MUX(SelectName::CMP0_RR, 5U) , NONE_TO_CMP0 = CLK_ATTACH_MUX(SelectName::CMP0_RR, 7U) , FRO12M_TO_CMP1 = CLK_ATTACH_MUX(SelectName::CMP1_RR, 0U) , FRO_HF_DIV_TO_CMP1 = CLK_ATTACH_MUX(SelectName::CMP1_RR, 2U) ,   CLK_IN_TO_CMP1 = CLK_ATTACH_MUX(SelectName::CMP1_RR, 3U) , CLK_1M_TO_CMP1 = CLK_ATTACH_MUX(SelectName::CMP1_RR, 5U) , NONE_TO_CMP1 = CLK_ATTACH_MUX(SelectName::CMP1_RR, 7U) , CPU_CLK_TO_TRACE = CLK_ATTACH_MUX(SelectName::TRACE, 0U) ,   CLK_1M_TO_TRACE = CLK_ATTACH_MUX(SelectName::TRACE, 1U) , CLK_16K_TO_TRACE = CLK_ATTACH_MUX(SelectName::TRACE, 2U) , NONE_TO_TRACE = CLK_ATTACH_MUX(SelectName::TRACE, 3U) , FRO12M_TO_CLKOUT = CLK_ATTACH_MUX(SelectName::CLKOUT, 0U) ,   FRO_HF_DIV_TO_CLKOUT = CLK_ATTACH_MUX(SelectName::CLKOUT, 1U) , CLK_IN_TO_CLKOUT = CLK_ATTACH_MUX(SelectName::CLKOUT, 2U) , CLK_16K_TO_CLKOUT = CLK_ATTACH_MUX(SelectName::CLKOUT, 3U) , SLOW_CLK_TO_CLKOUT = CLK_ATTACH_MUX(SelectName::CLKOUT, 6U) ,   NONE_TO_CLKOUT = CLK_ATTACH_MUX(SelectName::CLKOUT, 7U) , CPU_CLK_TO_SYSTICK = CLK_ATTACH_MUX(SelectName::SYSTICK, 0U) , CLK_1M_TO_SYSTICK = CLK_ATTACH_MUX(SelectName::SYSTICK, 1U) , CLK_16K_TO_SYSTICK = CLK_ATTACH_MUX(SelectName::SYSTICK, 2U) ,   NONE_TO_SYSTICK = CLK_ATTACH_MUX(SelectName::SYSTICK, 3U) , NONE_TO_NONE = (0xFFFFFFFFU) }
enum struct	Div : unsigned int {   I3C0_FCLK = (0x0A4U) , CTIMER0 = (0x0ACU) , CTIMER1 = (0x0B4U) , CTIMER2 = (0x0BCU) ,   WWDT0 = (0x0C4U) , LPI2C0 = (0x0CCU) , LPSPI0 = (0x0D4U) , LPSPI1 = (0x0DCU) ,   LPUART0 = (0x0E4U) , LPUART1 = (0x0ECU) , LPUART2 = (0x0F4U) , LPTMR0 = (0x104U) ,   ADC0 = (0x114U) , CMP0_FUNC = (0x11CU) , CMP0_RR = (0x124U) , CMP1_FUNC = (0x12CU) ,   CMP1_RR = (0x134U) , TRACE = (0x13CU) , CLKOUT = (0x144U) , SYSTICK = (0x14CU) ,   FRO_HF_DIV = (0x154U) , SLOWCLK = (0x378U) , AHBCLK = (0x380U) , MAX = (0x380U) }
enum struct	FircTrimSource : unsigned int { USB0 = 0U , SYS_OSC = 2U }
enum struct	GateName : unsigned int {   INPUTMUX0 = (0x00000U | (0U)) , INPUTMUX = (0x00000U | (0U)) , I3C0 = (0x00000U | (1U)) , CTIMER0 = (0x00000U | (2U)) ,   CTIMER1 = (0x00000U | (3U)) , CTIMER2 = (0x00000U | (4U)) , FREQME = (0x00000U | (5U)) , UTICK0 = (0x00000U | (6U)) ,   WWDT0 = (0x00000U | (7U)) , DMA = (0x00000U | (8U)) , AOI0 = (0x00000U | (9U)) , CRC = (0x00000U | (10U)) ,   CRC0 = (0x00000U | (10U)) , EIM = (0x00000U | (11U)) , ERM = (0x00000U | (12U)) , LPI2C0 = (0x00000U | (16U)) ,   LPSPI0 = (0x00000U | (17U)) , LPSPI1 = (0x00000U | (18U)) , LPUART0 = (0x00000U | (19U)) , LPUART1 = (0x00000U | (20U)) ,   LPUART2 = (0x00000U | (21U)) , USB0 = (0x00000U | (22U)) , QDC0 = (0x00000U | (23U)) , FLEXPWM0 = (0x00000U | (24U)) ,   OSTIMER0 = (0x00000U | (25U)) , ADC0 = (0x00000U | (26U)) , CMP0 = (0x00000U | (27U)) , CMP1 = (0x00000U | (28U)) ,   PORT0 = (0x00000U | (29U)) , PORT1 = (0x00000U | (30U)) , PORT2 = (0x00000U | (31U)) , PORT3 = ((0x10U << 16U) | (0U)) ,   ATX0 = ((0x10U << 16U) | (1U)) , MTR = ((0x10U << 16U) | (2U)) , TCU = ((0x10U << 16U) | (3U)) , EZRAMC_RAMA = ((0x10U << 16U) | (4U)) ,   GPIO0 = ((0x10U << 16U) | (5U)) , GPIO1 = ((0x10U << 16U) | (6U)) , GPIO2 = ((0x10U << 16U) | (7U)) , GPIO3 = ((0x10U << 16U) | (8U)) ,   ROMCP = ((0x10U << 16U) | (9U)) , PWMSM0 = ((REG_PWM0SUBCTL << 16U) | (0U)) , PWMSM1 = ((REG_PWM0SUBCTL << 16U) | (1U)) , PWMSM2 = ((REG_PWM0SUBCTL << 16U) | (2U)) ,   NOT_AVAIL = (0xFFFFFFFFU) }
enum struct	MonitorMode : unsigned int { kSCG_SysOscMonitorDisable = 0U , kSCG_SysOscMonitorInt = +chip::scg::Mask::SOSCCSR_SOSCCM , kSCG_SysOscMonitorReset }
enum struct	Name : unsigned int {   MAIN , CORE_SYS , SYSTEM , BUS ,   EXT , FRO_HF , FRO_HF_DIV , CLK_48M ,   FRP_12M , CLK_1M , FRO_16K , CLK_16K0 ,   CLK_16K1 , SLOW_CLK }
enum struct	SelectName : unsigned int {   I3C0_FCLK = (0x0A0U) , CTIMER0 = (0x0A8U) , CTIMER1 = (0x0B0U) , CTIMER2 = (0x0B8U) ,   LPI2C0 = (0x0C8U) , LPSPI0 = (0x0D0U) , LPSPI1 = (0x0D8U) , LPUART0 = (0x0E0U) ,   LPUART1 = (0x0E8U) , LPUART2 = (0x0F0U) , USB0 = (0x0F8U) , LPTMR0 = (0x100U) ,   OSTIMER0 = (0x108U) , ADC0 = (0x110U) , CMP0_RR = (0x120U) , CMP1_RR = (0x130U) ,   TRACE = (0x138U) , CLKOUT = (0x140U) , SYSTICK = (0x148U) , SCGSCS = (0x200U) ,   MAX = (0x200U) }
enum struct	SircTrimMode : unsigned int { NON_UPDATE = (0x100U) , UPDATE = (0x100U) | (0x200U) }
enum struct	SircTrimSource : unsigned int { NO_TRIM_SRC = 0 , SYS_OSC = 2U }

函式
constexpr unsigned int	operator+ (AttachID e)
constexpr unsigned int	operator+ (Div e)
constexpr unsigned int	operator+ (FircTrimSource e)
uint32	getGateNameOffset (const GateName _this)
uint32	getGateNameShift (const GateName _this)
constexpr unsigned int	operator+ (MonitorMode e)
constexpr unsigned int	operator+ (Name e)
constexpr unsigned int	operator+ (SelectName e)
constexpr unsigned int	operator+ (SircTrimMode e)
constexpr unsigned int	operator+ (SircTrimSource e)

變數
const uint32	REG_PWM0SUBCTL = 250U

詳細描述

Copyright (c) 2020 ZxyKira All rights reserved.

SPDX-License-Identifier: MIT

列舉型態說明文件

AttachID

enum struct chip::clock::AttachID : unsigned int

strong

列舉值
CLK_IN_TO_MAIN_CLK	Attach clk_in to MAIN_CLK.
FRO12M_TO_MAIN_CLK	Attach FRO_12M to MAIN_CLK.
FRO_HF_TO_MAIN_CLK	Attach FRO_HF to MAIN_CLK.
CLK_16K_TO_MAIN_CLK	Attach CLK_16K[1] to MAIN_CLK.
NONE_TO_MAIN_CLK	Attach NONE to MAIN_CLK.
FRO12M_TO_I3C0FCLK	Attach FRO12M to I3C0FCLK.
FRO_HF_DIV_TO_I3C0FCLK	Attach FRO_HF_DIV to I3C0FCLK.
CLK_IN_TO_I3C0FCLK	Attach CLK_IN to I3C0FCLK.
CLK_1M_TO_I3C0FCLK	Attach CLK_1M to I3C0FCLK.
NONE_TO_I3C0FCLK	Attach NONE to I3C0FCLK.
FRO12M_TO_CTIMER0	Attach FRO12M to CTIMER0.
FRO_HF_TO_CTIMER0	Attach FRO_HF to CTIMER0.
CLK_IN_TO_CTIMER0	Attach CLK_IN to CTIMER0.
CLK_16K_TO_CTIMER0	Attach CLK_16K to CTIMER0.
CLK_1M_TO_CTIMER0	Attach CLK_1M to CTIMER0.
NONE_TO_CTIMER0	Attach NONE to CTIMER0.
FRO12M_TO_CTIMER1	Attach FRO12M to CTIMER1.
FRO_HF_TO_CTIMER1	Attach FRO_HF to CTIMER1.
CLK_IN_TO_CTIMER1	Attach CLK_IN to CTIMER1.
CLK_16K_TO_CTIMER1	Attach CLK_16K to CTIMER1.
CLK_1M_TO_CTIMER1	Attach CLK_1M to CTIMER1.
NONE_TO_CTIMER1	Attach NONE to CTIMER1.
FRO12M_TO_CTIMER2	Attach FRO12M to CTIMER2.
FRO_HF_TO_CTIMER2	Attach FRO_HF to CTIMER2.
CLK_IN_TO_CTIMER2	Attach CLK_IN to CTIMER2.
CLK_16K_TO_CTIMER2	Attach CLK_16K to CTIMER2.
CLK_1M_TO_CTIMER2	Attach CLK_1M to CTIMER2.
NONE_TO_CTIMER2	Attach NONE to CTIMER2.
FRO12M_TO_LPI2C0	Attach FRO12M to LPI2C0.
FRO_HF_DIV_TO_LPI2C0	Attach FRO_HF_DIV to LPI2C0.
CLK_IN_TO_LPI2C0	Attach CLK_IN to LPI2C0.
CLK_1M_TO_LPI2C0	Attach CLK_1M to LPI2C0.
NONE_TO_LPI2C0	Attach NONE to LPI2C0.
FRO12M_TO_LPSPI0	Attach FRO12M to LPSPI0.
FRO_HF_DIV_TO_LPSPI0	Attach FRO_HF_DIV to LPSPI0.
CLK_IN_TO_LPSPI0	Attach CLK_IN to LPSPI0.
CLK_1M_TO_LPSPI0	Attach CLK_1M to LPSPI0.
NONE_TO_LPSPI0	Attach NONE to LPSPI0.
FRO12M_TO_LPSPI1	Attach FRO12M to LPSPI1.
FRO_HF_DIV_TO_LPSPI1	Attach FRO_HF_DIV to LPSPI1.
CLK_IN_TO_LPSPI1	Attach CLK_IN to LPSPI1.
CLK_1M_TO_LPSPI1	Attach CLK_1M to LPSPI1.
NONE_TO_LPSPI1	Attach NONE to LPSPI1.
FRO12M_TO_LPUART0	Attach FRO12M to LPUART0.
FRO_HF_DIV_TO_LPUART0	Attach FRO_HF_DIV to LPUART0.
CLK_IN_TO_LPUART0	Attach CLK_IN to LPUART0.
CLK_16K_TO_LPUART0	Attach CLK_16K to LPUART0.
CLK_1M_TO_LPUART0	Attach CLK_1M to LPUART0.
NONE_TO_LPUART0	Attach NONE to LPUART0.
FRO12M_TO_LPUART1	Attach FRO12M to LPUART1.
FRO_HF_DIV_TO_LPUART1	Attach FRO_HF_DIV to LPUART1.
CLK_IN_TO_LPUART1	Attach CLK_IN to LPUART1.
CLK_16K_TO_LPUART1	Attach CLK_16K to LPUART1.
CLK_1M_TO_LPUART1	Attach CLK_1M to LPUART1.
NONE_TO_LPUART1	Attach NONE to LPUART1.
FRO12M_TO_LPUART2	Attach FRO12M to LPUART2.
FRO_HF_DIV_TO_LPUART2	Attach FRO_HF_DIV to LPUART2.
CLK_IN_TO_LPUART2	Attach CLK_IN to LPUART2.
CLK_16K_TO_LPUART2	Attach CLK_16K to LPUART2.
CLK_1M_TO_LPUART2	Attach CLK_1M to LPUART2.
NONE_TO_LPUART2	Attach NONE to LPUART2.
CLK_48M_TO_USB0	Attach FRO12M to USB0.
CLK_IN_TO_USB0	Attach CLK_IN to USB0.
NONE_TO_USB0	Attach NONE to USB0.
FRO12M_TO_LPTMR0	Attach FRO12M to LPTMR0.
FRO_HF_DIV_TO_LPTMR0	Attach FRO_HF_DIV to LPTMR0.
CLK_IN_TO_LPTMR0	Attach CLK_IN to LPTMR0.
CLK_1M_TO_LPTMR0	Attach CLK_1M to LPTMR0.
NONE_TO_LPTMR0	Attach NONE to LPTMR0.
CLK_16K_TO_OSTIMER	Attach FRO16K to OSTIMER0.
CLK_1M_TO_OSTIMER	Attach CLK_1M to OSTIMER0.
NONE_TO_OSTIMER	Attach NONE to OSTIMER0.
FRO12M_TO_ADC0	Attach FRO12M to ADC0.
FRO_HF_TO_ADC0	Attach FRO_HF to ADC0.
CLK_IN_TO_ADC0	Attach CLK_IN to ADC0.
CLK_1M_TO_ADC0	Attach CLK_1M to ADC0.
NONE_TO_ADC0	Attach NONE to ADC0.
FRO12M_TO_CMP0	Attach FRO12M to CMP0.
FRO_HF_DIV_TO_CMP0	Attach FRO_HF_DIV to CMP0.
CLK_IN_TO_CMP0	Attach CLK_IN to CMP0.
CLK_1M_TO_CMP0	Attach CLK_1M to CMP0.
NONE_TO_CMP0	Attach NONE to CMP0.
FRO12M_TO_CMP1	Attach FRO12M to CMP1.
FRO_HF_DIV_TO_CMP1	Attach FRO_HF_DIV to CMP1.
CLK_IN_TO_CMP1	Attach CLK_IN to CMP1.
CLK_1M_TO_CMP1	Attach CLK_1M to CMP1.
NONE_TO_CMP1	Attach NONE to CMP1.
CPU_CLK_TO_TRACE	Attach CPU_CLK to TRACE.
CLK_1M_TO_TRACE	Attach CLK_1M to TRACE.
CLK_16K_TO_TRACE	Attach CLK_16K to TRACE.
NONE_TO_TRACE	Attach NONE to TRACE.
FRO12M_TO_CLKOUT	Attach FRO12M to CLKOUT.
FRO_HF_DIV_TO_CLKOUT	Attach FRO_HF_DIV to CLKOUT.
CLK_IN_TO_CLKOUT	Attach CLK_IN to CLKOUT.
CLK_16K_TO_CLKOUT	Attach CLK_16K to CLKOUT.
SLOW_CLK_TO_CLKOUT	Attach SLOW_CLK to CLKOUT.
NONE_TO_CLKOUT	Attach NONE to CLKOUT.
CPU_CLK_TO_SYSTICK	Attach CPU_CLK to SYSTICK.
CLK_1M_TO_SYSTICK	Attach CLK_1M to SYSTICK.
CLK_16K_TO_SYSTICK	Attach CLK_16K to SYSTICK.
NONE_TO_SYSTICK	Attach NONE to SYSTICK.
NONE_TO_NONE	Attach NONE to NONE.

Div

enum struct chip::clock::Div : unsigned int

strong

列舉值
I3C0_FCLK	I3C0_FCLK clock divider
CTIMER0	CTIMER0 clock divider
CTIMER1	CTIMER1 clock divider
CTIMER2	CTIMER2 clock divider
WWDT0	WWDT0 clock divider
LPI2C0	LPI2C0 clock divider
LPSPI0	LPSPI0 clock divider
LPSPI1	LPSPI1 clock divider
LPUART0	LPUART0 clock divider
LPUART1	LPUART1 clock divider
LPUART2	LPUART2 clock divider
LPTMR0	LPTMR0 clock divider
ADC0	ADC0 clock divider
CMP0_FUNC	CMP0_FUNC clock divider
CMP0_RR	CMP0_RR clock divider
CMP1_FUNC	CMP1_FUNC clock divider
CMP1_RR	CMP1_RR clock divider
TRACE	TRACE clock divider
CLKOUT	CLKOUT clock divider
SYSTICK	SYSTICK clock divider
FRO_HF_DIV	FRO_HF_DIV clock divider
SLOWCLK	SLOWCLK clock divider
AHBCLK	System clock divider
MAX	MAX clock divider

FircTrimSource

enum struct chip::clock::FircTrimSource : unsigned int

strong

列舉值
USB0	USB0 start of frame (1kHz).
SYS_OSC	System OSC.

GateName

enum struct chip::clock::GateName : unsigned int

strong

列舉值
INPUTMUX0	Clock gate name: INPUTMUX0
INPUTMUX	Clock gate name: INPUTMUX0
I3C0	Clock gate name: I3C0
CTIMER0	Clock gate name: CTIMER0
CTIMER1	Clock gate name: CTIMER1
CTIMER2	Clock gate name: CTIMER2
FREQME	Clock gate name: FREQME
UTICK0	Clock gate name: UTICK0
WWDT0	Clock gate name: WWDT0
DMA	Clock gate name: DMA
AOI0	Clock gate name: AOI0
CRC	Clock gate name: CRC
CRC0	Clock gate name: CRC
EIM	Clock gate name: EIM
ERM	Clock gate name: ERM
LPI2C0	Clock gate name: LPI2C0
LPSPI0	Clock gate name: LPSPI0
LPSPI1	Clock gate name: LPSPI1
LPUART0	Clock gate name: LPUART0
LPUART1	Clock gate name: LPUART1
LPUART2	Clock gate name: LPUART2
USB0	Clock gate name: USB0
QDC0	Clock gate name: QDC0
FLEXPWM0	Clock gate name: FLEXPWM0
OSTIMER0	Clock gate name: OSTIMER0
ADC0	Clock gate name: ADC0
CMP0	Clock gate name: CMP0
CMP1	Clock gate name: CMP1
PORT0	Clock gate name: PORT0
PORT1	Clock gate name: PORT1
PORT2	Clock gate name: PORT2
PORT3	Clock gate name: PORT3
ATX0	Clock gate name: ATX0
MTR	Clock gate name: MTR
TCU	Clock gate name: TCU
EZRAMC_RAMA	Clock gate name: EZRAMC_RAMA
GPIO0	Clock gate name: GPIO0
GPIO1	Clock gate name: GPIO1
GPIO2	Clock gate name: GPIO2
GPIO3	Clock gate name: GPIO3
ROMCP	Clock gate name: ROMCP
PWMSM0	Clock gate name: FlexPWM SM0
PWMSM1	Clock gate name: FlexPWM SM1
PWMSM2	Clock gate name: FlexPWM SM2
NOT_AVAIL	Clock gate name: None

MonitorMode

enum struct chip::clock::MonitorMode : unsigned int

strong

列舉值
kSCG_SysOscMonitorDisable	Monitor disabled.
kSCG_SysOscMonitorInt	Interrupt when the SOSC error is detected.
kSCG_SysOscMonitorReset	Reset when the SOSC error is detected.

Name

enum struct chip::clock::Name : unsigned int

strong

列舉值
MAIN	MAIN_CLK
CORE_SYS	Core/system clock(CPU_CLK)
SYSTEM	AHB clock
BUS	Bus clock (AHB clock)
EXT	External Clock
FRO_HF	FRO192
FRO_HF_DIV	Divided by FRO192
CLK_48M	CLK48M
FRP_12M	FRO12M
CLK_1M	CLK1M
FRO_16K	FRO16K
CLK_16K0	CLK16K[0]
CLK_16K1	CLK16K[1]
SLOW_CLK	SYSTEM_CLK divided by 4

SelectName

enum struct chip::clock::SelectName : unsigned int

strong

列舉值
I3C0_FCLK	I3C0_FCLK clock selection
CTIMER0	CTIMER0 clock selection
CTIMER1	CTIMER1 clock selection
CTIMER2	CTIMER2 clock selection
LPI2C0	LPI2C0 clock selection
LPSPI0	LPSPI0 clock selection
LPSPI1	LPSPI1 clock selection
LPUART0	LPUART0 clock selection
LPUART1	LPUART1 clock selection
LPUART2	LPUART2 clock selection
USB0	USB0 clock selection
LPTMR0	LPTMR0 clock selection
OSTIMER0	OSTIMER0 clock selection
ADC0	ADC0 clock selection
CMP0_RR	CMP0_RR clock selection
CMP1_RR	CMP1_RR clock selection
TRACE	TRACE clock selection
CLKOUT	CLKOUT clock selection
SYSTICK	SYSTICK clock selection
SCGSCS	SCG SCS clock selection
MAX	MAX clock selection

SircTrimMode

enum struct chip::clock::SircTrimMode : unsigned int

strong

列舉值
NON_UPDATE	Trim enable but not enable trim value update. In this mode, the trim value is fixed to the initialized value which is defined by trimCoar and trimFine in configure structure sirc_trim_config_t.
UPDATE	Trim enable and trim value update enable. In this mode, the trim value is auto update.

SircTrimSource

enum struct chip::clock::SircTrimSource : unsigned int

strong

列舉值
NO_TRIM_SRC	No external tirm source.
SYS_OSC	System OSC.