lpuart/Shift.h

 
#ifndef CHIP_09A56C9D_FEFE_4373_8735_91F9DED00F9D
#define CHIP_09A56C9D_FEFE_4373_8735_91F9DED00F9D
 
/* ***************************************************************************************
 * Include
 */
 
//----------------------------------------------------------------------------------------
#include "mframe.h"
 
//----------------------------------------------------------------------------------------
 
/* ***************************************************************************************
 * Namespace
 */
namespace chip::lpuart {
  enum struct Shift : unsigned int;
 
  constexpr unsigned int operator+(Shift e) {
    return static_cast<unsigned int>(e);
  }
}  // namespace chip::lpuart
 
/* ***************************************************************************************
 * Class/Interface/Struct/Enum
 */
enum struct chip::lpuart::Shift : unsigned int {
  VERID_FEATURE = 0U,
 
  VERID_MINOR = 16U,
 
  VERID_MAJOR = 24U,
 
  PARAM_TXFIFO = 0U,
 
  PARAM_RXFIFO = 8U,
 
  GLOBAL_RST = 1U,
 
  PINCFG_TRGSEL = 0U,
 
  BAUD_SBR = 0U,
 
  BAUD_SBNS = 13U,
 
  BAUD_RXEDGIE = 14U,
 
  BAUD_LBKDIE = 15U,
 
  BAUD_RESYNCDIS = 16U,
 
  BAUD_BOTHEDGE = 17U,
 
  BAUD_MATCFG = 18U,
 
  BAUD_RIDMAE = 20U,
 
  BAUD_RDMAE = 21U,
 
  BAUD_TDMAE = 23U,
 
  BAUD_OSR = 24U,
 
  BAUD_M10 = 29U,
 
  BAUD_MAEN2 = 30U,
 
  BAUD_MAEN1 = 31U,
 
  STAT_LBKFE = 0U,
 
  STAT_AME = 1U,
 
  STAT_MA2F = 14U,
 
  STAT_MA1F = 15U,
 
  STAT_PF = 16U,
 
  STAT_FE = 17U,
 
  STAT_NF = 18U,
 
  STAT_OR = 19U,
 
  STAT_IDLE = 20U,
 
  STAT_RDRF = 21U,
 
  STAT_TC = 22U,
 
  STAT_TDRE = 23U,
 
  STAT_RAF = 24U,
 
  STAT_LBKDE = 25U,
 
  STAT_BRK13 = 26U,
 
  STAT_RWUID = 27U,
 
  STAT_RXINV = 28U,
 
  STAT_MSBF = 29U,
 
  STAT_RXEDGIF = 30U,
 
  STAT_LBKDIF = 31U,
 
  CTRL_PT = 0U,
 
  CTRL_PE = 1U,
 
  CTRL_ILT = 2U,
 
  CTRL_WAKE = 3U,
 
  CTRL_M = 4U,
 
  CTRL_RSRC = 5U,
 
  CTRL_DOZEEN = 6U,
 
  CTRL_LOOPS = 7U,
 
  CTRL_IDLECFG = 8U,
 
  CTRL_M7 = 11U,
 
  CTRL_MA2IE = 14U,
 
  CTRL_MA1IE = 15U,
 
  CTRL_SBK = 16U,
 
  CTRL_RWU = 17U,
 
  CTRL_RE = 18U,
 
  CTRL_TE = 19U,
 
  CTRL_ILIE = 20U,
 
  CTRL_RIE = 21U,
 
  CTRL_TCIE = 22U,
 
  CTRL_TIE = 23U,
 
  CTRL_PEIE = 24U,
 
  CTRL_FEIE = 25U,
 
  CTRL_NEIE = 26U,
 
  CTRL_ORIE = 27U,
 
  CTRL_TXINV = 28U,
 
  CTRL_TXDIR = 29U,
 
  CTRL_R9T8 = 30U,
 
  CTRL_R8T9 = 31U,
 
  DATA_R0T0 = 0U,
 
  DATA_R1T1 = 1U,
 
  DATA_R2T2 = 2U,
 
  DATA_R3T3 = 3U,
 
  DATA_R4T4 = 4U,
 
  DATA_R5T5 = 5U,
 
  DATA_R6T6 = 6U,
 
  DATA_R7T7 = 7U,
 
  DATA_R8T8 = 8U,
 
  DATA_R9T9 = 9U,
 
  DATA_LINBRK = 10U,
 
  DATA_IDLINE = 11U,
 
  DATA_RXEMPT = 12U,
 
  DATA_FRETSC = 13U,
 
  DATA_PARITYE = 14U,
 
  DATA_NOISY = 15U,
 
  MATCH_MA1 = 0U,
 
  MATCH_MA2 = 16U,
 
  MODIR_TXCTSE = 0U,
 
  MODIR_TXRTSE = 1U,
 
  MODIR_TXRTSPOL = 2U,
 
  MODIR_RXRTSE = 3U,
 
  MODIR_TXCTSC = 4U,
 
  MODIR_TXCTSSRC = 5U,
 
  MODIR_RTSWATER = 8U,
 
  MODIR_TNP = 16U,
 
  MODIR_IREN = 18U,
 
  FIFO_RXFIFOSIZE = 0U,
 
  FIFO_RXFE = 3U,
 
  FIFO_TXFIFOSIZE = 4U,
 
  FIFO_TXFE = 7U,
 
  FIFO_RXUFE = 8U,
 
  FIFO_TXOFE = 9U,
 
  FIFO_RXIDEN = 10U,
 
  FIFO_RXFLUSH = 14U,
 
  FIFO_TXFLUSH = 15U,
 
  FIFO_RXUF = 16U,
 
  FIFO_TXOF = 17U,
 
  FIFO_RXEMPT = 22U,
 
  FIFO_TXEMPT = 23U,
 
  WATER_TXWATER = 0U,
 
  WATER_TXCOUNT = 8U,
 
  WATER_RXWATER = 16U,
 
  WATER_RXCOUNT = 24U,
 
  DATARO_DATA = 0U
 
};
 
/* ***************************************************************************************
 * End of file
 */
 
#endif /* CHIP_09A56C9D_FEFE_4373_8735_91F9DED00F9D */