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mcxa153::chip::fmu 命名空間(Namespace)參考文件

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class  FMU
 快閃記憶體管理單元(Flash Memory Unit) Flash Memory Unit 更多...
 
struct  Register
 

列舉型態

enum struct  Mask : unsigned int {
  FSTAT_FAIL = 0x1U , FSTAT_CMDABT = 0x4U , FSTAT_PVIOL = 0x10U , FSTAT_ACCERR = 0x20U ,
  FSTAT_CWSABT = 0x40U , FSTAT_CCIF = 0x80U , FSTAT_CMDPRT = 0x300U , FSTAT_CMDP = 0x800U ,
  FSTAT_CMDDID = 0xF000U , FSTAT_DFDIF = 0x10000U , FSTAT_SALV_USED = 0x20000U , FSTAT_PEWEN = 0x3000000U ,
  FSTAT_PERDY = 0x80000000U , FCNFG_CCIE = 0x80U , FCNFG_ERSREQ = 0x100U , FCNFG_DFDIE = 0x10000U ,
  FCNFG_ERSIEN0 = 0xF000000U , FCNFG_ERSIEN1 = 0xF0000000U , FCTRL_RWSC = 0xFU , FCTRL_LSACTIVE = 0x100U ,
  FCTRL_FDFD = 0x10000U , FCTRL_ABTREQ = 0x1000000U , FTEST_TMECTL = 0x1U , FTEST_TMEWR = 0x2U ,
  FTEST_TME = 0x4U , FTEST_TMODE = 0x8U , FTEST_TMELOCK = 0x10U , FCCOB0_CMDCODE = 0xFFU ,
  FCCOB1_CMDOPT = 0xFFU , FCCOB2_CMDADDR = 0xFFFFFFFFU , FCCOB3_CMDADDRE = 0xFFFFFFFFU , FCCOB4_CMDDATA0 = 0xFFFFFFFFU ,
  FCCOB5_CMDDATA1 = 0xFFFFFFFFU , FCCOB6_CMDDATA2 = 0xFFFFFFFFU , FCCOB7_CMDDATA3 = 0xFFFFFFFFU , RESET_STATUS_ARY_TRIM_DONE = 0x1U ,
  RESET_STATUS_FMU_PARM_EN = 0x2U , RESET_STATUS_FMU_PARM_DONE = 0x4U , RESET_STATUS_SOC_TRIM_EN = 0x8U , RESET_STATUS_SOC_TRIM_ECC = 0x10U ,
  RESET_STATUS_SOC_TRIM_DONE = 0x20U , RESET_STATUS_RPR_DONE = 0x40U , RESET_STATUS_INIT_DONE = 0x80U , RESET_STATUS_RST_SF_ERR = 0x100U ,
  RESET_STATUS_RST_DF_ERR = 0x200U , RESET_STATUS_SOC_TRIM_DF_ERR = 0x3FC00U , RESET_STATUS_RST_PATCH_LD = 0x40000U , RESET_STATUS_RECALL_DATA_MISMATCH = 0x80000U ,
  MCTL_COREHLD = 0x1U , MCTL_LSACT_EN = 0x4U , MCTL_LSACTWREN = 0x8U , MCTL_MASTER_REPAIR_EN = 0x10U ,
  MCTL_RFCMDEN = 0x20U , MCTL_CWSABTEN = 0x40U , MCTL_MRGRDDIS = 0x80U , MCTL_MRGRD0 = 0xF00U ,
  MCTL_MRGRD1 = 0xF000U , MCTL_ERSAACK = 0x10000U , MCTL_SCAN_OBS = 0x80000U , MCTL_BIST_CTL = 0x100000U ,
  MCTL_SMWR_CTL = 0x200000U , MCTL_SALV_DIS = 0x1000000U , MCTL_SOC_ECC_CTL = 0x2000000U , MCTL_FMU_ECC_CTL = 0x4000000U ,
  MCTL_BIST_PWR_DIS = 0x20000000U , MCTL_OSC_H = 0x80000000U , BSEL_GEN_SBSEL_GEN = 0x3U , BSEL_GEN_MBSEL_GEN = 0x300U ,
  PWR_OPT_PD_CDIV = 0xFFU , PWR_OPT_SLM_COUNT = 0x3FF0000U , PWR_OPT_PD_TIMER_EN = 0x80000000U , CMD_CHECK_ALIGNFAIL_PHR = 0x1U ,
  CMD_CHECK_ALIGNFAIL_PG = 0x2U , CMD_CHECK_ALIGNFAIL_SCR = 0x4U , CMD_CHECK_ALIGNFAIL_BLK = 0x8U , CMD_CHECK_ADDR_FAIL = 0x10U ,
  CMD_CHECK_IFR_CMD = 0x20U , CMD_CHECK_ALL_CMD = 0x40U , CMD_CHECK_RANGE_FAIL = 0x80U , CMD_CHECK_SCR_ALIGN_CHK = 0x100U ,
  CMD_CHECK_OPTION_FAIL = 0x200U , CMD_CHECK_ILLEGAL_CMD = 0x400U , BSEL_SBSEL = 0x3U , BSEL_MBSEL = 0x300U ,
  MSIZE_MAXADDR0 = 0xFFU , FLASH_RD_ADD_FLASH_RD_ADD = 0xFFFFFFFFU , FLASH_STOP_ADD_FLASH_STOP_ADD = 0xFFFFFFFFU , FLASH_RD_CTRL_FLASH_RD = 0x1U ,
  FLASH_RD_CTRL_WIDE_LOAD = 0x2U , FLASH_RD_CTRL_SINGLE_RD = 0x4U , MM_ADDR_MM_ADDR = 0xFFFFFFFFU , MM_WDATA_MM_WDATA = 0xFFFFFFFFU ,
  MM_CTL_MM_SEL = 0x1U , MM_CTL_MM_RD = 0x2U , MM_CTL_BIST_ON = 0x4U , MM_CTL_FORCE_SW_CLK = 0x8U ,
  UINT_CTL_SET_FAIL = 0x1U , UINT_CTL_DBERR = 0x2U , RD_DATA0_RD_DATA0 = 0xFFFFFFFFU , RD_DATA1_RD_DATA1 = 0xFFFFFFFFU ,
  RD_DATA2_RD_DATA2 = 0xFFFFFFFFU , RD_DATA3_RD_DATA3 = 0xFFFFFFFFU , PARITY_PARITY = 0x1FFU , RD_PATH_CTRL_STATUS_RD_CAPT = 0xFFU ,
  RD_PATH_CTRL_STATUS_SE_SIZE = 0xFF00U , RD_PATH_CTRL_STATUS_ECC_ENABLEB = 0x10000U , RD_PATH_CTRL_STATUS_MISR_EN = 0x20000U , RD_PATH_CTRL_STATUS_CPY_PAR_EN = 0x40000U ,
  RD_PATH_CTRL_STATUS_BIST_MUX_TO_SMW = 0x80000U , RD_PATH_CTRL_STATUS_AD_SET = 0xF00000U , RD_PATH_CTRL_STATUS_WR_PATH_EN = 0x1000000U , RD_PATH_CTRL_STATUS_WR_PATH_ECC_EN = 0x2000000U ,
  RD_PATH_CTRL_STATUS_DBERR_REG = 0x4000000U , RD_PATH_CTRL_STATUS_SBERR_REG = 0x8000000U , RD_PATH_CTRL_STATUS_CPY_PHRASE_EN = 0x10000000U , RD_PATH_CTRL_STATUS_SMW_ARRAY1_SMW0_SEL = 0x20000000U ,
  RD_PATH_CTRL_STATUS_BIST_ECC_EN = 0x40000000U , RD_PATH_CTRL_STATUS_LAST_READ = 0x80000000U , SMW_DIN0_SMW_DIN0 = 0xFFFFFFFFU , SMW_DIN1_SMW_DIN1 = 0xFFFFFFFFU ,
  SMW_DIN2_SMW_DIN2 = 0xFFFFFFFFU , SMW_DIN3_SMW_DIN3 = 0xFFFFFFFFU , SMW_ADDR_SMW_ADDR = 0xFFFFFFFFU , SMW_CMD_WAIT_CMD = 0x7U ,
  SMW_CMD_WAIT_WAIT_EN = 0x8U , SMW_CMD_WAIT_WAIT_AUTO_SET = 0x10U , SMW_STATUS_SMW_ERR = 0x1U , SMW_STATUS_SMW_BUSY = 0x2U ,
  SMW_STATUS_BIST_BUSY = 0x4U , SOCTRIM0_0_TRIM0_0 = 0xFFFFFFFFU , SOCTRIM0_1_TRIM0_1 = 0xFFFFFFFFU , SOCTRIM0_2_TRIM0_2 = 0xFFFFFFFFU ,
  SOCTRIM0_3_TRIM0_3 = 0xFFFFFFFFU , SOCTRIM1_0_TRIM1_0 = 0xFFFFFFFFU , SOCTRIM1_1_TRIM1_1 = 0xFFFFFFFFU , SOCTRIM1_2_TRIM1_2 = 0xFFFFFFFFU ,
  SOCTRIM1_3_TRIM1_3 = 0xFFFFFFFFU , SOCTRIM2_0_TRIM2_0 = 0xFFFFFFFFU , SOCTRIM2_1_TRIM2_1 = 0xFFFFFFFFU , SOCTRIM2_2_TRIM2_2 = 0xFFFFFFFFU ,
  SOCTRIM2_3_TRIM2_3 = 0xFFFFFFFFU , SOCTRIM3_0_TRIM3_0 = 0xFFFFFFFFU , SOCTRIM3_1_TRIM3_1 = 0xFFFFFFFFU , SOCTRIM3_2_TRIM3_2 = 0xFFFFFFFFU ,
  SOCTRIM3_3_TRIM3_3 = 0xFFFFFFFFU , SOCTRIM4_0_TRIM4_0 = 0xFFFFFFFFU , SOCTRIM4_1_TRIM4_1 = 0xFFFFFFFFU , SOCTRIM4_2_TRIM4_2 = 0xFFFFFFFFU ,
  SOCTRIM4_3_TRIM4_3 = 0xFFFFFFFFU , SOCTRIM5_0_TRIM5_0 = 0xFFFFFFFFU , SOCTRIM5_1_TRIM5_1 = 0xFFFFFFFFU , SOCTRIM5_2_TRIM5_2 = 0xFFFFFFFFU ,
  SOCTRIM5_3_TRIM5_3 = 0xFFFFFFFFU , SOCTRIM6_0_TRIM6_0 = 0xFFFFFFFFU , SOCTRIM6_1_TRIM6_1 = 0xFFFFFFFFU , SOCTRIM6_2_TRIM6_2 = 0xFFFFFFFFU ,
  SOCTRIM6_3_TRIM6_3 = 0xFFFFFFFFU , SOCTRIM7_0_TRIM7_0 = 0xFFFFFFFFU , SOCTRIM7_1_TRIM7_1 = 0xFFFFFFFFU , SOCTRIM7_2_TRIM7_2 = 0xFFFFFFFFU ,
  SOCTRIM7_3_TRIM7_3 = 0xFFFFFFFFU , R_IP_CONFIG_IPSEL0 = 0x3U , R_IP_CONFIG_IPSEL1 = 0xCU , R_IP_CONFIG_BIST_CDIVL = 0xFF0U ,
  R_IP_CONFIG_CDIVS = 0x7000U , R_IP_CONFIG_BIST_TVFY = 0xF8000U , R_IP_CONFIG_TSTCTL = 0x300000U , R_IP_CONFIG_DBGCTL = 0x400000U ,
  R_IP_CONFIG_BIST_CLK_SEL = 0x800000U , R_IP_CONFIG_SMWTST = 0x3000000U , R_IP_CONFIG_ECCEN = 0x4000000U , R_TESTCODE_TESTCODE = 0x3FU ,
  R_DFT_CTRL_DFT_XADR = 0xFU , R_DFT_CTRL_DFT_YADR = 0xF0U , R_DFT_CTRL_DFT_DATA = 0xF00U , R_DFT_CTRL_CMP_MASK = 0x3000U ,
  R_DFT_CTRL_DFT_DATA_SRC = 0x4000U , R_ADR_CTRL_GRPSEL = 0xFU , R_ADR_CTRL_XADR = 0xFFF0U , R_ADR_CTRL_YADR = 0x1F0000U ,
  R_ADR_CTRL_PROG_ATTR = 0xE00000U , R_DATA_CTRL0_DATA0 = 0xFFFFFFFFU , R_PIN_CTRL_MAS1 = 0x1U , R_PIN_CTRL_IFREN = 0x2U ,
  R_PIN_CTRL_IFREN1 = 0x4U , R_PIN_CTRL_REDEN = 0x8U , R_PIN_CTRL_LVE = 0x10U , R_PIN_CTRL_PV = 0x20U ,
  R_PIN_CTRL_EV = 0x40U , R_PIN_CTRL_WIPGM = 0x180U , R_PIN_CTRL_WHV = 0x1E00U , R_PIN_CTRL_WMV = 0xE000U ,
  R_PIN_CTRL_XE = 0x10000U , R_PIN_CTRL_YE = 0x20000U , R_PIN_CTRL_SE = 0x40000U , R_PIN_CTRL_ERASE = 0x80000U ,
  R_PIN_CTRL_PROG = 0x100000U , R_PIN_CTRL_NVSTR = 0x200000U , R_PIN_CTRL_SLM = 0x400000U , R_PIN_CTRL_RECALL = 0x800000U ,
  R_PIN_CTRL_HEM = 0x1000000U , R_CNT_LOOP_CTRL_LOOPCNT = 0xFFFU , R_CNT_LOOP_CTRL_LOOPOPT = 0x7000U , R_CNT_LOOP_CTRL_LOOPUNIT = 0x38000U ,
  R_CNT_LOOP_CTRL_LOOPDLY = 0x1FC0000U , R_TIMER_CTRL_TNVSUNIT = 0x7U , R_TIMER_CTRL_TNVSDLY = 0x78U , R_TIMER_CTRL_TNVHUNIT = 0x380U ,
  R_TIMER_CTRL_TNVHDLY = 0x3C00U , R_TIMER_CTRL_TPGSUNIT = 0x1C000U , R_TIMER_CTRL_TPGSDLY = 0x1E0000U , R_TIMER_CTRL_TRCVUNIT = 0xE00000U ,
  R_TIMER_CTRL_TRCVDLY = 0xF000000U , R_TIMER_CTRL_TLVSUNIT = 0x70000000U , R_TIMER_CTRL_TLVSDLY_L = 0x80000000U , R_TEST_CTRL_BUSY = 0x1U ,
  R_TEST_CTRL_DEBUG = 0x2U , R_TEST_CTRL_STATUS0 = 0x4U , R_TEST_CTRL_STATUS1 = 0x8U , R_TEST_CTRL_DEBUGRUN = 0x10U ,
  R_TEST_CTRL_STARTRUN = 0x20U , R_TEST_CTRL_CMDINDEX = 0xFFC0U , R_TEST_CTRL_DISABLE_IP1 = 0x10000U , R_ABORT_LOOP_ABORT_LOOP = 0x1U ,
  R_ADR_QUERY_YADRFAIL = 0x1FU , R_ADR_QUERY_XADRFAIL = 0x1FFE0U , R_DOUT_QUERY0_DOUTFAIL = 0xFFFFFFFFU , R_SMW_QUERY_SMWLOOP = 0x3FFU ,
  R_SMW_QUERY_SMWLAST = 0x7FC00U , R_SMW_SETTING0_SMWPARM0 = 0x7FFFFFFFU , R_SMW_SETTING1_SMWPARM1 = 0xFFFFFFFU , R_SMP_WHV0_SMPWHV0 = 0xFFFFFFFFU ,
  R_SMP_WHV1_SMPWHV1 = 0xFFFFFFFFU , R_SME_WHV0_SMEWHV0 = 0xFFFFFFFFU , R_SME_WHV1_SMEWHV1 = 0xFFFFFFFFU , R_SMW_SETTING2_SMWPARM2 = 0x1FFFFFFFU ,
  R_D_MISR0_DATASIG0 = 0xFFFFFFFFU , R_A_MISR0_ADRSIG0 = 0xFFFFFFFFU , R_C_MISR0_CTRLSIG0 = 0xFFFFFFFFU , R_SMW_SETTING3_SMWPARM3 = 0x1FFFFU ,
  R_DATA_CTRL1_DATA1 = 0xFFFFFFFFU , R_DATA_CTRL2_DATA2 = 0xFFFFFFFFU , R_DATA_CTRL3_DATA3 = 0xFFFFFFFFU , R_REPAIR0_0_RDIS0_0 = 0x1U ,
  R_REPAIR0_0_RADR0_0 = 0x1FEU , R_REPAIR0_1_RDIS0_1 = 0x1U , R_REPAIR0_1_RADR0_1 = 0x1FEU , R_REPAIR1_0_RDIS1_0 = 0x1U ,
  R_REPAIR1_0_RADR1_0 = 0x1FEU , R_REPAIR1_1_RDIS1_1 = 0x1U , R_REPAIR1_1_RADR1_1 = 0x1FEU , R_DATA_CTRL0_EX_DATA0X = 0x7U ,
  R_TIMER_CTRL_EX_TLVSDLY_H = 0x7U , R_DOUT_QUERY1_DOUT = 0x7U , R_D_MISR1_DATASIG1 = 0xFFU , R_A_MISR1_ADRSIG1 = 0xFFU ,
  R_C_MISR1_CTRLSIG1 = 0xFFU , R_DATA_CTRL1_EX_DATA1X = 0x7U , R_DATA_CTRL2_EX_DATA2X = 0x7U , R_DATA_CTRL3_EX_DATA3X = 0x7U ,
  SMW_TIMER_OPTION_SMW_CDIVL = 0xFFU , SMW_TIMER_OPTION_SMW_TVFY = 0x1F00U , SMW_SETTING_OPTION0_MV_INIT = 0x1C000U , SMW_SETTING_OPTION0_MV_END = 0xE0000U ,
  SMW_SETTING_OPTION0_MV_MISC = 0xF00000U , SMW_SETTING_OPTION0_IPGM_INIT = 0x3000000U , SMW_SETTING_OPTION0_IPGM_END = 0xC000000U , SMW_SETTING_OPTION0_IPGM_MISC = 0x70000000U ,
  SMW_SETTING_OPTION2_THVS_CTRL = 0x7U , SMW_SETTING_OPTION2_TRCV_CTRL = 0x38U , SMW_SETTING_OPTION2_XTRA_ERS = 0xC0U , SMW_SETTING_OPTION2_XTRA_PGM = 0x300U ,
  SMW_SETTING_OPTION2_WHV_CNTR = 0x3FC00U , SMW_SETTING_OPTION2_POST_TERS = 0x1C0000U , SMW_SETTING_OPTION2_POST_TPGM = 0x600000U , SMW_SETTING_OPTION2_VFY_OPT = 0x1800000U ,
  SMW_SETTING_OPTION2_TPGM_OPT = 0x6000000U , SMW_SETTING_OPTION2_MASK0_OPT = 0x8000000U , SMW_SETTING_OPTION2_DIS_PRER = 0x10000000U , SMW_SETTING_OPTION3_HEM_WHV_CNTR = 0xFFU ,
  SMW_SETTING_OPTION3_HEM_MAX_ERS = 0x1FF00U , SMW_SMP_WHV_OPTION0_SMP_WHV_OPT0 = 0xFFFFFFFFU , SMW_SME_WHV_OPTION0_SME_WHV_OPT0 = 0xFFFFFFFFU , SMW_SETTING_OPTION1_TERS_CTRL0 = 0x7U ,
  SMW_SETTING_OPTION1_TPGM_CTRL = 0x18U , SMW_SETTING_OPTION1_TNVS_CTRL = 0xE0U , SMW_SETTING_OPTION1_TNVH_CTRL = 0x700U , SMW_SETTING_OPTION1_TPGS_CTRL = 0x3800U ,
  SMW_SETTING_OPTION1_MAX_ERASE = 0x7FC000U , SMW_SETTING_OPTION1_MAX_PROG = 0xF800000U , SMW_SMP_WHV_OPTION1_SMP_WHV_OPT1 = 0xFFFFFFFFU , SMW_SME_WHV_OPTION1_SME_WHV_OPT1 = 0xFFFFFFFFU ,
  REPAIR0_0_RDIS0_0 = 0x1U , REPAIR0_0_RADR0_0 = 0x1FEU , REPAIR0_1_RDIS0_1 = 0x1U , REPAIR0_1_RADR0_1 = 0x1FEU ,
  REPAIR1_0_RDIS1_0 = 0x1U , REPAIR1_0_RADR1_0 = 0x1FEU , REPAIR1_1_RDIS1_1 = 0x1U , REPAIR1_1_RADR1_1 = 0x1FEU ,
  SMW_HB_SIGNALS_SMW_ARRAY = 0x7U , SMW_HB_SIGNALS_USER_IFREN1 = 0x8U , SMW_HB_SIGNALS_USER_PV = 0x10U , SMW_HB_SIGNALS_USER_EV = 0x20U ,
  SMW_HB_SIGNALS_USER_IFREN = 0x40U , SMW_HB_SIGNALS_USER_REDEN = 0x80U , SMW_HB_SIGNALS_USER_HEM = 0x100U , BIST_DUMP_CTRL_BIST_DONE = 0x10000U ,
  BIST_DUMP_CTRL_BIST_FAIL = 0x20000U , BIST_DUMP_CTRL_DATADUMP = 0x40000U , BIST_DUMP_CTRL_DATADUMP_TRIG = 0x80000U , BIST_DUMP_CTRL_DATADUMP_PATT = 0x300000U ,
  BIST_DUMP_CTRL_DATADUMP_MRGEN = 0x400000U , BIST_DUMP_CTRL_DATADUMP_MRGTYPE = 0x800000U , ATX_PIN_CTRL_TM_TO_ATX = 0xFFU , FAILCNT_FAILCNT = 0xFFFFFFFFU ,
  PGM_PULSE_CNT0_PGM_CNT0 = 0xFFFFFFFFU , PGM_PULSE_CNT1_PGM_CNT1 = 0xFFFFFFFFU , ERS_PULSE_CNT_ERS_CNT0 = 0xFFFFU , ERS_PULSE_CNT_ERS_CNT1 = 0xFFFF0000U ,
  MAX_PULSE_CNT_LAST_PCNT = 0x1FFU , MAX_PULSE_CNT_MAX_ERS_CNT = 0x1FF0000U , MAX_PULSE_CNT_MAX_PGM_CNT = 0xF8000000U , PORT_CTRL_BDONE_SEL = 0x3U ,
  PORT_CTRL_BSDO_SEL = 0xCU
}
 Flash Memory Unit Register Mask 快閃記憶體單元暫存器遮罩 更多...
 
enum struct  Shift : unsigned int {
  FSTAT_FAIL = 0U , FSTAT_CMDABT = 2U , FSTAT_PVIOL = 4U , FSTAT_ACCERR = 5U ,
  FSTAT_CWSABT = 6U , FSTAT_CCIF = 7U , FSTAT_CMDPRT = 8U , FSTAT_CMDP = 11U ,
  FSTAT_CMDDID = 12U , FSTAT_DFDIF = 16U , FSTAT_SALV_USED = 17U , FSTAT_PEWEN = 24U ,
  FSTAT_PERDY = 31U , FCNFG_CCIE = 7U , FCNFG_ERSREQ = 8U , FCNFG_DFDIE = 16U ,
  FCNFG_ERSIEN0 = 24U , FCNFG_ERSIEN1 = 28U , FCTRL_RWSC = 0U , FCTRL_LSACTIVE = 8U ,
  FCTRL_FDFD = 16U , FCTRL_ABTREQ = 24U , FTEST_TMECTL = 0U , FTEST_TMEWR = 1U ,
  FTEST_TME = 2U , FTEST_TMODE = 3U , FTEST_TMELOCK = 4U , FCCOB0_CMDCODE = 0U ,
  FCCOB1_CMDOPT = 0U , FCCOB2_CMDADDR = 0U , FCCOB3_CMDADDRE = 0U , FCCOB4_CMDDATA0 = 0U ,
  FCCOB5_CMDDATA1 = 0U , FCCOB6_CMDDATA2 = 0U , FCCOB7_CMDDATA3 = 0U , RESET_STATUS_ARY_TRIM_DONE = 0U ,
  RESET_STATUS_FMU_PARM_EN = 1U , RESET_STATUS_FMU_PARM_DONE = 2U , RESET_STATUS_SOC_TRIM_EN = 3U , RESET_STATUS_SOC_TRIM_ECC = 4U ,
  RESET_STATUS_SOC_TRIM_DONE = 5U , RESET_STATUS_RPR_DONE = 6U , RESET_STATUS_INIT_DONE = 7U , RESET_STATUS_RST_SF_ERR = 8U ,
  RESET_STATUS_RST_DF_ERR = 9U , RESET_STATUS_SOC_TRIM_DF_ERR = 10U , RESET_STATUS_RST_PATCH_LD = 18U , RESET_STATUS_RECALL_DATA_MISMATCH = 19U ,
  MCTL_COREHLD = 0U , MCTL_LSACT_EN = 2U , MCTL_LSACTWREN = 3U , MCTL_MASTER_REPAIR_EN = 4U ,
  MCTL_RFCMDEN = 5U , MCTL_CWSABTEN = 6U , MCTL_MRGRDDIS = 7U , MCTL_MRGRD0 = 8U ,
  MCTL_MRGRD1 = 12U , MCTL_ERSAACK = 16U , MCTL_SCAN_OBS = 19U , MCTL_BIST_CTL = 20U ,
  MCTL_SMWR_CTL = 21U , MCTL_SALV_DIS = 24U , MCTL_SOC_ECC_CTL = 25U , MCTL_FMU_ECC_CTL = 26U ,
  MCTL_BIST_PWR_DIS = 29U , MCTL_OSC_H = 31U , BSEL_GEN_SBSEL_GEN = 0U , BSEL_GEN_MBSEL_GEN = 8U ,
  PWR_OPT_PD_CDIV = 0U , PWR_OPT_SLM_COUNT = 16U , PWR_OPT_PD_TIMER_EN = 31U , CMD_CHECK_ALIGNFAIL_PHR = 0U ,
  CMD_CHECK_ALIGNFAIL_PG = 1U , CMD_CHECK_ALIGNFAIL_SCR = 2U , CMD_CHECK_ALIGNFAIL_BLK = 3U , CMD_CHECK_ADDR_FAIL = 4U ,
  CMD_CHECK_IFR_CMD = 5U , CMD_CHECK_ALL_CMD = 6U , CMD_CHECK_RANGE_FAIL = 7U , CMD_CHECK_SCR_ALIGN_CHK = 8U ,
  CMD_CHECK_OPTION_FAIL = 9U , CMD_CHECK_ILLEGAL_CMD = 10U , BSEL_SBSEL = 0U , BSEL_MBSEL = 8U ,
  MSIZE_MAXADDR0 = 0U , FLASH_RD_ADD_FLASH_RD_ADD = 0U , FLASH_STOP_ADD_FLASH_STOP_ADD = 0U , FLASH_RD_CTRL_FLASH_RD = 0U ,
  FLASH_RD_CTRL_WIDE_LOAD = 1U , FLASH_RD_CTRL_SINGLE_RD = 2U , MM_ADDR_MM_ADDR = 0U , MM_WDATA_MM_WDATA = 0U ,
  MM_CTL_MM_SEL = 0U , MM_CTL_MM_RD = 1U , MM_CTL_BIST_ON = 2U , MM_CTL_FORCE_SW_CLK = 3U ,
  UINT_CTL_SET_FAIL = 0U , UINT_CTL_DBERR = 1U , RD_DATA0_RD_DATA0 = 0U , RD_DATA1_RD_DATA1 = 0U ,
  RD_DATA2_RD_DATA2 = 0U , RD_DATA3_RD_DATA3 = 0U , PARITY_PARITY = 0U , RD_PATH_CTRL_STATUS_RD_CAPT = 0U ,
  RD_PATH_CTRL_STATUS_SE_SIZE = 8U , RD_PATH_CTRL_STATUS_ECC_ENABLEB = 16U , RD_PATH_CTRL_STATUS_MISR_EN = 17U , RD_PATH_CTRL_STATUS_CPY_PAR_EN = 18U ,
  RD_PATH_CTRL_STATUS_BIST_MUX_TO_SMW = 19U , RD_PATH_CTRL_STATUS_AD_SET = 20U , RD_PATH_CTRL_STATUS_WR_PATH_EN = 24U , RD_PATH_CTRL_STATUS_WR_PATH_ECC_EN = 25U ,
  RD_PATH_CTRL_STATUS_DBERR_REG = 26U , RD_PATH_CTRL_STATUS_SBERR_REG = 27U , RD_PATH_CTRL_STATUS_CPY_PHRASE_EN = 28U , RD_PATH_CTRL_STATUS_SMW_ARRAY1_SMW0_SEL = 29U ,
  RD_PATH_CTRL_STATUS_BIST_ECC_EN = 30U , RD_PATH_CTRL_STATUS_LAST_READ = 31U , SMW_DIN0_SMW_DIN0 = 0U , SMW_DIN1_SMW_DIN1 = 0U ,
  SMW_DIN2_SMW_DIN2 = 0U , SMW_DIN3_SMW_DIN3 = 0U , SMW_ADDR_SMW_ADDR = 0U , SMW_CMD_WAIT_CMD = 0U ,
  SMW_CMD_WAIT_WAIT_EN = 3U , SMW_CMD_WAIT_WAIT_AUTO_SET = 4U , SMW_STATUS_SMW_ERR = 0U , SMW_STATUS_SMW_BUSY = 1U ,
  SMW_STATUS_BIST_BUSY = 2U , SOCTRIM0_0_TRIM0_0 = 0U , SOCTRIM0_1_TRIM0_1 = 0U , SOCTRIM0_2_TRIM0_2 = 0U ,
  SOCTRIM0_3_TRIM0_3 = 0U , SOCTRIM1_0_TRIM1_0 = 0U , SOCTRIM1_1_TRIM1_1 = 0U , SOCTRIM1_2_TRIM1_2 = 0U ,
  SOCTRIM1_3_TRIM1_3 = 0U , SOCTRIM2_0_TRIM2_0 = 0U , SOCTRIM2_1_TRIM2_1 = 0U , SOCTRIM2_2_TRIM2_2 = 0U ,
  SOCTRIM2_3_TRIM2_3 = 0U , SOCTRIM3_0_TRIM3_0 = 0U , SOCTRIM3_1_TRIM3_1 = 0U , SOCTRIM3_2_TRIM3_2 = 0U ,
  SOCTRIM3_3_TRIM3_3 = 0U , SOCTRIM4_0_TRIM4_0 = 0U , SOCTRIM4_1_TRIM4_1 = 0U , SOCTRIM4_2_TRIM4_2 = 0U ,
  SOCTRIM4_3_TRIM4_3 = 0U , SOCTRIM5_0_TRIM5_0 = 0U , SOCTRIM5_1_TRIM5_1 = 0U , SOCTRIM5_2_TRIM5_2 = 0U ,
  SOCTRIM5_3_TRIM5_3 = 0U , SOCTRIM6_0_TRIM6_0 = 0U , SOCTRIM6_1_TRIM6_1 = 0U , SOCTRIM6_2_TRIM6_2 = 0U ,
  SOCTRIM6_3_TRIM6_3 = 0U , SOCTRIM7_0_TRIM7_0 = 0U , SOCTRIM7_1_TRIM7_1 = 0U , SOCTRIM7_2_TRIM7_2 = 0U ,
  SOCTRIM7_3_TRIM7_3 = 0U , R_IP_CONFIG_IPSEL0 = 0U , R_IP_CONFIG_IPSEL1 = 2U , R_IP_CONFIG_BIST_CDIVL = 4U ,
  R_IP_CONFIG_CDIVS = 12U , R_IP_CONFIG_BIST_TVFY = 15U , R_IP_CONFIG_TSTCTL = 20U , R_IP_CONFIG_DBGCTL = 22U ,
  R_IP_CONFIG_BIST_CLK_SEL = 23U , R_IP_CONFIG_SMWTST = 24U , R_IP_CONFIG_ECCEN = 26U , R_TESTCODE_TESTCODE = 0U ,
  R_DFT_CTRL_DFT_XADR = 0U , R_DFT_CTRL_DFT_YADR = 4U , R_DFT_CTRL_DFT_DATA = 8U , R_DFT_CTRL_CMP_MASK = 12U ,
  R_DFT_CTRL_DFT_DATA_SRC = 14U , R_ADR_CTRL_GRPSEL = 0U , R_ADR_CTRL_XADR = 4U , R_ADR_CTRL_YADR = 16U ,
  R_ADR_CTRL_PROG_ATTR = 21U , R_DATA_CTRL0_DATA0 = 0U , R_PIN_CTRL_MAS1 = 0U , R_PIN_CTRL_IFREN = 1U ,
  R_PIN_CTRL_IFREN1 = 2U , R_PIN_CTRL_REDEN = 3U , R_PIN_CTRL_LVE = 4U , R_PIN_CTRL_PV = 5U ,
  R_PIN_CTRL_EV = 6U , R_PIN_CTRL_WIPGM = 7U , R_PIN_CTRL_WHV = 9U , R_PIN_CTRL_WMV = 13U ,
  R_PIN_CTRL_XE = 16U , R_PIN_CTRL_YE = 17U , R_PIN_CTRL_SE = 18U , R_PIN_CTRL_ERASE = 19U ,
  R_PIN_CTRL_PROG = 20U , R_PIN_CTRL_NVSTR = 21U , R_PIN_CTRL_SLM = 22U , R_PIN_CTRL_RECALL = 23U ,
  R_PIN_CTRL_HEM = 24U , R_CNT_LOOP_CTRL_LOOPCNT = 0U , R_CNT_LOOP_CTRL_LOOPOPT = 12U , R_CNT_LOOP_CTRL_LOOPUNIT = 15U ,
  R_CNT_LOOP_CTRL_LOOPDLY = 18U , R_TIMER_CTRL_TNVSUNIT = 0U , R_TIMER_CTRL_TNVSDLY = 3U , R_TIMER_CTRL_TNVHUNIT = 7U ,
  R_TIMER_CTRL_TNVHDLY = 10U , R_TIMER_CTRL_TPGSUNIT = 14U , R_TIMER_CTRL_TPGSDLY = 17U , R_TIMER_CTRL_TRCVUNIT = 21U ,
  R_TIMER_CTRL_TRCVDLY = 24U , R_TIMER_CTRL_TLVSUNIT = 28U , R_TIMER_CTRL_TLVSDLY_L = 31U , R_TEST_CTRL_BUSY = 0U ,
  R_TEST_CTRL_DEBUG = 1U , R_TEST_CTRL_STATUS0 = 2U , R_TEST_CTRL_STATUS1 = 3U , R_TEST_CTRL_DEBUGRUN = 4U ,
  R_TEST_CTRL_STARTRUN = 5U , R_TEST_CTRL_CMDINDEX = 6U , R_TEST_CTRL_DISABLE_IP1 = 16U , R_ABORT_LOOP_ABORT_LOOP = 0U ,
  R_ADR_QUERY_YADRFAIL = 0U , R_ADR_QUERY_XADRFAIL = 5U , R_DOUT_QUERY0_DOUTFAIL = 0U , R_SMW_QUERY_SMWLOOP = 0U ,
  R_SMW_QUERY_SMWLAST = 10U , R_SMW_SETTING0_SMWPARM0 = 0U , R_SMW_SETTING1_SMWPARM1 = 0U , R_SMP_WHV0_SMPWHV0 = 0U ,
  R_SMP_WHV1_SMPWHV1 = 0U , R_SME_WHV0_SMEWHV0 = 0U , R_SME_WHV1_SMEWHV1 = 0U , R_SMW_SETTING2_SMWPARM2 = 0U ,
  R_D_MISR0_DATASIG0 = 0U , R_A_MISR0_ADRSIG0 = 0U , R_C_MISR0_CTRLSIG0 = 0U , R_SMW_SETTING3_SMWPARM3 = 0U ,
  R_DATA_CTRL1_DATA1 = 0U , R_DATA_CTRL2_DATA2 = 0U , R_DATA_CTRL3_DATA3 = 0U , R_REPAIR0_0_RDIS0_0 = 0U ,
  R_REPAIR0_0_RADR0_0 = 1U , R_REPAIR0_1_RDIS0_1 = 0U , R_REPAIR0_1_RADR0_1 = 1U , R_REPAIR1_0_RDIS1_0 = 0U ,
  R_REPAIR1_0_RADR1_0 = 1U , R_REPAIR1_1_RDIS1_1 = 0U , R_REPAIR1_1_RADR1_1 = 1U , R_DATA_CTRL0_EX_DATA0X = 0U ,
  R_TIMER_CTRL_EX_TLVSDLY_H = 0U , R_DOUT_QUERY1_DOUT = 0U , R_D_MISR1_DATASIG1 = 0U , R_A_MISR1_ADRSIG1 = 0U ,
  R_C_MISR1_CTRLSIG1 = 0U , R_DATA_CTRL1_EX_DATA1X = 0U , R_DATA_CTRL2_EX_DATA2X = 0U , R_DATA_CTRL3_EX_DATA3X = 0U ,
  SMW_TIMER_OPTION_SMW_CDIVL = 0U , SMW_TIMER_OPTION_SMW_TVFY = 8U , SMW_SETTING_OPTION0_MV_INIT = 14U , SMW_SETTING_OPTION0_MV_END = 17U ,
  SMW_SETTING_OPTION0_MV_MISC = 20U , SMW_SETTING_OPTION0_IPGM_INIT = 24U , SMW_SETTING_OPTION0_IPGM_END = 26U , SMW_SETTING_OPTION0_IPGM_MISC = 28U ,
  SMW_SETTING_OPTION2_THVS_CTRL = 0U , SMW_SETTING_OPTION2_TRCV_CTRL = 3U , SMW_SETTING_OPTION2_XTRA_ERS = 6U , SMW_SETTING_OPTION2_XTRA_PGM = 8U ,
  SMW_SETTING_OPTION2_WHV_CNTR = 10U , SMW_SETTING_OPTION2_POST_TERS = 18U , SMW_SETTING_OPTION2_POST_TPGM = 21U , SMW_SETTING_OPTION2_VFY_OPT = 23U ,
  SMW_SETTING_OPTION2_TPGM_OPT = 25U , SMW_SETTING_OPTION2_MASK0_OPT = 27U , SMW_SETTING_OPTION2_DIS_PRER = 28U , SMW_SETTING_OPTION3_HEM_WHV_CNTR = 0U ,
  SMW_SETTING_OPTION3_HEM_MAX_ERS = 8U , SMW_SMP_WHV_OPTION0_SMP_WHV_OPT0 = 0U , SMW_SME_WHV_OPTION0_SME_WHV_OPT0 = 0U , SMW_SETTING_OPTION1_TERS_CTRL0 = 0U ,
  SMW_SETTING_OPTION1_TPGM_CTRL = 3U , SMW_SETTING_OPTION1_TNVS_CTRL = 5U , SMW_SETTING_OPTION1_TNVH_CTRL = 8U , SMW_SETTING_OPTION1_TPGS_CTRL = 11U ,
  SMW_SETTING_OPTION1_MAX_ERASE = 14U , SMW_SETTING_OPTION1_MAX_PROG = 23U , SMW_SMP_WHV_OPTION1_SMP_WHV_OPT1 = 0U , SMW_SME_WHV_OPTION1_SME_WHV_OPT1 = 0U ,
  REPAIR0_0_RDIS0_0 = 0U , REPAIR0_0_RADR0_0 = 1U , REPAIR0_1_RDIS0_1 = 0U , REPAIR0_1_RADR0_1 = 1U ,
  REPAIR1_0_RDIS1_0 = 0U , REPAIR1_0_RADR1_0 = 1U , REPAIR1_1_RDIS1_1 = 0U , REPAIR1_1_RADR1_1 = 1U ,
  SMW_HB_SIGNALS_SMW_ARRAY = 0U , SMW_HB_SIGNALS_USER_IFREN1 = 3U , SMW_HB_SIGNALS_USER_PV = 4U , SMW_HB_SIGNALS_USER_EV = 5U ,
  SMW_HB_SIGNALS_USER_IFREN = 6U , SMW_HB_SIGNALS_USER_REDEN = 7U , SMW_HB_SIGNALS_USER_HEM = 8U , BIST_DUMP_CTRL_BIST_DONE = 16U ,
  BIST_DUMP_CTRL_BIST_FAIL = 17U , BIST_DUMP_CTRL_DATADUMP = 18U , BIST_DUMP_CTRL_DATADUMP_TRIG = 19U , BIST_DUMP_CTRL_DATADUMP_PATT = 20U ,
  BIST_DUMP_CTRL_DATADUMP_MRGEN = 22U , BIST_DUMP_CTRL_DATADUMP_MRGTYPE = 23U , ATX_PIN_CTRL_TM_TO_ATX = 0U , FAILCNT_FAILCNT = 0U ,
  PGM_PULSE_CNT0_PGM_CNT0 = 0U , PGM_PULSE_CNT1_PGM_CNT1 = 0U , ERS_PULSE_CNT_ERS_CNT0 = 0U , ERS_PULSE_CNT_ERS_CNT1 = 16U ,
  MAX_PULSE_CNT_LAST_PCNT = 0U , MAX_PULSE_CNT_MAX_ERS_CNT = 16U , MAX_PULSE_CNT_MAX_PGM_CNT = 27U , PORT_CTRL_BDONE_SEL = 0U ,
  PORT_CTRL_BSDO_SEL = 2U
}
 FMU Register Bit Fields Shift Position Enumeration FMU暫存器位元欄位位移位置列舉 更多...
 

函式

constexpr unsigned int operator+ (Mask e)
 
constexpr unsigned int operator+ (Shift e)
 

變數

Register & FMU0
 

詳細描述

Copyright (c) 2020 ZxyKira All rights reserved.

SPDX-License-Identifier: MIT

Copyright = c) 2020 ZxyKira All rights reserved.

SPDX-License-Identifier: MIT

列舉型態說明文件

◆ Mask

enum struct mcxa153::chip::fmu::Mask : unsigned int
strong

Flash Memory Unit Register Mask 快閃記憶體單元暫存器遮罩

This enumeration defines bit masks for accessing and configuring the Flash Memory Unit (FMU) registers. 此列舉定義了用於訪問和配置快閃記憶體單元(FMU)暫存器的位元遮罩。

自
1.0.0
列舉值
FSTAT_FAIL 

FSTAT - FAIL FSTAT - 失敗標誌

Flash Status Register - Command Fail Flag 快閃記憶體狀態寄存器 - 命令失敗標誌

  • [0b0] Error not detected 未檢測到錯誤
  • [0b1] Error detected 檢測到錯誤
FSTAT_CMDABT 

FSTAT - CMDABT FSTAT - 命令中止

Flash Status Register - Command Abort Flag 快閃記憶體狀態寄存器 - 命令中止標誌

  • [0b0] No command abort detected 未檢測到命令中止
  • [0b1] Command abort detected 檢測到命令中止
FSTAT_PVIOL 

FSTAT - PVIOL FSTAT - 保護違規

Flash Status Register - Command Protection Violation Flag 快閃記憶體狀態寄存器 - 命令保護違規標誌

  • [0b0] No protection violation detected 未檢測到保護違規
  • [0b1] Protection violation detected 檢測到保護違規
FSTAT_ACCERR 

FSTAT - ACCERR FSTAT - 訪問錯誤

Flash Status Register - Command Access Error Flag 快閃記憶體狀態寄存器 - 命令訪問錯誤標誌

  • [0b0] No access error detected 未檢測到訪問錯誤
  • [0b1] Access error detected 檢測到訪問錯誤
FSTAT_CWSABT 

FSTAT - CWSABT.

Flash Status Register - Command Write Sequence Abort Flag

  • [0b0]Command write sequence not aborted
  • [0b1]Command write sequence aborted
FSTAT_CCIF 

FSTAT - CCIF.

Flash Status Register - Command Complete Interrupt Flag

  • [0b0]Flash command or initialization in progress
  • [0b1]Flash command or initialization has completed
FSTAT_CMDPRT 

FSTAT - CMDPRT.

Flash Status Register - Command Protection Level

  • [0b00]Secure, normal access
  • [0b01]Secure, privileged access
  • [0b10]Nonsecure, normal access
  • [0b11]Nonsecure, privileged access
FSTAT_CMDP 

FSTAT - CMDP.

Flash Status Register - Command Protection Status Flag

  • [0b0]Command protection level and domain ID are stale
  • [0b1]Command protection level = CMDPRT) and domain ID = CMDDID) are set
FSTAT_CMDDID 

FSTAT - CMDDID.

Flash Status Register - Command Domain ID

FSTAT_DFDIF 

FSTAT - DFDIF.

Flash Status Register - Double Bit Fault Detect Interrupt Flag

  • [0b0]Double bit fault not detected during a valid flash read access from the FMC
  • [0b1]Double bit fault detected = or FCTRL[FDFD] is set) during a valid flash read access from the FMC
FSTAT_SALV_USED 

FSTAT - SALV_USED.

Flash Status Register - Salvage Used for Erase operation

  • [0b0]Salvage not used during the last operation
  • [0b1]Salvage used during the last erase operation
FSTAT_PEWEN 

FSTAT - PEWEN.

Flash Status Register - Program-Erase Write Enable Control

  • [0b00]Writes are not enabled
  • [0b01]Writes are enabled for one flash or IFR phrase = phrase programming, sector erase)
  • [0b10]Writes are enabled for one flash or IFR page = page programming)
  • [0b11]Reserved
FSTAT_PERDY 

FSTAT - PERDY.

Flash Status Register - Program/Erase Ready Control/Status Flag

  • [0b0]Program or sector erase command operation is not stalled
  • [0b1]Program or sector erase command operation is stalled
FCNFG_CCIE 

FCNFG - CCIE.

Flash Configuration Register - Command Complete Interrupt Enable

  • [0b0]Command complete interrupt disabled
  • [0b1]Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set.
FCNFG_ERSREQ 

FCNFG - ERSREQ.

Flash Configuration Register - Mass Erase = Erase All) Request

  • [0b0]No request or request complete
  • [0b1]Request to run the Mass Erase operation
FCNFG_DFDIE 

FCNFG - DFDIE.

Flash Configuration Register - Double Bit Fault Detect Interrupt Enable

  • [0b0]Double bit fault detect interrupt disabled
  • [0b1]Double bit fault detect interrupt enabled; an interrupt request is generated whenever the FSTAT[DFDIF] flag is set
FCNFG_ERSIEN0 

FCNFG - ERSIEN0.

Flash Configuration Register - Erase IFR Sector Enable - Block 0

  • [0b0000]Block 0 IFR Sector X is protected from erase by ERSSCR command
  • [0b0001]Block 0 IFR Sector X is not protected from erase by ERSSCR command
FCNFG_ERSIEN1 

FCNFG - ERSIEN1.

Flash Configuration Register - Erase IFR Sector Enable - Block 1 = for dual block configs)

  • [0b0000]Block 1 IFR Sector X is protected from erase by ERSSCR command
  • [0b0001]Block 1 IFR Sector X is not protected from erase by ERSSCR command
FCTRL_RWSC 

FCTRL - RWSC.

Flash Control Register - Read Wait-State Control

  • [0b0000]no additional wait-states are added = single cycle access)
  • [0b0001]1 additional wait-state is added
  • [0b0010]2 additional wait-states are added
  • [0b0011]3 additional wait-states are added
  • [0b0100]4 additional wait-states are added
  • [0b0101]5 additional wait-states are added
  • [0b0110]6 additional wait-states are added
  • [0b0111]7 additional wait-states are added
  • [0b1000]8 additional wait-states are added
  • [0b1001]9 additional wait-states are added
  • [0b1010]10 additional wait-states are added
  • [0b1011]11 additional wait-states are added
  • [0b1100]12 additional wait-states are added
  • [0b1101]13 additional wait-states are added
  • [0b1110]14 additional wait-states are added
  • [0b1111]15 additional wait-states are added
FCTRL_LSACTIVE 

FCTRL - LSACTIVE.

Flash Control Register - Low Speed Active Mode

  • [0b0]Full speed active mode requested
  • [0b1]Low speed active mode requested
FCTRL_FDFD 

FCTRL - FDFD.

Flash Control Register - Force Double Bit Fault Detect

  • [0b0]FSTAT[DFDIF] sets only if a double bit fault is detected during a valid flash read access from the FMC
  • [0b1]FSTAT[DFDIF] sets during any valid flash read access from the FMC; an interrupt request is generated if the DFDIE bit is set
FCTRL_ABTREQ 

FCTRL - ABTREQ.

Flash Control Register - Abort Request

  • [0b0]No request to abort a command write sequence
  • [0b1]Request to abort a command write sequence
FTEST_TMECTL 

FCTRL - TMECTL.

Flash Test Register - Test Mode Entry Control

  • [0b0]FTEST register always reads 0 and writes to FTEST are ignored
  • [0b1]FTEST register is readable and can be written to enable writability of TME
FTEST_TMEWR 

FCTRL - TMEWR.

Flash Test Register - Test Mode Entry Writable

  • [0b0]TME bit is not writable
  • [0b1]TME bit is writable
FTEST_TME 

FCTRL - TME.

Flash Test Register - Test Mode Entry

  • [0b0]Test mode entry not requested
  • [0b1]Test mode entry requested
FTEST_TMODE 

FCTRL - TMODE.

Flash Test Register - Test Mode Status

  • [0b0]Test mode not active
  • [0b1]Test mode active
FTEST_TMELOCK 

FCTRL - TMELOCK.

Flash Test Register - Test Mode Entry Lock

  • [0b0]FTEST register not locked from accepting writes
  • [0b1]FTEST register locked from accepting writes
FCCOB0_CMDCODE 

FCCOB0 - CMDCODE.

Flash Command Control 0 Register - Command code

FCCOB1_CMDOPT 

FCCOB1 - CMDOPT.

Flash Command Control 1 Register - Command options

FCCOB2_CMDADDR 

FCCOB2 - CMDADDR Flash Command Control 2 Register - Command starting address.

FCCOB3_CMDADDRE 

FCCOB3 - CMDADDRE.

Flash Command Control 3 Register - Command ending address

FCCOB4_CMDDATA0 

FCCOB4 - CMDDATA0.

Flash Command Control 4 Register - Command data word 0

FCCOB5_CMDDATA1 

FCCOB5 - CMDDATA1.

Flash Command Control 5 Register - Command data word 1

FCCOB6_CMDDATA2 

FCCOB6 - CMDDATA2.

Flash Command Control 6 Register - Command data word 2

FCCOB7_CMDDATA3 

FCCOB7 - CMDDATA3.

Flash Command Control 7 Register - Command data word 3

RESET_STATUS_ARY_TRIM_DONE 

RESET_STATUS - ARY_TRIM_DONE.

FMU Initialization Tracking Register - Array Trim Complete

  • [0b0]Recall register load operation has not been completed
  • [0b1]Recall register load operation has completed
RESET_STATUS_FMU_PARM_EN 

RESET_STATUS - FMU_PARM_EN.

FMU Initialization Tracking Register - Status of the C0DE_C0DEh check to enable loading of the FMU parameters

  • [0b0]C0DE_C0DEh check not attempted
  • [0b1]C0DE_C0DEh check completed
RESET_STATUS_FMU_PARM_DONE 

RESET_STATUS - FMU_PARM_DONE.

FMU Initialization Tracking Register - FMU Register Load Complete

  • [0b0]FMU registers have not been loaded
  • [0b1]FMU registers have been loaded
RESET_STATUS_SOC_TRIM_EN 

RESET_STATUS - SOC_TRIM_EN.

FMU Initialization Tracking Register - Status of the C0DE_C0DEh check to enable loading of the SoC trim settings

  • [0b0]C0DE_C0DEh check not attempted
  • [0b1]C0DE_C0DEh check completed
RESET_STATUS_SOC_TRIM_ECC 

RESET_STATUS - SOC_TRIM_ECC.

FMU Initialization Tracking Register - Status of the C0DE_C0DEh check for enabling ECC decoder during reads of SoC trim settings

  • [0b0]C0DE_C0DEh check failed
  • [0b1]C0DE_C0DEh check passed
RESET_STATUS_SOC_TRIM_DONE 

RESET_STATUS - SOC_TRIM_DONE.

FMU Initialization Tracking Register - SoC Trim Complete

  • [0b0]SoC Trim registers have not been updated
  • [0b1]All SoC Trim registers have been updated
RESET_STATUS_RPR_DONE 

RESET_STATUS - RPR_DONE.

FMU Initialization Tracking Register - Array Repair Complete

  • [0b0]Repair registers have not been loaded
  • [0b1]Repair registers have been loaded
RESET_STATUS_INIT_DONE 

RESET_STATUS - INIT_DONE.

FMU Initialization Tracking Register - Initialization Done

  • [0b0]All initialization steps did not complete
  • [0b1]All initialization steps completed
RESET_STATUS_RST_SF_ERR 

RESET_STATUS - RST_SF_ERR.

FMU Initialization Tracking Register - ECC Single Fault during Reset Recovery

  • [0b0]No single-bit faults detected during initialization
  • [0b1]At least one single ECC fault was detected during initialization
RESET_STATUS_RST_DF_ERR 

RESET_STATUS - RST_DF_ERR.

FMU Initialization Tracking Register - ECC Double Fault during Reset Recovery

  • [0b0]No double-bit faults detected during initialization
  • [0b1]Double-bit ECC fault was detected during initialization
RESET_STATUS_SOC_TRIM_DF_ERR 

RESET_STATUS - SOC_TRIM_DF_ERR.

FMU Initialization Tracking Register - ECC Double Fault during load of SoC Trim phrases

RESET_STATUS_RST_PATCH_LD 

RESET_STATUS - RST_PATCH_LD.

FMU Initialization Tracking Register - Reset Patch Required

  • [0b0]No patch required to be loaded during reset
  • [0b1]Patch loaded during reset
RESET_STATUS_RECALL_DATA_MISMATCH 

RESET_STATUS - RECALL_DATA_MISMATCH.

FMU Initialization Tracking Register - Recall Data Mismatch

  • [0b0]Data read towards end of reset matched data read for Recall
  • [0b1]Data read towards end of reset did not match data read for recall
MCTL_COREHLD 

MCTL - COREHLD.

FMU Control Register - Core Hold

  • [0b0]CPU access is allowed
  • [0b1]CPU access must be blocked
MCTL_LSACT_EN 

MCTL - LSACT_EN.

FMU Control Register - LSACTIVE Feature Enable

  • [0b0]LSACTIVE feature disabled completely: FCTRL[LSACTIVE] is forced low and no longer writable, LVE cannot assert at the TSMC array interface.
  • [0b1]LSACTIVE feature fully enabled and controllable by SoC and internal UINT SM.
MCTL_LSACTWREN 

MCTL - LSACTWREN.

FMU Control Register - LSACTIVE Write Enable

  • [0b0]Unrestricted write access allowed
  • [0b1]Write access while CMP set must match CMDDID and CMDPRT
MCTL_MASTER_REPAIR_EN 

MCTL - MASTER_REPAIR_EN.

FMU Control Register - Master Repair Enable

  • [0b0]Repair disabled
  • [0b1]Repair enable determined by bit 0 of each REPAIR register
MCTL_RFCMDEN 

MCTL - RFCMDEN.

FMU Control Register - RF Active Command Enable Control

  • [0b0]Flash commands blocked = CCIF not writable)
  • [0b1]Flash commands allowed
MCTL_CWSABTEN 

MCTL - CWSABTEN.

FMU Control Register - Command Write Sequence Abort Enable

  • [0b0]CWS abort feature is disabled
  • [0b1]CWS abort feature is enabled
MCTL_MRGRDDIS 

MCTL - MRGRDDIS.

FMU Control Register - Margin Read Disable

  • [0b0]Margin Read Settings are enabled
  • [0b1]Margin Read Settings are disabled
MCTL_MRGRD0 

MCTL - MRGRD0.

FMU Control Register - Margin Read Setting for Program

MCTL_MRGRD1 

MCTL - MRGRD1.

FMU Control Register - Margin Read Setting for Erase

MCTL_ERSAACK 

MCTL - ERSAACK.

FMU Control Register - Mass Erase = Erase All) Acknowledge

  • [0b0]Mass Erase operation is not active = operation has completed or has not started)
  • [0b1]Mass Erase operation is active = controller acknowledges that the soc_ersall_req input is asserted and will continue with the operation)
MCTL_SCAN_OBS 

MCTL - SCAN_OBS.

FMU Control Register - Scan Observability Control

  • [0b0]Normal functional behavior
  • [0b1]Enables observation of signals that may otherwise be ATPG untestable
MCTL_BIST_CTL 

MCTL - BIST_CTL.

FMU Control Register - BIST IP Control

  • [0b0]BIST IP disabled
  • [0b1]BIST IP enabled
MCTL_SMWR_CTL 

MCTL - SMWR_CTL.

FMU Control Register - SMWR IP Control

  • [0b0]SMWR IP disabled
  • [0b1]SMWR IP enabled
MCTL_SALV_DIS 

MCTL - SALV_DIS.

FMU Control Register - Salvage Disable

  • [0b0]Salvage enabled = ECC used during erase verify)
  • [0b1]Salvage disabled = ECC not used during erase verify)
MCTL_SOC_ECC_CTL 

MCTL - SOC_ECC_CTL.

FMU Control Register - SOC ECC Control

  • [0b0]ECC is enabled for SOC read access
  • [0b1]ECC is disabled for SOC read access
MCTL_FMU_ECC_CTL 

MCTL - FMU_ECC_CTL.

FMU Control Register - FMU ECC Control

  • [0b0]ECC is enabled for FMU program operations
  • [0b1]ECC is disabled for FMU program operations
MCTL_BIST_PWR_DIS 

MCTL - BIST_PWR_DIS.

FMU Control Register - BIST Power Mode Disable

  • [0b0]BIST DFT logic has full control of SLM and LVE when BIST is enabled = including during commands)
  • [0b1]BIST DFT logic has no control of SLM and LVE; power mode RTL is in complete control of SLM and LVE values
MCTL_OSC_H 

MCTL - OSC_H.

FMU Control Register - Oscillator control

  • [0b0]Use APB clock
  • [0b1]Use a known fixed-frequency clock, e.g. 12 MHz
BSEL_GEN_SBSEL_GEN 

BSEL_GEN - SBSEL_GEN.

FMU Block Select Generation Register - Generated SBSEL

BSEL_GEN_MBSEL_GEN 

BSEL_GEN - MBSEL_GEN.

FMU Block Select Generation Register - Generated MBSEL

PWR_OPT_PD_CDIV 

PWR_OPT - PD_CDIV.

Power Mode Options Register - Power Down Clock Divider Setting

PWR_OPT_SLM_COUNT 

PWR_OPT - SLM_COUNT.

Power Mode Options Register - Sleep Recovery Timer Count

PWR_OPT_PD_TIMER_EN 

PWR_OPT - PD_TIMER_EN.

Power Mode Options Register - Power Down BIST Timer Enable

  • [0b0]BIST timer is not triggered during Power Down recovery
  • [0b1]BIST timer is triggered during Power Down recovery = default behavior)
CMD_CHECK_ALIGNFAIL_PHR 

CMD_CHECK - ALIGNFAIL_PHR.

FMU Command Check Register - Phrase Alignment Fail

  • [0b0]The address is phrase-aligned
  • [0b1]The address is not phrase-aligned
CMD_CHECK_ALIGNFAIL_PG 

CMD_CHECK - ALIGNFAIL_PG.

FMU Command Check Register - Page Alignment Fail

  • [0b0]The address is page-aligned
  • [0b1]The address is not page-aligned
CMD_CHECK_ALIGNFAIL_SCR 

CMD_CHECK - ALIGNFAIL_SCR.

FMU Command Check Register - Sector Alignment Fail

  • [0b0]The address is sector-aligned
  • [0b1]The address is not sector-aligned
CMD_CHECK_ALIGNFAIL_BLK 

CMD_CHECK - ALIGNFAIL_BLK.

FMU Command Check Register - Block Alignment Fail

  • [0b0]The address is block-aligned
  • [0b1]The address is not block-aligned
CMD_CHECK_ADDR_FAIL 

CMD_CHECK - ADDR_FAIL.

FMU Command Check Register - Address Fail

  • [0b0]The address is within the flash or IFR address space
  • [0b1]The address is outside the flash or IFR address space
CMD_CHECK_IFR_CMD 

CMD_CHECK - IFR_CMD.

FMU Command Check Register - IFR Command

  • [0b0]The command operates on a main flash address
  • [0b1]The command operates on an IFR address
CMD_CHECK_ALL_CMD 

CMD_CHECK - ALL_CMD.

FMU Command Check Register - All Blocks Command

  • [0b0]The command operates on a single flash block
  • [0b1]The command operates on all flash blocks
CMD_CHECK_RANGE_FAIL 

CMD_CHECK - RANGE_FAIL.

FMU Command Check Register - Address Range Fail

  • [0b0]The address range is valid
  • [0b1]The address range is invalid
CMD_CHECK_SCR_ALIGN_CHK 

SCMD_CHECK - CR_ALIGN_CHK.

FMU Command Check Register - Sector Alignment Check

  • [0b0]No sector alignment check
  • [0b1]Sector alignment check
CMD_CHECK_OPTION_FAIL 

CMD_CHECK - OPTION_FAIL.

FMU Command Check Register - Option Check Fail

  • [0b0]Option check passes for read command or command is not a read command
  • [0b1]Option check fails for read command
CMD_CHECK_ILLEGAL_CMD 

CMD_CHECK - ILLEGAL_CMD.

FMU Command Check Register - Illegal Command

  • [0b0]Command is legal
  • [0b1]Command is illegal
BSEL_SBSEL 

BSEL - SBSEL.

FMU Block Select Register - Slave Block Select

BSEL_MBSEL 

BSEL - MBSEL.

FMU Block Select Register - Master Block Select

MSIZE_MAXADDR0 

MSIZE - MAXADDR0.

FMU Memory Size Register - Size of Flash Block 0

FLASH_RD_ADD_FLASH_RD_ADD 

FLASH_RD_ADD - FLASH_RD_ADD.

Flash Read Address Register - Flash Read Address

FLASH_STOP_ADD_FLASH_STOP_ADD 

FLASH_STOP_ADD - FLASH_STOP_ADD.

Flash Stop Address Register - Flash Stop Address

FLASH_RD_CTRL_FLASH_RD 

FLASH_RD_CTRL - FLASH_RD.

Flash Read Control Register - Flash Read Enable

  • [0b0]Manual flash read not enabled.(default)
  • [0b1]Manual flash read enabled
FLASH_RD_CTRL_WIDE_LOAD 

FLASH_RD_CTRL - WIDE_LOAD.

Flash Read Control Register - Wide Load Enable

  • [0b0]Wide load mode disabled = default)
  • [0b1]Wide load mode enabled
FLASH_RD_CTRL_SINGLE_RD 

FLASH_RD_CTRL - SINGLE_RD.

Flash Read Control Register - Single Flash Read

  • [0b0]Normal UINT operation
  • [0b1]UINT configured for single cycle reads
MM_ADDR_MM_ADDR 

MM_ADDR - MM_ADDR.

Memory Map Address Register - Memory Map Address

MM_WDATA_MM_WDATA 

MM_WDATA - MM_WDATA.

Memory Map Write Data Register - Memory Map Write Data

MM_CTL_MM_SEL 

MM_CTL - MM_SEL.

Memory Map Control Register - Register Access Enable

MM_CTL_MM_RD 

MM_CTL - MM_RD.

Memory Map Control Register - Register R/W Control

  • [0b0]Write to register
  • [0b1]Read register
MM_CTL_BIST_ON 

MM_CTL - BIST_ON.

Memory Map Control Register - BIST on

  • [0b0]BIST enable not forced by user interface
  • [0b1]BIST enable control by user interface
MM_CTL_FORCE_SW_CLK 

MM_CTL - FORCE_SW_CLK.

Memory Map Control Register - Force Switch Clock

  • [0b0]Switch clock not forced on = gated normally)
  • [0b1]Switch clock forced on
UINT_CTL_SET_FAIL 

UINT_CTL - SET_FAIL.

User Interface Control Register - Set Fail On Exit

  • [0b0]FAIL flag should not be set on command exit = no failure detected)
  • [0b1]FAIL flag should be set on command exit
UINT_CTL_DBERR 

UINT_CTL - DBERR.

User Interface Control Register - Double-Bit ECC Fault Detect

  • [0b0]No double-bit fault detected during UINT-driven read sequence
  • [0b1]Double-bit fault detected during UINT-driven read sequence
RD_DATA0_RD_DATA0 

RD_DATA0 - RD_DATA0.

Read Data 0 Register - Read Data 0

RD_DATA1_RD_DATA1 

RD_DATA1 - RD_DATA1.

Read Data 1 Register - Read Data 1

RD_DATA2_RD_DATA2 

RD_DATA2 - RD_DATA2.

Read Data 2 Register - Read Data 2

RD_DATA3_RD_DATA3 

RD_DATA3 - RD_DATA3.

Read Data 3 Register - Read Data 3

PARITY_PARITY 

PARITY - PARITY.

Parity Register - Read data [136:128]

RD_PATH_CTRL_STATUS_RD_CAPT 

RD_PATH_CTRL_STATUS - RD_CAPT.

Read Path Control and Status Register - Read Capture Clock Periods

RD_PATH_CTRL_STATUS_SE_SIZE 

RD_PATH_CTRL_STATUS - SE_SIZE.

Read Path Control and Status Register - SE Clock Periods

RD_PATH_CTRL_STATUS_ECC_ENABLEB 

RD_PATH_CTRL_STATUS - ECC_ENABLEB.

Read Path Control and Status Register - ECC Decoder Control

  • [0b0]ECC decoder enabled = default)
  • [0b1]ECC decoder disabled
RD_PATH_CTRL_STATUS_MISR_EN 

RD_PATH_CTRL_STATUS - MISR_EN.

Read Path Control and Status Register - MISR Enable

  • [0b0]MISR option disabled = default)
  • [0b1]MISR option enabled
RD_PATH_CTRL_STATUS_CPY_PAR_EN 

RD_PATH_CTRL_STATUS - CPY_PAR_EN.

Read Path Control and Status Register - Copy Parity Enable

  • [0b0]Copy parity disabled
  • [0b1]Copy parity enabled
RD_PATH_CTRL_STATUS_BIST_MUX_TO_SMW 

RD_PATH_CTRL_STATUS - BIST_MUX_TO_SMW.

Read Path Control and Status Register - BIST Mux to SMW

  • [0b0]BIST drives fields
  • [0b1]SMW registers drive fields
RD_PATH_CTRL_STATUS_AD_SET 

RD_PATH_CTRL_STATUS - AD_SET.

Read Path Control and Status Register - Multi-Cycle Address Setup Time

RD_PATH_CTRL_STATUS_WR_PATH_EN 

RD_PATH_CTRL_STATUS - WR_PATH_EN.

Read Path Control and Status Register - Write Path Enable

  • [0b0]Writes to BIST setting registers driven by MM_WDATA
  • [0b1]Writes to BIST setting registers driven by SMW_DIN
RD_PATH_CTRL_STATUS_WR_PATH_ECC_EN 

RD_PATH_CTRL_STATUS - WR_PATH_ECC_EN.

Read Path Control and Status Register - Write Path ECC Enable

  • [0b0]ECC encoding disabled
  • [0b1]ECC encoding enabled
RD_PATH_CTRL_STATUS_DBERR_REG 

RD_PATH_CTRL_STATUS - DBERR_REG.

Read Path Control and Status Register - Double-Bit Error

  • [0b0]Double-bit fault not detected
  • [0b1]Double-bit fault detected on previous UINT flash read
RD_PATH_CTRL_STATUS_SBERR_REG 

RD_PATH_CTRL_STATUS - SBERR_REG.

Read Path Control and Status Register - Single-Bit Error

  • [0b0]Single-bit fault not detected
  • [0b1]Single-bit fault detected on previous UINT flash read
RD_PATH_CTRL_STATUS_CPY_PHRASE_EN 

RD_PATH_CTRL_STATUS - CPY_PHRASE_EN.

Read Path Control and Status Register - Copy Phrase Enable

  • [0b0]Copy Flash read data disabled
  • [0b1]Copy Flash read data enabled
RD_PATH_CTRL_STATUS_SMW_ARRAY1_SMW0_SEL 

RD_PATH_CTRL_STATUS - SMW_ARRAY1_SMW0_SEL.

Read Path Control and Status Register - SMW_ARRAY1_SMW0_SEL

  • [0b0]Select block 0
  • [0b1]Select block 1
RD_PATH_CTRL_STATUS_BIST_ECC_EN 

RD_PATH_CTRL_STATUS - BIST_ECC_EN.

Read Path Control and Status Register - BIST ECC Enable

  • [0b0]ECC correction disabled
  • [0b1]ECC correction enabled
RD_PATH_CTRL_STATUS_LAST_READ 

RD_PATH_CTRL_STATUS - LAST_READ.

Read Path Control and Status Register - Last Read

  • [0b0]Latest read not last in multi-address operation
  • [0b1]Latest read last in multi-address operation
SMW_DIN0_SMW_DIN0 

SMW_DIN0 - SMW_DIN0.

SMW DIN 0 Register - SMW DIN 0

SMW_DIN1_SMW_DIN1 

SMW_DIN1 - SMW_DIN1.

SMW DIN 1 Register - SMW DIN 1

SMW_DIN2_SMW_DIN2 

SMW_DIN2 - SMW_DIN2.

SMW DIN 2 Register - SMW DIN 2

SMW_DIN3_SMW_DIN3 

SMW_DIN3 - SMW_DIN3.

SMW DIN 3 Register - SMW DIN 3

SMW_ADDR_SMW_ADDR 

SMW_ADDR - SMW_ADDR.

SMW Address Register - SMW Address

SMW_CMD_WAIT_CMD 

SMW_CMD_WAIT - CMD.

SMW Command and Wait Register - SMW Command

  • [0b000]IDLE
  • [0b001]ABORT
  • [0b010]SME2 to one-shot mass erase
  • [0b011]SME3 to sector erase on selected array
  • [0b100]SMP1 to program phrase or page on selected array with shot disabled on previously programmed bit
  • [0b101]Reserved for SME4 = multi-sector erase)
  • [0b110]SMP2 to program phrase or page on selected array to repair cells of weak program after power loss
  • [0b111]Reserved
SMW_CMD_WAIT_WAIT_EN 

SMW_CMD_WAIT - WAIT_EN.

SMW Command and Wait Register - SMW Wait Enable

  • [0b0]Wait feature disabled
  • [0b1]Wait feature enabled
SMW_CMD_WAIT_WAIT_AUTO_SET 

SMW_CMD_WAIT - WAIT_AUTO_SET.

SMW Command and Wait Register - SMW Wait Auto Set

SMW_STATUS_SMW_ERR 

SMW_STATUS - SMW_ERR.

SMW Status Register - SMW Error

  • [0b0]Error not detected
  • [0b1]Error detected
SMW_STATUS_SMW_BUSY 

SMW_STATUS - SMW_BUSY.

SMW Status Register - SMW Busy

  • [0b0]SMW command not active
  • [0b1]SMW command is active
SMW_STATUS_BIST_BUSY 

SMW_STATUS - BIST_BUSY.

SMW Status Register - BIST Busy

  • [0b0]BIST Command not active
  • [0b1]BIST Command is active
SOCTRIM0_0_TRIM0_0 

SOCTRIM0_0 - TRIM0_0.

SoC Trim Phrase 0 Word 0 Register - TRIM0_0

SOCTRIM0_1_TRIM0_1 

SOCTRIM0_1 - TRIM0_1.

SoC Trim Phrase 0 Word 1 Register - TRIM0_1

SOCTRIM0_2_TRIM0_2 

SOCTRIM0_2 - TRIM0_2.

SoC Trim Phrase 0 Word 2 Register - TRIM0_2

SOCTRIM0_3_TRIM0_3 

SOCTRIM0_3 - TRIM0_3.

SoC Trim Phrase 0 Word 3 Register - TRIM0_3

SOCTRIM1_0_TRIM1_0 

SOCTRIM1_0 - TRIM1_0.

SoC Trim Phrase 1 Word 0 Register - TRIM1_0

SOCTRIM1_1_TRIM1_1 

SOCTRIM1_1 - TRIM1_1.

SoC Trim Phrase 1 Word 1 Register - TRIM1_1

SOCTRIM1_2_TRIM1_2 

SOCTRIM1_2 - TRIM1_2.

SoC Trim Phrase 1 Word 2 Register - TRIM1_2

SOCTRIM1_3_TRIM1_3 

SOCTRIM1_3 - TRIM1_3.

SoC Trim Phrase 1 Word 3 Register - TRIM1_3

SOCTRIM2_0_TRIM2_0 

SOCTRIM2_0 - TRIM2_0.

SoC Trim Phrase 2 Word 0 Register - TRIM2_0

SOCTRIM2_1_TRIM2_1 

SOCTRIM2_1 - TRIM2_1.

SoC Trim Phrase 2 Word 1 Register - TRIM2_1

SOCTRIM2_2_TRIM2_2 

SOCTRIM2_2 - TRIM2_2.

SoC Trim Phrase 2 Word 2 Register - TRIM2_2

SOCTRIM2_3_TRIM2_3 

SOCTRIM2_3 - TRIM2_3.

SoC Trim Phrase 2 Word 3 Register - TRIM2_3

SOCTRIM3_0_TRIM3_0 

SOCTRIM3_0 - TRIM3_0.

SoC Trim Phrase 3 Word 0 Register - TRIM3_0

SOCTRIM3_1_TRIM3_1 

SOCTRIM3_1 - TRIM3_1.

SoC Trim Phrase 3 Word 1 Register - TRIM3_1

SOCTRIM3_2_TRIM3_2 

SOCTRIM3_2 - TRIM3_2.

SoC Trim Phrase 3 Word 2 Register - TRIM3_2

SOCTRIM3_3_TRIM3_3 

SOCTRIM3_3 - TRIM3_3.

SoC Trim Phrase 3 Word 3 Register - TRIM3_3

SOCTRIM4_0_TRIM4_0 

SOCTRIM4_0 - TRIM4_0.

SoC Trim Phrase 4 Word 0 Register - TRIM4_0

SOCTRIM4_1_TRIM4_1 

SOCTRIM4_1 - TRIM4_1.

SoC Trim Phrase 4 Word 1 Register - TRIM4_1

SOCTRIM4_2_TRIM4_2 

SOCTRIM4_2 - TRIM4_2.

SoC Trim Phrase 4 Word 2 Register - TRIM4_2

SOCTRIM4_3_TRIM4_3 

SOCTRIM4_3 - TRIM4_3.

SoC Trim Phrase 4 Word 3 Register - TRIM4_3

SOCTRIM5_0_TRIM5_0 

SOCTRIM5_0 - TRIM5_0.

SoC Trim Phrase 5 Word 0 Register - TRIM5_0

SOCTRIM5_1_TRIM5_1 

SOCTRIM5_1 - TRIM5_1.

SoC Trim Phrase 5 Word 1 Register - TRIM5_1

SOCTRIM5_2_TRIM5_2 

SOCTRIM5_2 - TRIM5_2.

SoC Trim Phrase 5 Word 2 Register - TRIM5_2

SOCTRIM5_3_TRIM5_3 

SOCTRIM5_3 - TRIM5_3.

SoC Trim Phrase 5 Word 3 Register - TRIM5_3

SOCTRIM6_0_TRIM6_0 

SOCTRIM6_0 - TRIM6_0.

SoC Trim Phrase 6 Word 0 Register - TRIM6_0

SOCTRIM6_1_TRIM6_1 

SOCTRIM6_1 - TRIM6_1.

SoC Trim Phrase 6 Word 1 Register - TRIM6_1

SOCTRIM6_2_TRIM6_2 

SOCTRIM6_2 - TRIM6_2.

SoC Trim Phrase 6 Word 2 Register - TRIM6_2

SOCTRIM6_3_TRIM6_3 

SOCTRIM6_3 - TRIM6_3.

SoC Trim Phrase 6 Word 3 Register - TRIM6_3

SOCTRIM7_0_TRIM7_0 

SOCTRIM7_0 - TRIM7_0.

SoC Trim Phrase 7 Word 0 Register - TRIM7_0

SOCTRIM7_1_TRIM7_1 

SOCTRIM7_1 - TRIM7_1.

SoC Trim Phrase 7 Word 1 Register - TRIM7_1

SOCTRIM7_2_TRIM7_2 

SOCTRIM7_2 - TRIM7_2.

SoC Trim Phrase 7 Word 2 Register - TRIM7_2

SOCTRIM7_3_TRIM7_3 

SOCTRIM7_3 - TRIM7_3.

SoC Trim Phrase 7 Word 3 Register - TRIM7_3

R_IP_CONFIG_IPSEL0 

R_IP_CONFIG - IPSEL0.

BIST Configuration Register - Block 0 Select Control

  • [0b00]Unselect block 0
  • [0b01]not used, reserved
  • [0b10]Enable block 0 test, repair off = default)
  • [0b11]Enable block 0 test, repair on
R_IP_CONFIG_IPSEL1 

R_IP_CONFIG - IPSEL1.

BIST Configuration Register - Block 1 Select Control

  • [0b00]Unselect block 1
  • [0b01]not used, reserved
  • [0b10]Enable block 1 test, repair off = default)
  • [0b11]Enable block 1 test, repair on
R_IP_CONFIG_BIST_CDIVL 

R_IP_CONFIG - BIST_CDIVL.

BIST Configuration Register - Clock Divide Scalar for Long Pulse

R_IP_CONFIG_CDIVS 

R_IP_CONFIG - CDIVS.

BIST Configuration Register - Number of clock cycles to generate short pulse

R_IP_CONFIG_BIST_TVFY 

R_IP_CONFIG - BIST_TVFY.

BIST Configuration Register - Timer adjust for verify

R_IP_CONFIG_TSTCTL 

R_IP_CONFIG - TSTCTL.

BIST Configuration Register - BIST self-test control

  • [0b00]Default, disable both BIST self-test and MISR
  • [0b01]Enable BIST self-test mode DOUT from macro will be forced to '0', and disable MISR.
  • [0b10]Enable MISR
  • [0b11]Enable both BIST self-test mode and MISR
R_IP_CONFIG_DBGCTL 

R_IP_CONFIG - DBGCTL.

BIST Configuration Register - Debug feature control

  • [0b0]Default
  • [0b1]Enable debug feature to collect failure address and data.
R_IP_CONFIG_BIST_CLK_SEL 

R_IP_CONFIG - BIST_CLK_SEL.

BIST Configuration Register - BIST Clock Select

R_IP_CONFIG_SMWTST 

R_IP_CONFIG - SMWTST.

BIST Configuration Register - SMWR DOUT Function Control

  • [0b00]Default
  • [0b01]Enable SMWR self-test mode, DOUT from macro will be forced to all 0
  • [0b10]Enable SMWR self-test mode, DOUT from macro will be forced to all 1
  • [0b11]Reserved = unused)
R_IP_CONFIG_ECCEN 

R_IP_CONFIG - ECCEN.

BIST Configuration Register - BIST ECC Control

  • [0b0]Default mode = no ECC encode or decode)
  • [0b1]Enable ECC encode/decode
R_TESTCODE_TESTCODE 

R_TESTCODE - TESTCODE.

BIST Test Code Register - Used to store test code information before running TMR-RST/TMRSET BIST command

R_DFT_CTRL_DFT_XADR 

R_DFT_CTRL - DFT_XADR.

BIST DFT Control Register - DFT XADR Pattern

  • [0b0000]XADR fixed, no change at all
  • [0b0001]XADR increased by 1 after row. For READ operation, XADR increases by 1 after reading the last word of row. For PROG operation, XADR increases by 1 after NVSTR falls.
  • [0b0010]XADR increased for diagonal. For PROG-DIAGONAL operation, XADR is increased to create diagonal pattern.
  • [0b0011]XADR increased by sector. During ERASE operation, XADR increased by number of rows in a sector when NVSTR falls.
  • [0b0100]XADR inversed. XADR is inversed after reading one word or after programming one row when NVSTR falls.
  • [0b0101]XADR increased by 2 after row. For READ operation, XADR is increased by 2 after reading the last word of a row. For PROG operation, XADR is increased by 2 when NVSTR falls.
  • [0b0110]XADR[0] inversed. XADR[0] is inversed after reading one word or after programming one row when NVSTR falls.
  • [0b0111]XADR increased by 1. For READ operations only, XADR increased by 1 after each read cycle.
  • [0b1000]XADR decreased by 1 after row. For READ operations only, XADR is decreased by 1 after YADR decreases to 0.
  • [0b1001]XADR decreased by 1. For READ operations only, XADR is decreased by 1 after each read cycle.
R_DFT_CTRL_DFT_YADR 

R_DFT_CTRL - DFT_YADR.

BIST DFT Control Register - DFT YADR Pattern

  • [0b0000]YADR fixed, no change at all
  • [0b0001]YADR for ICKBD. For PROG and READ operations, YADR changed to generate inverse checkerboard pattern.
  • [0b0010]YADR for CKBD. For PROG and READ operations, YADR changed to generate checkerboard pattern.
  • [0b0011]YADR increased by 1. For READ operations, YADR increased by 1 after each read cycle. For PROG operations, YADR increased by 1 after YE falls.
  • [0b0100]YADR increased for diagonal. For PROG-DIAGONAL operation, YADR is increased to create diagonal pattern.
  • [0b0101]YADR inversed. YADR is inversed after reading one word or after programming one word when YE falls.
  • [0b0110]YADR[0] inversed. YADR[0] is inversed after reading one word or after programming one word when YE falls.
  • [0b0111]YADR increased by 1 after last row. For READ operations only, YADR is increased by 1 after XADR reaches last row.
  • [0b1000]YADR decreased by 1. For READ operations only, YADR is decreased by 1 after each read cycle.
  • [0b1001]YADR decreased by 1 after first row. For READ operations only, YADR is decreased by 1 after XADR decreases to 0.
R_DFT_CTRL_DFT_DATA 

R_DFT_CTRL - DFT_DATA.

BIST DFT Control Register - DFT Data Pattern

  • [0b0000]CKBD pattern. For READ operations only, compare DOUT with checkerboard data pattern for each read cycle.
  • [0b0001]ICKBD pattern. For READ operations only, compare DOUT with inverse checkerboard data pattern for each read cycle.
  • [0b0010]Diagonal pattern. Used for READ operations only, compare DOUT to diagonal pattern.
  • [0b0011]Fixed data pattern. For READ operations, comparison to DOUT for selected groups; refer to R_ADR_CTRL[GRPSEL] for modules with multiple groups.
  • [0b0100]Random data pattern which will be generated based on the initial seed set in R_DATA; for READ operations, used for DOUT comparison of selected groups. For PROG operations, used to control DIN of selected groups.
  • [0b0101]DOUT based pattern. For READ operations only, DOUT of selected group will be latched in R_DATA. If more than one group is selected in R_ADR_CTRL[GRPSEL], the group with the lower index will be latched.
  • [0b0110]R_DATA based pattern. For READ operations, expected DOUT value of selected groups equals to R_DATA when XADR[0]==YADR[0] or ~R_DATA when XADR[0]!=YADR[0]. For PROG operations, DIN of selected groups equals R_DATA when XADR[0]==YADR[0] or ~R_DATA when XADR[0]!=YADR[0].
  • [0b0111]SCAN-IO pattern. For READ operations, control expected DOUT value of selected groups to SCAN-IO data pattern. For PROG operations, control DIN of selected groups to SCAN-IO data pattern.
  • [0b1000]REPAIR set. For PROG operation to IFR1(7,1) and IFR1(7,2), R_REPAIR0_0 and R_REPAIR0_1 or R_REPAIR1_0 and R_REPAIR1_1 will control DIN. For READ operation on IFR1(7,1) and IFR1(7,2), DOUT will be compared against R_REPAIR0_0 and R_REPAIR0_1 or R_REPAIR1_0 andR_REPAIR1_1. When this option is selected, only one flash block can be selected.
  • [0b1001]REPAIR load. For READ operation only, DOUT from IFR1(7,1) and IFR1(7,2) is loaded to R_REPAIR0 and R_REPAIR1.
R_DFT_CTRL_CMP_MASK 

R_DFT_CTRL - CMP_MASK.

BIST DFT Control Register - Data Compare Mask

  • [0b00]Expected data is compared to DOUT
  • [0b01]Expected data = only 0s are considered) are compared to DOUT
  • [0b10]Expected data = only 1s are considered) are compared to DOUT
R_DFT_CTRL_DFT_DATA_SRC 

R_DFT_CTRL - DFT_DATA_SRC.

BIST DFT Control Register - DFT Data Source

  • [0b0]{R_DATA_CTRL0,R_DATA_CTRL_EX[2:0],R_DATA_CTRL0,R_DATA_CTRL_EX[2:0],R_DATA_CTRL0,R_DATA_CTRL_EX[2:0],R_DATA_CTRL0} is used
  • [0b1]{R_DATA_CTRL3,R_DATA_CTRL2_EX[2:0],R_DATA_CTRL2,R_DATA_CTRL1_EX[2:0],R_DATA_CTRL1,R_DATA_CTRL_EX[2:0],R_DATA_CTRL0} is used
R_ADR_CTRL_GRPSEL 

R_ADR_CTRL - GRPSEL.

BIST Address Control Register - Data Group Select

  • [0b0000]Select no data
  • [0b0001]Select data slice [34:0]
  • [0b0010]Select data slice [69:35]
  • [0b0100]Select data slice [104:70]
  • [0b1000]Select data slice [136:105]
  • [0b1111]Select data [136:0]
R_ADR_CTRL_XADR 

R_ADR_CTRL - XADR.

BIST Address Control Register - BIST XADR

R_ADR_CTRL_YADR 

R_ADR_CTRL - YADR.

BIST Address Control Register - BIST YADR

R_ADR_CTRL_PROG_ATTR 

R_ADR_CTRL - PROG_ATTR.

BIST Address Control Register - Program Attribute

  • [0b000]One YE pulse will program one data slice group
  • [0b001]One YE pulse will program two data slice groups
  • [0b010]One YE pulse will program three data slice groups = reserved)
  • [0b011]One YE pulse will program four data slice groups
  • [0b100]One YE pulse will program five data slice groups = reserved)
  • [0b101]One YE pulse will program six data slice groups = reserved)
  • [0b110]One YE pulse will program seven data slice groups = reserved)
  • [0b111]One YE pulse will program eight data slice groups = reserved)
R_DATA_CTRL0_DATA0 

R_DATA_CTRL0 - DATA0.

BIST Data Control 0 Register - BIST Data 0 Low

R_PIN_CTRL_MAS1 

R_PIN_CTRL - MAS1.

BIST Pin Control Register - Mass Erase

R_PIN_CTRL_IFREN 

R_PIN_CTRL - IFREN.

BIST Pin Control Register - IFR Enable

R_PIN_CTRL_IFREN1 

R_PIN_CTRL - IFREN1.

BIST Pin Control Register - IFR1 Enable

R_PIN_CTRL_REDEN 

R_PIN_CTRL - REDEN.

BIST Pin Control Register - Redundancy Block Enable

R_PIN_CTRL_LVE 

R_PIN_CTRL - LVE.

BIST Pin Control Register - Low Voltage Enable

R_PIN_CTRL_PV 

R_PIN_CTRL - PV.

BIST Pin Control Register - Program Verify Enable

R_PIN_CTRL_EV 

R_PIN_CTRL - EV.

BIST Pin Control Register - Erase Verify Enable

R_PIN_CTRL_WIPGM 

R_PIN_CTRL - WIPGM.

BIST Pin Control Register - Program Current

R_PIN_CTRL_WHV 

R_PIN_CTRL - WHV.

BIST Pin Control Register - High Voltage Level

R_PIN_CTRL_WMV 

R_PIN_CTRL - WMV.

BIST Pin Control Register - Medium Voltage Level

R_PIN_CTRL_XE 

R_PIN_CTRL - XE.

BIST Pin Control Register - X Address Enable

R_PIN_CTRL_YE 

R_PIN_CTRL - YE.

BIST Pin Control Register - Y Address Enable

R_PIN_CTRL_SE 

R_PIN_CTRL - SE.

BIST Pin Control Register - Sense Amp Enable

R_PIN_CTRL_ERASE 

R_PIN_CTRL - ERASE.

BIST Pin Control Register - Erase Mode

R_PIN_CTRL_PROG 

R_PIN_CTRL - PROG.

BIST Pin Control Register - Program Mode

R_PIN_CTRL_NVSTR 

R_PIN_CTRL - NVSTR.

BIST Pin Control Register - NVM Store

R_PIN_CTRL_SLM 

R_PIN_CTRL - SLM.

BIST Pin Control Register - Sleep Mode Enable

R_PIN_CTRL_RECALL 

R_PIN_CTRL - RECALL.

BIST Pin Control Register - Recall Trim Code

R_PIN_CTRL_HEM 

R_PIN_CTRL - HEM.

BIST Pin Control Register - HEM Control

R_CNT_LOOP_CTRL_LOOPCNT 

R_CNT_LOOP_CTRL - LOOPCNT.

BIST Loop Count Control Register - Loop Count Control

R_CNT_LOOP_CTRL_LOOPOPT 

R_CNT_LOOP_CTRL - LOOPOPT.

BIST Loop Count Control Register - Loop Option

  • [0b000]Loop is disabled; selected BIST operation is run once
  • [0b001]Loop is enabled; XADR increments by 1 XADR increments by 1 for each new loop. Stops when total loop count meets LOOPCNT+1.
  • [0b010]Loop is enabled; YADR increments by 1 YADR increments by 1 for each new loop. Stops when total loop count meets LOOPCNT+1.
  • [0b011]Loop is enabled; XADR increments by 2 XADR increments by 2 for each new loop. Stops when total loop count meets LOOPCNT+1.
  • [0b100]Loop is enabled; XADR increments by sector XADR increments by 16 for each new loop. Stops when total loop count meets LOOPCNT+1.
R_CNT_LOOP_CTRL_LOOPUNIT 

R_CNT_LOOP_CTRL - LOOPUNIT.

BIST Loop Count Control Register - Loop Time Unit

  • [0b000]Clock cycles
  • [0b001]0.5 usec
  • [0b010]1 usec
  • [0b011]10 usec
  • [0b100]100 usec
  • [0b101]1 msec
  • [0b110]10 msec
  • [0b111]100 msec
R_CNT_LOOP_CTRL_LOOPDLY 

R_CNT_LOOP_CTRL - LOOPDLY.

BIST Loop Count Control Register - Loop Time Delay Scalar

R_TIMER_CTRL_TNVSUNIT 

R_TIMER_CTRL - TNVSUNIT.

BIST Timer Control Register - Tnvs Time Unit

  • [0b000]Clock cycles
  • [0b001]0.5 usec
  • [0b010]1 usec
  • [0b011]10 usec
  • [0b100]100 usec
  • [0b101]1 msec
  • [0b110]10 msec
  • [0b111]100 msec
R_TIMER_CTRL_TNVSDLY 

R_TIMER_CTRL - TNVSDLY.

BIST Timer Control Register - Tnvs Time Delay Scalar

R_TIMER_CTRL_TNVHUNIT 

R_TIMER_CTRL - TNVHUNIT.

BIST Timer Control Register - Tnvh Time Unit

  • [0b000]Clock cycles
  • [0b001]0.5 usec
  • [0b010]1 usec
  • [0b011]10 usec
  • [0b100]100 usec
  • [0b101]1 msec
  • [0b110]10 msec
  • [0b111]100 msec
R_TIMER_CTRL_TNVHDLY 

R_TIMER_CTRL - TNVHDLY.

BIST Timer Control Register - Tnvh Time Delay Scalar

R_TIMER_CTRL_TPGSUNIT 

R_TIMER_CTRL - TPGSUNIT.

BIST Timer Control Register - Tpgs Time Unit

  • [0b000]Clock cycles
  • [0b001]0.5 usec
  • [0b010]1 usec
  • [0b011]10 usec
  • [0b100]100 usec
  • [0b101]1 msec
  • [0b110]10 msec
  • [0b111]100 msec
R_TIMER_CTRL_TPGSDLY 

R_TIMER_CTRL - TPGSDLY.

BIST Timer Control Register - Tpgs Time Delay Scalar

R_TIMER_CTRL_TRCVUNIT 

R_TIMER_CTRL - TRCVUNIT.

BIST Timer Control Register - Trcv Time Unit

  • [0b000]Clock cycles
  • [0b001]0.5 usec
  • [0b010]1 usec
  • [0b011]10 usec
  • [0b100]100 usec
  • [0b101]1 msec
  • [0b110]10 msec
  • [0b111]100 msec
R_TIMER_CTRL_TRCVDLY 

R_TIMER_CTRL - TRCVDLY.

BIST Timer Control Register - Trcv Time Delay Scalar

R_TIMER_CTRL_TLVSUNIT 

R_TIMER_CTRL - TLVSUNIT.

BIST Timer Control Register - Tlvs Time Unit

  • [0b000]Clock cycles
  • [0b001]0.5 usec
  • [0b010]1 usec
  • [0b011]10 usec
  • [0b100]100 usec
  • [0b101]1 msec
  • [0b110]10 msec
  • [0b111]100 msec
R_TIMER_CTRL_TLVSDLY_L 

R_TIMER_CTRL - TLVSDLY_L.

BIST Timer Control Register - Tlvs Time Delay Scalar Low

R_TEST_CTRL_BUSY 

R_TEST_CTRL - BUSY.

BIST Test Control Register - BIST Busy Status

  • [0b0]BIST is idle
  • [0b1]BIST is busy
R_TEST_CTRL_DEBUG 

R_TEST_CTRL - DEBUG.

BIST Test Control Register - BIST Debug Status

R_TEST_CTRL_STATUS0 

R_TEST_CTRL - STATUS0.

BIST Test Control Register - BIST Status 0

  • [0b0]BIST test passed on flash block 0
  • [0b1]BIST test failed on flash block 0
R_TEST_CTRL_STATUS1 

R_TEST_CTRL - STATUS1.

BIST Test Control Register - BIST status 1

  • [0b0]BIST test passed on flash block 1
  • [0b1]BIST test failed on flash block 1
R_TEST_CTRL_DEBUGRUN 

R_TEST_CTRL - DEBUGRUN.

BIST Test Control Register - BIST Continue Debug Run

R_TEST_CTRL_STARTRUN 

R_TEST_CTRL - STARTRUN.

BIST Test Control Register - Run New BIST Operation

R_TEST_CTRL_CMDINDEX 

R_TEST_CTRL - CMDINDEX.

BIST Test Control Register - BIST Command Index = code)

R_TEST_CTRL_DISABLE_IP1 

R_TEST_CTRL - DISABLE_IP1.

BIST Test Control Register - BIST Disable IP1

R_ABORT_LOOP_ABORT_LOOP 

R_ABORT_LOOP - ABORT_LOOP.

BIST Abort Loop Register - Abort Loop

  • [0b0]No effect
  • [0b1]Abort BIST loop commands and force the loop counter to return to 0x0
R_ADR_QUERY_YADRFAIL 

R_ADR_QUERY - YADRFAIL.

BIST Address Query Register - Failing YADR

R_ADR_QUERY_XADRFAIL 

R_ADR_QUERY - XADRFAIL.

BIST Address Query Register - Failing XADR

R_DOUT_QUERY0_DOUTFAIL 

R_DOUT_QUERY0 - DOUTFAIL.

BIST DOUT Query 0 Register - Failing DOUT Low

R_SMW_QUERY_SMWLOOP 

R_SMW_QUERY - SMWLOOP.

BIST SMW Query Register - SMW Total Loop Count

R_SMW_QUERY_SMWLAST 

R_SMW_QUERY - SMWLAST.

BIST SMW Query Register - SMW Last Voltage Setting

R_SMW_SETTING0_SMWPARM0 

R_SMW_SETTING0 - SMWPARM0.

BIST SMW Setting 0 Register - SMW Parameter Set 0

R_SMW_SETTING1_SMWPARM1 

R_SMW_SETTING1 - SMWPARM1.

BIST SMW Setting 1 Register - SMW Parameter Set 1

R_SMP_WHV0_SMPWHV0 

R_SMP_WHV0 - SMPWHV0.

BIST SMP WHV Setting 0 Register - SMP WHV Parameter Set 0

R_SMP_WHV1_SMPWHV1 

R_SMP_WHV1 - SMPWHV1.

BIST SMP WHV Setting 1 Register - SMP WHV Parameter Set 1

R_SME_WHV0_SMEWHV0 

R_SME_WHV0 - SMEWHV0.

BIST SME WHV Setting 0 Register - SME WHV Parameter Set 0

R_SME_WHV1_SMEWHV1 

R_SME_WHV1 - SMEWHV1.

BIST SME WHV Setting 1 Register - SME WHV Parameter Set 1

R_SMW_SETTING2_SMWPARM2 

R_SMW_SETTING2 - SMWPARM2.

BIST SMW Setting 2 Register - SMW Parameter Set 2

R_D_MISR0_DATASIG0 

R_D_MISR0 - DATASIG0.

BIST DIN MISR 0 Register - Data Signature

R_A_MISR0_ADRSIG0 

R_A_MISR0 - ADRSIG0.

BIST Address MISR 0 Register - Address Signature

R_C_MISR0_CTRLSIG0 

R_C_MISR0 - CTRLSIG0.

BIST Control MISR 0 Register - Control Signature

R_SMW_SETTING3_SMWPARM3 

R_SMW_SETTING3 - SMWPARM3.

BIST SMW Setting 3 Register - SMW Parameter Set 3

R_DATA_CTRL1_DATA1 

R_DATA_CTRL1 - DATA1.

BIST Data Control 1 Register - BIST Data 1 Low

R_DATA_CTRL2_DATA2 

R_DATA_CTRL2 - DATA2.

BIST Data Control 2 Register - BIST Data 2 Low

R_DATA_CTRL3_DATA3 

R_DATA_CTRL3 - DATA3.

BIST Data Control 3 Register - BIST Data 3 Low

R_REPAIR0_0_RDIS0_0 

R_REPAIR0_0 - RDIS0_0.

BIST Repair 0 for Block 0 Register - Control Repair 0 in Block 0.

  • [0b0]Repair address is valid
  • [0b1]Repair address is not valid
R_REPAIR0_0_RADR0_0 

R_REPAIR0_0 - RADR0_0.

BIST Repair 0 for Block 0 Register - XADR for Repair 0 in Block 0

R_REPAIR0_1_RDIS0_1 

R_REPAIR0_1 - RDIS0_1.

BIST Repair 1 Block 0 Register - Control Repair 1 in Block 0.

  • [0b0]Repair address is valid
  • [0b1]Repair address is not valid
R_REPAIR0_1_RADR0_1 

R_REPAIR0_1 - RADR0_1.

BIST Repair 1 Block 0 Register - XADR for Repair 1 in Block 0.

R_REPAIR1_0_RDIS1_0 

R_REPAIR1_0 - RDIS1_0.

BIST Repair 0 Block 1 Register - Control Repair 0 in Block 1.

  • [0b0]Repair address is valid
  • [0b1]Repair address is not valid
R_REPAIR1_0_RADR1_0 

R_REPAIR1_0 - RADR1_0.

BIST Repair 0 Block 1 Register - XADR for Repair 0 in Block 1.

R_REPAIR1_1_RDIS1_1 

R_REPAIR1_1 - RDIS1_1.

BIST Repair 1 Block 1 Register - Control Repair 1 in Block 1.

  • [0b0]Repair address is valid
  • [0b1]Repair address is not valid
R_REPAIR1_1_RADR1_1 

R_REPAIR1_1 - RADR1_1.

BIST Repair 1 Block 1 Register - XADR for Repair 1 in Block 1.

R_DATA_CTRL0_EX_DATA0X 

R_DATA_CTRL0_EX - DATA0X.

BIST Data Control 0 Extension Register - BIST Data 0 High

R_TIMER_CTRL_EX_TLVSDLY_H 

R_TIMER_CTRL_EX - TLVSDLY_H.

BIST Timer Control Extension Register - Tlvs Time Delay Scalar High

R_DOUT_QUERY1_DOUT 

R_DOUT_QUERY1 - DOUT.

BIST DOUT Query 1 Register - Failing DOUT High

R_D_MISR1_DATASIG1 

R_D_MISR1 - DATASIG1.

BIST DIN MISR 1 Register - MISR Data Signature High

R_A_MISR1_ADRSIG1 

R_A_MISR1 - ADRSIG1.

BIST Address MISR 1 Register - MISR Address Signature High

R_C_MISR1_CTRLSIG1 

R_C_MISR1 - CTRLSIG1.

BIST Control MISR 1 Register - MISR Control Signature High

R_DATA_CTRL1_EX_DATA1X 

R_DATA_CTRL1_EX - DATA1X.

BIST Data Control 1 Extension Register - BIST Data 1 High

R_DATA_CTRL2_EX_DATA2X 

R_DATA_CTRL2_EX - DATA2X.

BIST Data Control 2 Extension Register - BIST Data 2 High

R_DATA_CTRL3_EX_DATA3X 

R_DATA_CTRL3_EX - DATA3X.

BIST Data Control 3 Extension Register - BIST Data 3 High

SMW_TIMER_OPTION_SMW_CDIVL 

SMW_TIMER_OPTION - SMW_CDIVL.

Clock Divide Scalar for Long Pulse

SMW_TIMER_OPTION_SMW_TVFY 

SMW_TIMER_OPTION - SMW_TVFY.

SMW Timer Option Register - Timer Adjust for Verify

SMW_SETTING_OPTION0_MV_INIT 

SMW_SETTING_OPTION0 - MV_INIT.

SMW Setting Option 0 Register - Medium Voltage Level Select Initial

SMW_SETTING_OPTION0_MV_END 

SMW_SETTING_OPTION0 - MV_END.

SMW Setting Option 0 Register - Medium Voltage Level Select Final

SMW_SETTING_OPTION0_MV_MISC 

SMW_SETTING_OPTION0 - MV_MISC.

SMW Setting Option 0 Register - Medium Voltage Control Misc

SMW_SETTING_OPTION0_IPGM_INIT 

SMW_SETTING_OPTION0 - IPGM_INIT.

SMW Setting Option 0 Register - Program Current Control Initial

SMW_SETTING_OPTION0_IPGM_END 

SMW_SETTING_OPTION0 - IPGM_END.

SMW Setting Option 0 Register - Program Current Control Final

SMW_SETTING_OPTION0_IPGM_MISC 

SMW_SETTING_OPTION0 - IPGM_MISC.

SMW Setting Option 0 Register - Program Current Control Misc

SMW_SETTING_OPTION2_THVS_CTRL 

SMW_SETTING_OPTION2 - THVS_CTRL.

SMW Setting Option 2 Register - Thvs control

SMW_SETTING_OPTION2_TRCV_CTRL 

SMW_SETTING_OPTION2 - TRCV_CTRL.

SMW Setting Option 2 Register - Trcv Control

SMW_SETTING_OPTION2_XTRA_ERS 

SMW_SETTING_OPTION2 - XTRA_ERS.

SMW Setting Option 2 Register - Number of Post Shots for SME

SMW_SETTING_OPTION2_XTRA_PGM 

SMW_SETTING_OPTION2 - XTRA_PGM.

SMW Setting Option 2 Register - Number of Post Shots for SMP

SMW_SETTING_OPTION2_WHV_CNTR 

SMW_SETTING_OPTION2 - WHV_CNTR.

SMW Setting Option 2 Register - WHV Counter

SMW_SETTING_OPTION2_POST_TERS 

SMW_SETTING_OPTION2 - POST_TERS.

SMW Setting Option 2 Register - Post Ters Time

  • [0b000]50 usec
  • [0b001]100 usec
  • [0b010]200 usec
  • [0b011]300 usec
  • [0b100]500 usec
  • [0b101]1 msec
  • [0b110]1.5 msec
  • [0b111]2 msec
SMW_SETTING_OPTION2_POST_TPGM 

SMW_SETTING_OPTION2 - POST_TPGM.

SMW Setting Option 2 Register - Post Tpgm Time

  • [0b00]1 usec
  • [0b01]2 usec
  • [0b10]4 usec
  • [0b11]8 usec
SMW_SETTING_OPTION2_VFY_OPT 

SMW_SETTING_OPTION2 - VFY_OPT.

SMW Setting Option 2 Register - Verify Option

  • [0b00]Skip verify for post shot only, verify for all other shots
  • [0b01]Skip verify for the 1st and post shots
  • [0b10]Skip the 1st, 2nd, and post shots
  • [0b11]Skip verify for all shots
SMW_SETTING_OPTION2_TPGM_OPT 

SMW_SETTING_OPTION2 - TPGM_OPT.

SMW Setting Option 2 Register - Tpgm Option

  • [0b00]Fixed Tpgm for all shots, except post shot
  • [0b01]Increase Tpgm option by 1 for each loop until Tpgm reaches 4 usec
  • [0b10]Increase Tpgm option by 1 for each loop until Tpgm reaches 8 usec
  • [0b11]Unused
SMW_SETTING_OPTION2_MASK0_OPT 

SMW_SETTING_OPTION2 - MASK0_OPT.

SMW Setting Option 2 Register - MASK0_OPT

  • [0b0]Mask programmed bits passing PV until extra shot
  • [0b1]Always program bits even if they pass PV
SMW_SETTING_OPTION2_DIS_PRER 

SMW_SETTING_OPTION2 - DIS_PRER.

SMW Setting Option 2 Register - Disable pre-PV Read before First Program Shot

  • [0b0]Enable pre-PV read before first program shot
  • [0b1]Disable pre-PV read before first program shot
SMW_SETTING_OPTION3_HEM_WHV_CNTR 

SMW_SETTING_OPTION3 - HEM_WHV_CNTR.

SMW Setting Option 3 Register - WHV_COUNTER for HEM-erase Cycle

SMW_SETTING_OPTION3_HEM_MAX_ERS 

SMW_SETTING_OPTION3 - HEM_MAX_ERS.

SMW Setting Option 3 Register - HEM Max Erase Shot Count

SMW_SMP_WHV_OPTION0_SMP_WHV_OPT0 

SMW_SMP_WHV_OPTION0 - SMP_WHV_OPT0.

SMW SMP WHV Option 0 Register - Smart Program WHV Option Low

SMW_SME_WHV_OPTION0_SME_WHV_OPT0 

SMW_SME_WHV_OPTION0 - SME_WHV_OPT0.

SMW SME WHV Option 0 Register - Smart Erase WHV Option Low

SMW_SETTING_OPTION1_TERS_CTRL0 

SMW_SETTING_OPTION1 - TERS_CTRL0.

SMW Setting Option 1 Register - Ters Control

  • [0b000]50 usec
  • [0b001]100 usec
  • [0b010]200 usec
  • [0b011]300 usec
  • [0b100]500 usec
  • [0b101]1 msec
  • [0b110]1.5 msec
  • [0b111]2 msec
SMW_SETTING_OPTION1_TPGM_CTRL 

SMW_SETTING_OPTION1 - TPGM_CTRL.

SMW Setting Option 1 Register - Tpgm Control

  • [0b00]1 usec
  • [0b01]2 usec
  • [0b10]4 usec
  • [0b11]8 usec
SMW_SETTING_OPTION1_TNVS_CTRL 

SMW_SETTING_OPTION1 - TNVS_CTRL.

SMW Setting Option 1 Register - Tnvs Control

  • [0b000]5 usec
  • [0b001]8 usec
  • [0b010]11 usec
  • [0b011]14 usec
  • [0b100]17 usec
  • [0b101]20 usec
  • [0b110]23 usec
  • [0b111]26 usec
SMW_SETTING_OPTION1_TNVH_CTRL 

SMW_SETTING_OPTION1 - TNVH_CTRL.

SMW Setting Option 1 Register - Tnvh Control

  • [0b000]2 usec
  • [0b001]2.5 usec
  • [0b010]3 usec
  • [0b011]3.5 usec
  • [0b100]4 usec
  • [0b101]4.5 usec
  • [0b110]5 usec
  • [0b111]5.5 usec
SMW_SETTING_OPTION1_TPGS_CTRL 

SMW_SETTING_OPTION1 - TPGS_CTRL.

SMW Setting Option 1 Register - Tpgs Control

  • [0b000]1 usec
  • [0b001]2 usec
  • [0b010]3 usec
  • [0b011]4 usec
  • [0b100]5 usec
  • [0b101]6 usec
  • [0b110]7 usec
  • [0b111]8 usec
SMW_SETTING_OPTION1_MAX_ERASE 

SMW_SETTING_OPTION1 - MAX_ERASE.

SMW Setting Option 1 Register - Number of Erase Shots

SMW_SETTING_OPTION1_MAX_PROG 

SMW_SETTING_OPTION1 - MAX_PROG.

SMW Setting Option 1 Register - Number of Program Shots

SMW_SMP_WHV_OPTION1_SMP_WHV_OPT1 

SMW_SMP_WHV_OPTION1 - SMP_WHV_OPT1.

SMW SMP WHV Option 1 Register - Smart Program WHV Option High

SMW_SME_WHV_OPTION1_SME_WHV_OPT1 

SMW_SME_WHV_OPTION1 - SME_WHV_OPT1.

SMW SME WHV Option 1 Register - Smart Erase WHV Option High

REPAIR0_0_RDIS0_0 

REPAIR0_0 - RDIS0_0.

FMU Repair 0 Block 0 Register - RDIS0_0

  • [0b0]Repair address is valid
  • [0b1]Repair address is not valid
REPAIR0_0_RADR0_0 

REPAIR0_0 - RADR0_0.

FMU Repair 0 Block 0 Register - RADR0_0

REPAIR0_1_RDIS0_1 

REPAIR0_1 - RDIS0_1.

FMU Repair 1 Block 0 Register - RDIS0_1

  • [0b0]Repair address is valid
  • [0b1]Repair address is not valid
REPAIR0_1_RADR0_1 

REPAIR0_1 - RADR0_1.

FMU Repair 1 Block 0 Register - RADR0_1

REPAIR1_0_RDIS1_0 

REPAIR1_0 - RDIS1_0.

FMU Repair 0 Block 1 Register - RDIS1_0

  • [0b0]Repair address is valid
  • [0b1]Repair address is not valid
REPAIR1_0_RADR1_0 

REPAIR1_0 - RADR1_0.

FMU Repair 0 Block 1 Register - RADR1_0

REPAIR1_1_RDIS1_1 

REPAIR1_1 - RDIS1_1.

FMU Repair 1 Block 1 Register - RDIS1_1

  • [0b0]Repair address is valid
  • [0b1]Repair address is not valid
REPAIR1_1_RADR1_1 

REPAIR1_1 - RADR1_1.

FMU Repair 1 Block 1 Register - RADR1_1

SMW_HB_SIGNALS_SMW_ARRAY 

SMW_HB_SIGNALS - SMW_ARRAY.

SMW HB Signals Register - SMW Region Select

  • [0b000]Main array
  • [0b001]IFR space only or main = and REDEN space) with IFR space for mass erase
  • [0b010]IFR1 space
  • [0b100]REDEN space
SMW_HB_SIGNALS_USER_IFREN1 

SMW_HB_SIGNALS - USER_IFREN1.

SMW HB Signals Register - IFR1 Enable

  • [0b0]IFREN1 input to the flash array is driven LOW
  • [0b1]IFREN1 input to the flash array is driven HIGH
SMW_HB_SIGNALS_USER_PV 

SMW_HB_SIGNALS - USER_PV.

SMW HB Signals Register - Program Verify

  • [0b0]PV input to the flash array is driven LOW
  • [0b1]PV input to the flash array is driven HIGH
SMW_HB_SIGNALS_USER_EV 

SMW_HB_SIGNALS - USER_EV.

SMW HB Signals Register - Erase Verify

  • [0b0]EV input to the flash array is driven LOW
  • [0b1]EV input to the flash array is driven HIGH
SMW_HB_SIGNALS_USER_IFREN 

SMW_HB_SIGNALS - USER_IFREN.

SMW HB Signals Register - IFR Enable

  • [0b0]IFREN input to the flash array is driven LOW
  • [0b1]IFREN input to the flash array is driven HIGH
SMW_HB_SIGNALS_USER_REDEN 

SMW_HB_SIGNALS - USER_REDEN.

SMW HB Signals Register - Repair Read Enable

  • [0b0]REDEN input to the flash array is driven LOW
  • [0b1]REDEN input to the flash array is driven HIGH
SMW_HB_SIGNALS_USER_HEM 

SMW_HB_SIGNALS - USER_HEM.

SMW HB Signals Register - High Endurance Enable

  • [0b0]HEM input to SMW / BIST PIN_CTRL[24] is driven LOW
  • [0b1]HEM input to SMW / BIST PIN_CTRL[24] is driven HIGH
BIST_DUMP_CTRL_BIST_DONE 

BIST_DUMP_CTRL - BIST_DONE.

BIST Datadump Control Register - BIST Done

  • [0b0]The BIST = or data dump) is running
  • [0b1]The BIST = or data dump) has completed
BIST_DUMP_CTRL_BIST_FAIL 

BIST_DUMP_CTRL - BIST_FAIL.

BIST Datadump Control Register - BIST Fail

  • [0b0]The last BIST operation completed successfully = or could not fail)
  • [0b1]The last BIST operation failed
BIST_DUMP_CTRL_DATADUMP 

BIST_DUMP_CTRL - DATADUMP.

BIST Datadump Control Register - Data Dump Enable

BIST_DUMP_CTRL_DATADUMP_TRIG 

BIST_DUMP_CTRL - DATADUMP_TRIG.

BIST Datadump Control Register - Data Dump Trigger

BIST_DUMP_CTRL_DATADUMP_PATT 

BIST_DUMP_CTRL - DATADUMP_PATT.

BIST Datadump Control Register - Data Dump Pattern Select

  • [0b00]All ones
  • [0b01]All zeroes
  • [0b10]Checkerboard
  • [0b11]Inverse checkerboard
BIST_DUMP_CTRL_DATADUMP_MRGEN 

BIST_DUMP_CTRL - DATADUMP_MRGEN.

BIST Datadump Control Register - Data Dump Margin Enable

  • [0b0]Normal read pulse shape
  • [0b1]Margin read pulse shape
BIST_DUMP_CTRL_DATADUMP_MRGTYPE 

BIST_DUMP_CTRL - DATADUMP_MRGTYPE.

BIST Datadump Control Register - Data Dump Margin Type

  • [0b0]DIN method used
  • [0b1]TM method used
ATX_PIN_CTRL_TM_TO_ATX 

ATX_PIN_CTRL - TM_TO_ATX.

ATX Pin Control Register - TM to ATX

  • [0b00000001]TM[0] to ATX0
  • [0b00000010]TM[1] to ATX0
  • [0b00000100]TM[2] to ATX0
  • [0b00001000]TM[3] to ATX0
  • [0b00010000]TM[0] to ATX1
  • [0b00100000]TM[1] to ATX1
  • [0b01000000]TM[2] to ATX1
  • [0b10000000]TM[3] to ATX1
FAILCNT_FAILCNT 

FAILCNT - FAILCNT.

Fail Count Register - Fail Count

PGM_PULSE_CNT0_PGM_CNT0 

PGM_PULSE_CNT0 - PGM_CNT0.

Block 0 Program Pulse Count Register - Program Pulse Count

PGM_PULSE_CNT1_PGM_CNT1 

PGM_PULSE_CNT1 - PGM_CNT1.

Block 1 Program Pulse Count Register - Program Pulse Count

ERS_PULSE_CNT_ERS_CNT0 

ERS_PULSE_CNT - ERS_CNT0.

Erase Pulse Count Register - Block 0 Erase Pulse Count

ERS_PULSE_CNT_ERS_CNT1 

ERS_PULSE_CNT - ERS_CNT1.

Erase Pulse Count Register - Block 1 Erase Pulse Count

MAX_PULSE_CNT_LAST_PCNT 

MAX_PULSE_CNT - LAST_PCNT.

Maximum Pulse Count Register - Last SMW Operation's Pulse Count

MAX_PULSE_CNT_MAX_ERS_CNT 

MAX_PULSE_CNT - MAX_ERS_CNT.

Maximum Pulse Count Register - Maximum Erase Pulse Count

MAX_PULSE_CNT_MAX_PGM_CNT 

MAX_PULSE_CNT - MAX_PGM_CNT.

Maximum Pulse Count Register - Maximum Program Pulse Count

PORT_CTRL_BDONE_SEL 

PORT_CTRL - BDONE_SEL.

Port Control Register - BIST Done Select

  • [0b00]Select internal bist_done signal from current module instantiation
  • [0b01]Select ipt_bist_fail signal from current module instantiation
  • [0b10]Select ipt_bist_done signal from other module instantiation
  • [0b11]Select AND of internal bist_done signal from current module instantiation with ipt_bist_done signal from other module instantiation
PORT_CTRL_BSDO_SEL 

PORT_CTRL - BSDO_SEL.

Port Control Register - BIST Serial Data Output Select

  • [0b00]Select internal bist_sdo signal from current module instantiation
  • [0b01]Select ipt_bist_done signal from current module instantiation
  • [0b10]Select ipt_bist_sdo signal from other module instantiation
  • [0b11]Select ipt_bist_done signal from other module instantiation

◆ Shift

enum struct mcxa153::chip::fmu::Shift : unsigned int
strong

FMU Register Bit Fields Shift Position Enumeration FMU暫存器位元欄位位移位置列舉

列舉值
FSTAT_FAIL 

FSTAT - FAIL Flash Status Register - Command Fail Flag 快閃記憶體狀態暫存器 - 命令失敗旗標

  • [0b0] Error not detected 未檢測到錯誤
  • [0b1] Error detected 檢測到錯誤
FSTAT_CMDABT 

FSTAT - CMDABT Flash Status Register - Command Abort Flag 快閃記憶體狀態暫存器 - 命令中止旗標

  • [0b0] No command abort detected 未檢測到命令中止
  • [0b1] Command abort detected 檢測到命令中止
FSTAT_PVIOL 

FSTAT - PVIOL Flash Status Register - Command Protection Violation Flag 快閃記憶體狀態暫存器 - 命令保護違規旗標

  • [0b0] No protection violation detected 未檢測到保護違規
  • [0b1] Protection violation detected 檢測到保護違規
FSTAT_ACCERR 

FSTAT - ACCERR
Flash Status Register - Command Access Error Flag 快閃記憶體狀態暫存器 - 命令存取錯誤旗標

  • [0b0] No access error detected 未檢測到存取錯誤
  • [0b1] Access error detected 檢測到存取錯誤
FSTAT_CWSABT 

FSTAT - CWSABT Flash Status Register - Command Write Sequence Abort Flag 快閃記憶體狀態暫存器 - 命令寫入序列中止旗標

  • [0b0] Command write sequence not aborted 命令寫入序列未中止
  • [0b1] Command write sequence aborted 命令寫入序列已中止
FSTAT_CCIF 

FSTAT - CCIF Flash Status Register - Command Complete Interrupt Flag 快閃記憶體狀態暫存器 - 命令完成中斷旗標

  • [0b0] Flash command or initialization in progress 快閃命令或初始化進行中
  • [0b1] Flash command or initialization has completed 快閃命令或初始化已完成
FSTAT_CMDPRT 

FSTAT - CMDPRT Flash Status Register - Command Protection Level 快閃記憶體狀態暫存器 - 命令保護等級

  • [0b00] Secure, normal access 安全，正常存取
  • [0b01] Secure, privileged access 安全，特權存取
  • [0b10] Nonsecure, normal access 非安全，正常存取
  • [0b11] Nonsecure, privileged access 非安全，特權存取
FSTAT_CMDP 

FSTAT - CMDP Flash Status Register - Command Protection Status Flag 快閃記憶體狀態暫存器 - 命令保護狀態旗標

  • [0b0] Command protection level and domain ID are stale 命令保護等級和域ID已過期
  • [0b1] Command protection level (CMDPRT) and domain ID (CMDDID) are set 命令保護等級（CMDPRT）和域ID（CMDDID）已設置
FSTAT_CMDDID 

FSTAT - CMDDID Flash Status Register - Command Domain ID 快閃記憶體狀態暫存器 - 命令域ID.

FSTAT_DFDIF 

FSTAT - DFDIF Flash Status Register - Double Bit Fault Detect Interrupt Flag 快閃記憶體狀態暫存器 - 雙位錯誤檢測中斷旗標

  • [0b0] Double bit fault not detected during a valid flash read access from the FMC 在FMC的有效快閃讀取存取期間未檢測到雙位錯誤
  • [0b1] Double bit fault detected (or FCTRL[FDFD] is set) during a valid flash read access from the FMC 在FMC的有效快閃讀取存取期間檢測到雙位錯誤（或FCTRL[FDFD]已設置）
FSTAT_SALV_USED 

FSTAT - SALV_USED Flash Status Register - Salvage Used for Erase operation 快閃記憶體狀態暫存器 - 用於擦除操作的挽救

  • [0b0] Salvage not used during the last operation 在最後一次操作期間未使用挽救
  • [0b1] Salvage used during the last erase operation 在最後一次擦除操作期間使用了挽救
FSTAT_PEWEN 

FSTAT - PEWEN Flash Status Register - Program-Erase Write Enable Control 快閃記憶體狀態暫存器 - 程式-擦除寫入啟用控制

  • [0b00] Writes are not enabled 未啟用寫入
  • [0b01] Writes are enabled for one flash or IFR phrase (phrase programming, sector erase) 啟用寫入一個快閃或IFR短語（短語程式，扇區擦除）
  • [0b10] Writes are enabled for one flash or IFR page (page programming) 啟用寫入一個快閃或IFR頁面（頁面程式）
  • [0b11] Reserved 保留
FSTAT_PERDY 

FSTAT - PERDY Flash Status Register - Program/Erase Ready Control/Status Flag 快閃記憶體狀態暫存器 - 程式/擦除準備控制/狀態旗標

  • [0b0] Program or sector erase command operation is not stalled 程式或扇區擦除命令操作未停滯
  • [0b1] Program or sector erase command operation is stalled 程式或扇區擦除命令操作已停滯
FCNFG_CCIE 

FCNFG - CCIE Flash Configuration Register - Command Complete Interrupt Enable 快閃記憶體配置暫存器 - 命令完成中斷啟用

  • [0b0] Command complete interrupt disabled 命令完成中斷已禁用
  • [0b1] Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set. 命令完成中斷已啟用。每當設置FSTAT[CCIF]旗標時，會生成中斷請求。
FCNFG_ERSREQ 

FCNFG - ERSREQ Flash Configuration Register - Mass Erase (Erase All) Request 快閃記憶體配置暫存器 - 大量擦除（全部擦除）請求

  • [0b0] No request or request complete 無請求或請求完成
  • [0b1] Request to run the Mass Erase operation 請求執行大量擦除操作
FCNFG_DFDIE 

FCNFG - DFDIE Flash Configuration Register - Double Bit Fault Detect Interrupt Enable 快閃記憶體配置暫存器 - 雙位錯誤檢測中斷啟用

  • [0b0] Double bit fault detect interrupt disabled 雙位錯誤檢測中斷已禁用
  • [0b1] Double bit fault detect interrupt enabled; an interrupt request is generated whenever the FSTAT[DFDIF] flag is set 雙位錯誤檢測中斷已啟用；每當設置FSTAT[DFDIF]旗標時，會生成中斷請求
FCNFG_ERSIEN0 

FCNFG - ERSIEN0 Flash Configuration Register - Erase IFR Sector Enable - Block 0 快閃記憶體配置暫存器 - 擦除IFR扇區啟用 - 區塊0.

  • [0b0000] Block 0 IFR Sector X is protected from erase by ERSSCR command 區塊0 IFR扇區X受ERSSCR命令保護免於擦除
  • [0b0001] Block 0 IFR Sector X is not protected from erase by ERSSCR command 區塊0 IFR扇區X未受ERSSCR命令保護免於擦除
FCNFG_ERSIEN1 

FCNFG - ERSIEN1 Flash Configuration Register - Erase IFR Sector Enable - Block 1 (for dual block configs) 快閃記憶體配置暫存器 - 擦除IFR扇區啟用 - 區塊1（適用於雙區塊配置）

  • [0b0000] Block 1 IFR Sector X is protected from erase by ERSSCR command 區塊1 IFR扇區X受ERSSCR命令保護免於擦除
  • [0b0001] Block 1 IFR Sector X is not protected from erase by ERSSCR command 區塊1 IFR扇區X未受ERSSCR命令保護免於擦除
FCTRL_RWSC 

FCTRL - RWSC Flash Control Register - Read Wait-State Control 快閃記憶體控制暫存器 - 讀取等待狀態控制

  • [0b0000] no additional wait-states are added (single cycle access) 未添加額外的等待狀態（單周期存取）
  • [0b0001] 1 additional wait-state is added 添加1個額外的等待狀態
  • [0b0010] 2 additional wait-states are added 添加2個額外的等待狀態
  • [0b0011] 3 additional wait-states are added 添加3個額外的等待狀態
  • [0b0100] 4 additional wait-states are added 添加4個額外的等待狀態
  • [0b0101] 5 additional wait-states are added 添加5個額外的等待狀態
  • [0b0110] 6 additional wait-states are added 添加6個額外的等待狀態
  • [0b0111] 7 additional wait-states are added 添加7個額外的等待狀態
  • [0b1000] 8 additional wait-states are added 添加8個額外的等待狀態
  • [0b1001] 9 additional wait-states are added 添加9個額外的等待狀態
  • [0b1010] 10 additional wait-states are added 添加10個額外的等待狀態
  • [0b1011] 11 additional wait-states are added 添加11個額外的等待狀態
  • [0b1100] 12 additional wait-states are added 添加12個額外的等待狀態
  • [0b1101] 13 additional wait-states are added 添加13個額外的等待狀態
  • [0b1110] 14 additional wait-states are added 添加14個額外的等待狀態
  • [0b1111] 15 additional wait-states are added 添加15個額外的等待狀態
FCTRL_LSACTIVE 

FCTRL - LSACTIVE Flash Control Register - Low Speed Active Mode 快閃記憶體控制暫存器 - 低速活動模式

  • [0b0] Full speed active mode requested 請求全速活動模式
  • [0b1] Low speed active mode requested 請求低速活動模式
FCTRL_FDFD 

FCTRL - FDFD Flash Control Register - Force Double Bit Fault Detect 快閃記憶體控制暫存器 - 強制雙位錯誤檢測

  • [0b0] FSTAT[DFDIF] sets only if a double bit fault is detected during a valid flash read access from the FMC 僅在FMC的有效快閃讀取存取期間檢測到雙位錯誤時設置FSTAT[DFDIF]
  • [0b1] FSTAT[DFDIF] sets during any valid flash read access from the FMC; an interrupt request is generated if the DFDIE bit is set 在FMC的任何有效快閃讀取存取期間設置FSTAT[DFDIF]；如果設置了DFDIE位，則生成中斷請求
FCTRL_ABTREQ 

FCTRL - ABTREQ Flash Control Register - Abort Request 快閃記憶體控制暫存器 - 中止請求

  • [0b0] No request to abort a command write sequence 無中止命令寫入序列的請求
  • [0b1] Request to abort a command write sequence 請求中止命令寫入序列
FTEST_TMECTL 

FCTRL - TMECTL Flash Test Register - Test Mode Entry Control 快閃記憶體測試暫存器 - 測試模式進入控制

  • [0b0] FTEST register always reads 0 and writes to FTEST are ignored FTEST暫存器始終讀取0，對FTEST的寫入被忽略
  • [0b1] FTEST register is readable and can be written to enable writability of TME FTEST暫存器可讀且可寫以啟用TME的可寫性
FTEST_TMEWR 

FCTRL - TMEWR Flash Test Register - Test Mode Entry Writable 快閃記憶體測試暫存器 - 測試模式進入可寫性

  • [0b0] TME bit is not writable TME位不可寫
  • [0b1] TME bit is writable TME位可寫
FTEST_TME 

FCTRL - TME Flash Test Register - Test Mode Entry 快閃記憶體測試暫存器 - 測試模式進入

  • [0b0] Test mode entry not requested 未請求進入測試模式
  • [0b1] Test mode entry requested 請求進入測試模式
FTEST_TMODE 

FCTRL - TMODE Flash Test Register - Test Mode Status 快閃記憶體測試暫存器 - 測試模式狀態

  • [0b0] Test mode not active 測試模式未激活
  • [0b1] Test mode active 測試模式已激活
FTEST_TMELOCK 

FCTRL - TMELOCK Flash Test Register - Test Mode Entry Lock 快閃記憶體測試暫存器 - 測試模式進入鎖定

  • [0b0] FTEST register not locked from accepting writes FTEST暫存器未鎖定以接受寫入
  • [0b1] FTEST register locked from accepting writes FTEST暫存器已鎖定以接受寫入
FCCOB0_CMDCODE 

FCCOB0 - CMDCODE Flash Command Control 0 Register - Command code 快閃記憶體命令控制0暫存器 - 命令代碼

FCCOB1_CMDOPT 

FCCOB1 - CMDOPT Flash Command Control 1 Register - Command options 快閃記憶體命令控制1暫存器 - 命令選項

FCCOB2_CMDADDR 

FCCOB2 - CMDADDR Flash Command Control 2 Register - Command starting address 快閃記憶體命令控制2暫存器 - 命令起始地址

FCCOB3_CMDADDRE 

FCCOB3 - CMDADDRE Flash Command Control 3 Register - Command ending address 快閃記憶體命令控制3暫存器 - 命令結束地址

FCCOB4_CMDDATA0 

FCCOB4 - CMDDATA0 Flash Command Control 4 Register - Command data word 0 快閃記憶體命令控制4暫存器 - 命令數據字0.

FCCOB5_CMDDATA1 

FCCOB5 - CMDDATA1 Flash Command Control 5 Register - Command data word 1 快閃記憶體命令控制5暫存器 - 命令數據字1.

FCCOB6_CMDDATA2 

FCCOB6 - CMDDATA2 Flash Command Control 6 Register - Command data word 2 快閃記憶體命令控制6暫存器 - 命令數據字2.

FCCOB7_CMDDATA3 

FCCOB7 - CMDDATA3 Flash Command Control 7 Register - Command data word 3 快閃記憶體命令控制7暫存器 - 命令數據字3.

RESET_STATUS_ARY_TRIM_DONE 

RESET_STATUS - ARY_TRIM_DONE FMU Initialization Tracking Register - Array Trim Complete FMU初始化跟踪暫存器 - 數組修剪完成

  • [0b0] Recall register load operation has not been completed 回憶暫存器加載操作尚未完成
  • [0b1] Recall register load operation has completed 回憶暫存器加載操作已完成
RESET_STATUS_FMU_PARM_EN 

RESET_STATUS - FMU_PARM_EN FMU Initialization Tracking Register - Status of the C0DE_C0DEh check to enable loading of the FMU parameters FMU初始化跟踪暫存器 - C0DE_C0DEh檢查的狀態以啟用加載FMU參數

  • [0b0] C0DE_C0DEh check not attempted 未嘗試C0DE_C0DEh檢查
  • [0b1] C0DE_C0DEh check completed C0DE_C0DEh檢查已完成
RESET_STATUS_FMU_PARM_DONE 

RESET_STATUS - FMU_PARM_DONE FMU Initialization Tracking Register - FMU Register Load Complete FMU初始化跟踪暫存器 - FMU暫存器加載完成

  • [0b0] FMU registers have not been loaded FMU暫存器尚未加載
  • [0b1] FMU registers have been loaded FMU暫存器已加載
RESET_STATUS_SOC_TRIM_EN 

RESET_STATUS - SOC_TRIM_EN FMU Initialization Tracking Register - Status of the C0DE_C0DEh check to enable loading of the SoC trim settings FMU初始化跟踪暫存器 - C0DE_C0DEh檢查的狀態以啟用加載SoC修剪設置

  • [0b0] C0DE_C0DEh check not attempted 未嘗試C0DE_C0DEh檢查
  • [0b1] C0DE_C0DEh check completed C0DE_C0DEh檢查已完成
RESET_STATUS_SOC_TRIM_ECC 

RESET_STATUS - SOC_TRIM_ECC FMU Initialization Tracking Register - Status of the C0DE_C0DEh check for enabling ECC decoder during reads of SoC trim settings FMU初始化跟踪暫存器 - C0DE_C0DEh檢查的狀態以啟用在讀取SoC修剪設置期間的ECC解碼器

  • [0b0] C0DE_C0DEh check failed C0DE_C0DEh檢查失敗
  • [0b1] C0DE_C0DEh check passed C0DE_C0DEh檢查通過
RESET_STATUS_SOC_TRIM_DONE 

RESET_STATUS - SOC_TRIM_DONE FMU Initialization Tracking Register - SoC Trim Complete FMU初始化跟踪暫存器 - SoC修剪完成

  • [0b0] SoC Trim registers have not been updated SoC修剪暫存器尚未更新
  • [0b1] All SoC Trim registers have been updated 所有SoC修剪暫存器已更新
RESET_STATUS_RPR_DONE 

RESET_STATUS - RPR_DONE FMU Initialization Tracking Register - Array Repair Complete FMU初始化跟踪暫存器 - 數組修復完成

  • [0b0] Repair registers have not been loaded 修復暫存器尚未加載
  • [0b1] Repair registers have been loaded 修復暫存器已加載
RESET_STATUS_INIT_DONE 

RESET_STATUS - INIT_DONE FMU Initialization Tracking Register - Initialization Done FMU初始化跟踪暫存器 - 初始化完成

  • [0b0] All initialization steps did not complete 所有初始化步驟未完成
  • [0b1] All initialization steps completed 所有初始化步驟已完成
RESET_STATUS_RST_SF_ERR 

RESET_STATUS - RST_SF_ERR FMU Initialization Tracking Register - ECC Single Fault during Reset Recovery FMU初始化跟踪暫存器 - 在重置恢復期間的ECC單位錯誤

  • [0b0] No single-bit faults detected during initialization 在初始化期間未檢測到單位錯誤
  • [0b1] At least one single ECC fault was detected during initialization 在初始化期間檢測到至少一個ECC單位錯誤
RESET_STATUS_RST_DF_ERR 

RESET_STATUS - RST_DF_ERR FMU Initialization Tracking Register - ECC Double Fault during Reset Recovery FMU初始化跟踪暫存器 - 在重置恢復期間的ECC雙位錯誤

  • [0b0] No double-bit faults detected during initialization 在初始化期間未檢測到雙位錯誤
  • [0b1] Double-bit ECC fault was detected during initialization 在初始化期間檢測到ECC雙位錯誤
RESET_STATUS_SOC_TRIM_DF_ERR 

RESET_STATUS - SOC_TRIM_DF_ERR FMU Initialization Tracking Register - ECC Double Fault during load of SoC Trim phrases FMU初始化跟踪暫存器 - 在加載SoC修剪短語期間的ECC雙位錯誤

RESET_STATUS_RST_PATCH_LD 

RESET_STATUS - RST_PATCH_LD FMU Initialization Tracking Register - Reset Patch Required FMU初始化跟踪暫存器 - 需要重置補丁

  • [0b0] No patch required to be loaded during reset 在重置期間不需要加載補丁
  • [0b1] Patch loaded during reset 在重置期間加載了補丁
RESET_STATUS_RECALL_DATA_MISMATCH 

RESET_STATUS - RECALL_DATA_MISMATCH FMU Initialization Tracking Register - Recall Data Mismatch FMU初始化跟踪暫存器 - 回憶數據不匹配

  • [0b0] Data read towards end of reset matched data read for Recall 在重置結束時讀取的數據與回憶讀取的數據匹配
  • [0b1] Data read towards end of reset did not match data read for recall 在重置結束時讀取的數據與回憶讀取的數據不匹配
MCTL_COREHLD 

MCTL - COREHLD FMU Control Register - Core Hold FMU控制暫存器 - 核心保持

  • [0b0] CPU access is allowed 允許CPU存取
  • [0b1] CPU access must be blocked 必須阻止CPU存取
MCTL_LSACT_EN 

MCTL - LSACT_EN FMU Control Register - LSACTIVE Feature Enable FMU控制暫存器 - LSACTIVE功能啟用

  • [0b0] LSACTIVE feature disabled completely: FCTRL[LSACTIVE] is forced low and no longer writable, LVE cannot assert at the TSMC array interface. LSACTIVE功能完全禁用：FCTRL[LSACTIVE]被強制為低且不再可寫，LVE無法在TSMC數組接口上斷言。
  • [0b1] LSACTIVE feature fully enabled and controllable by SoC and internal UINT SM. LSACTIVE功能完全啟用並可由SoC和內部UINT SM控制。
MCTL_LSACTWREN 

MCTL - LSACTWREN FMU Control Register - LSACTIVE Write Enable FMU控制暫存器 - LSACTIVE寫入啟用

  • [0b0] Unrestricted write access allowed 允許不受限制的寫入存取
  • [0b1] Write access while CMP set must match CMDDID and CMDPRT 在設置CMP時的寫入存取必須匹配CMDDID和CMDPRT
MCTL_MASTER_REPAIR_EN 

MCTL - MASTER_REPAIR_EN FMU Control Register - Master Repair Enable FMU控制暫存器 - 主修復啟用

  • [0b0] Repair disabled 修復已禁用
  • [0b1] Repair enable determined by bit 0 of each REPAIR register 修復啟用由每個REPAIR暫存器的位0確定
MCTL_RFCMDEN 

MCTL - RFCMDEN FMU Control Register - RF Active Command Enable Control FMU控制暫存器 - RF活動命令啟用控制

  • [0b0] Flash commands blocked (CCIF not writable) 快閃命令被阻止（CCIF不可寫）
  • [0b1] Flash commands allowed 允許快閃命令
MCTL_CWSABTEN 

MCTL - CWSABTEN FMU Control Register - Command Write Sequence Abort Enable FMU控制暫存器 - 命令寫入序列中止啟用

  • [0b0] CWS abort feature is disabled CWS中止功能已禁用
  • [0b1] CWS abort feature is enabled CWS中止功能已啟用
MCTL_MRGRDDIS 

MCTL - MRGRDDIS FMU Control Register - Margin Read Disable FMU控制暫存器 - 邊際讀取禁用

  • [0b0] Margin Read Settings are enabled 邊際讀取設置已啟用
  • [0b1] Margin Read Settings are disabled 邊際讀取設置已禁用
MCTL_MRGRD0 

MCTL - MRGRD0 FMU Control Register - Margin Read Setting for Program FMU控制暫存器 - 用於程式的邊際讀取設置

MCTL_MRGRD1 

MCTL - MRGRD1 FMU Control Register - Margin Read Setting for Erase FMU控制暫存器 - 用於擦除的邊際讀取設置

MCTL_ERSAACK 

MCTL - ERSAACK FMU Control Register - Mass Erase (Erase All) Acknowledge FMU控制暫存器 - 大量擦除（全部擦除）確認

  • [0b0] Mass Erase operation is not active (operation has completed or has not started) 大量擦除操作未激活（操作已完成或尚未開始）
  • [0b1] Mass Erase operation is active (controller acknowledges that the soc_ersall_req input is asserted and will continue with the operation) 大量擦除操作已激活（控制器確認soc_ersall_req輸入已斷言並將繼續操作）
MCTL_SCAN_OBS 

MCTL - SCAN_OBS FMU Control Register - Scan Observability Control FMU控制暫存器 - 掃描可觀察性控制

  • [0b0] Normal functional behavior 正常功能行為
  • [0b1] Enables observation of signals that may otherwise be ATPG untestable 啟用對可能無法進行ATPG測試的信號的觀察
MCTL_BIST_CTL 

MCTL - BIST_CTL FMU Control Register - BIST IP Control FMU控制暫存器 - BIST IP控制

  • [0b0] BIST IP disabled BIST IP已禁用
  • [0b1] BIST IP enabled BIST IP已啟用
MCTL_SMWR_CTL 

MCTL - SMWR_CTL FMU Control Register - SMWR IP Control FMU控制暫存器 - SMWR IP控制

  • [0b0] SMWR IP disabled SMWR IP已禁用
  • [0b1] SMWR IP enabled SMWR IP已啟用
MCTL_SALV_DIS 

MCTL - SALV_DIS FMU Control Register - Salvage Disable FMU控制暫存器 - 挽救禁用

  • [0b0] Salvage enabled (ECC used during erase verify) 挽救已啟用（在擦除驗證期間使用ECC）
  • [0b1] Salvage disabled (ECC not used during erase verify) 挽救已禁用（在擦除驗證期間未使用ECC）
MCTL_SOC_ECC_CTL 

MCTL - SOC_ECC_CTL FMU Control Register - SOC ECC Control FMU控制暫存器 - SOC ECC控制

  • [0b0] ECC is enabled for SOC read access ECC已啟用以進行SOC讀取存取
  • [0b1] ECC is disabled for SOC read access ECC已禁用以進行SOC讀取存取
MCTL_FMU_ECC_CTL 

MCTL - FMU_ECC_CTL FMU Control Register - FMU ECC Control FMU控制暫存器 - FMU ECC控制

  • [0b0] ECC is enabled for FMU program operations ECC已啟用以進行FMU程式操作
  • [0b1] ECC is disabled for FMU program operations ECC已禁用以進行FMU程式操作
MCTL_BIST_PWR_DIS 

MCTL - BIST_PWR_DIS FMU Control Register - BIST Power Mode Disable FMU控制暫存器 - BIST電源模式禁用

  • [0b0] BIST DFT logic has full control of SLM and LVE when BIST is enabled (including during commands) 當啟用BIST時，BIST DFT邏輯完全控制SLM和LVE（包括在命令期間）
  • [0b1] BIST DFT logic has no control of SLM and LVE; power mode RTL is in complete control of SLM and LVE values BIST DFT邏輯無法控制SLM和LVE；電源模式RTL完全控制SLM和LVE值
MCTL_OSC_H 

MCTL - OSC_H FMU Control Register - Oscillator control FMU控制暫存器 - 振盪器控制

  • [0b0] Use APB clock 使用APB時鐘
  • [0b1] Use a known fixed-frequency clock, e.g. 12 MHz 使用已知固定頻率時鐘，例如12 MHz
BSEL_GEN_SBSEL_GEN 

BSEL_GEN - SBSEL_GEN FMU Block Select Generation Register - Generated SBSEL FMU區塊選擇生成暫存器 - 生成的SBSEL.

BSEL_GEN_MBSEL_GEN 

BSEL_GEN - MBSEL_GEN FMU Block Select Generation Register - Generated MBSEL FMU區塊選擇生成暫存器 - 生成的MBSEL.

PWR_OPT_PD_CDIV 

PWR_OPT - PD_CDIV Power Mode Options Register - Power Down Clock Divider Setting 電源模式選項暫存器 - 電源關閉時鐘分頻器設置

PWR_OPT_SLM_COUNT 

PWR_OPT - SLM_COUNT Power Mode Options Register - Sleep Recovery Timer Count 電源模式選項暫存器 - 睡眠恢復計時器計數

PWR_OPT_PD_TIMER_EN 

PWR_OPT - PD_TIMER_EN Power Mode Options Register - Power Down BIST Timer Enable 電源模式選項暫存器 - 電源關閉BIST計時器啟用

  • [0b0] BIST timer is not triggered during Power Down recovery 在電源關閉恢復期間未觸發BIST計時器
  • [0b1] BIST timer is triggered during Power Down recovery (default behavior) 在電源關閉恢復期間觸發BIST計時器（默認行為）
CMD_CHECK_ALIGNFAIL_PHR 

CMD_CHECK - ALIGNFAIL_PHR FMU Command Check Register - Phrase Alignment Fail FMU命令檢查暫存器 - 短語對齊失敗

  • [0b0] The address is phrase-aligned 地址已短語對齊
  • [0b1] The address is not phrase-aligned 地址未短語對齊
CMD_CHECK_ALIGNFAIL_PG 

CMD_CHECK - ALIGNFAIL_PG FMU Command Check Register - Page Alignment Fail FMU命令檢查暫存器 - 頁面對齊失敗

  • [0b0] The address is page-aligned 地址已頁面對齊
  • [0b1] The address is not page-aligned 地址未頁面對齊
CMD_CHECK_ALIGNFAIL_SCR 

CMD_CHECK - ALIGNFAIL_SCR FMU Command Check Register - Sector Alignment Fail FMU命令檢查暫存器 - 扇區對齊失敗

  • [0b0] The address is sector-aligned 地址已扇區對齊
  • [0b1] The address is not sector-aligned 地址未扇區對齊
CMD_CHECK_ALIGNFAIL_BLK 

CMD_CHECK - ALIGNFAIL_BLK FMU Command Check Register - Block Alignment Fail FMU命令檢查暫存器 - 區塊對齊失敗

  • [0b0] The address is block-aligned 地址已區塊對齊
  • [0b1] The address is not block-aligned 地址未區塊對齊
CMD_CHECK_ADDR_FAIL 

CMD_CHECK - ADDR_FAIL FMU Command Check Register - Address Fail FMU命令檢查暫存器 - 地址失敗

  • [0b0] The address is within the flash or IFR address space 地址在快閃或IFR地址空間內
  • [0b1] The address is outside the flash or IFR address space 地址在快閃或IFR地址空間外
CMD_CHECK_IFR_CMD 

CMD_CHECK - IFR_CMD FMU Command Check Register - IFR Command FMU命令檢查暫存器 - IFR命令

  • [0b0] The command operates on a main flash address 命令在主快閃地址上操作
  • [0b1] The command operates on an IFR address 命令在IFR地址上操作
CMD_CHECK_ALL_CMD 

CMD_CHECK - ALL_CMD FMU Command Check Register - All Blocks Command FMU命令檢查暫存器 - 所有區塊命令

  • [0b0] The command operates on a single flash block 命令在單個快閃區塊上操作
  • [0b1] The command operates on all flash blocks 命令在所有快閃區塊上操作
CMD_CHECK_RANGE_FAIL 

CMD_CHECK - RANGE_FAIL FMU Command Check Register - Address Range Fail FMU命令檢查暫存器 - 地址範圍失敗

  • [0b0] The address range is valid 地址範圍有效
  • [0b1] The address range is invalid 地址範圍無效
CMD_CHECK_SCR_ALIGN_CHK 

SCMD_CHECK - CR_ALIGN_CHK FMU Command Check Register - Sector Alignment Check FMU命令檢查暫存器 - 扇區對齊檢查

  • [0b0] No sector alignment check 無扇區對齊檢查
  • [0b1] Sector alignment check 扇區對齊檢查
CMD_CHECK_OPTION_FAIL 

CMD_CHECK - OPTION_FAIL FMU Command Check Register - Option Check Fail FMU命令檢查暫存器 - 選項檢查失敗

  • [0b0] Option check passes for read command or command is not a read command 讀取命令的選項檢查通過或命令不是讀取命令
  • [0b1] Option check fails for read command 讀取命令的選項檢查失敗
CMD_CHECK_ILLEGAL_CMD 

CMD_CHECK - ILLEGAL_CMD FMU Command Check Register - Illegal Command FMU命令檢查暫存器 - 非法命令

  • [0b0] Command is legal 命令合法
  • [0b1] Command is illegal 命令非法
BSEL_SBSEL 

BSEL - SBSEL FMU Block Select Register - Slave Block Select FMU區塊選擇暫存器 - 從屬區塊選擇

BSEL_MBSEL 

BSEL - MBSEL FMU Block Select Register - Master Block Select FMU區塊選擇暫存器 - 主區塊選擇

MSIZE_MAXADDR0 

MSIZE - MAXADDR0 FMU Memory Size Register - Size of Flash Block 0 FMU記憶體大小暫存器 - 快閃區塊0的大小

FLASH_RD_ADD_FLASH_RD_ADD 

FLASH_RD_ADD - FLASH_RD_ADD Flash Read Address Register - Flash Read Address 快閃讀取地址暫存器 - 快閃讀取地址

FLASH_STOP_ADD_FLASH_STOP_ADD 

FLASH_STOP_ADD - FLASH_STOP_ADD Flash Stop Address Register - Flash Stop Address 快閃停止地址暫存器 - 快閃停止地址

FLASH_RD_CTRL_FLASH_RD 

FLASH_RD_CTRL - FLASH_RD Flash Read Control Register - Flash Read Enable 快閃讀取控制暫存器 - 快閃讀取啟用

  • [0b0] Manual flash read not enabled.(default) 手動快閃讀取未啟用。（默認）
  • [0b1] Manual flash read enabled 手動快閃讀取已啟用
FLASH_RD_CTRL_WIDE_LOAD 

FLASH_RD_CTRL - WIDE_LOAD Flash Read Control Register - Wide Load Enable 快閃讀取控制暫存器 - 寬載入啟用

  • [0b0] Wide load mode disabled (default) 寬載入模式已禁用（默認）
  • [0b1] Wide load mode enabled 寬載入模式已啟用
FLASH_RD_CTRL_SINGLE_RD 

FLASH_RD_CTRL - SINGLE_RD Flash Read Control Register - Single Flash Read 快閃讀取控制暫存器 - 單次快閃讀取

  • [0b0] Normal UINT operation 正常UINT操作
  • [0b1] UINT configured for single cycle reads UINT配置為單周期讀取
MM_ADDR_MM_ADDR 

MM_ADDR - MM_ADDR Memory Map Address Register - Memory Map Address 記憶體映射地址暫存器 - 記憶體映射地址

MM_WDATA_MM_WDATA 

MM_WDATA - MM_WDATA Memory Map Write Data Register - Memory Map Write Data 記憶體映射寫入數據暫存器 - 記憶體映射寫入數據

MM_CTL_MM_SEL 

MM_CTL - MM_SEL Memory Map Control Register - Register Access Enable 記憶體映射控制暫存器 - 暫存器存取啟用

MM_CTL_MM_RD 

MM_CTL - MM_RD Memory Map Control Register - Register R/W Control 記憶體映射控制暫存器 - 暫存器讀寫控制

  • [0b0] Write to register 寫入暫存器
  • [0b1] Read register 讀取暫存器
MM_CTL_BIST_ON 

MM_CTL - BIST_ON Memory Map Control Register - BIST on 記憶體映射控制暫存器 - BIST啟用

  • [0b0] BIST enable not forced by user interface BIST啟用未由用戶界面強制
  • [0b1] BIST enable control by user interface BIST啟用由用戶界面控制
MM_CTL_FORCE_SW_CLK 

MM_CTL - FORCE_SW_CLK Memory Map Control Register - Force Switch Clock 記憶體映射控制暫存器 - 強制切換時鐘

  • [0b0] Switch clock not forced on (gated normally) 切換時鐘未強制啟用（正常門控）
  • [0b1] Switch clock forced on 切換時鐘強制啟用
UINT_CTL_SET_FAIL 

UINT_CTL - SET_FAIL User Interface Control Register - Set Fail On Exit 用戶界面控制暫存器 - 在退出時設置失敗

  • [0b0] FAIL flag should not be set on command exit (no failure detected) 在命令退出時不應設置FAIL旗標（未檢測到失敗）
  • [0b1] FAIL flag should be set on command exit 在命令退出時應設置FAIL旗標
UINT_CTL_DBERR 

UINT_CTL - DBERR User Interface Control Register - Double-Bit ECC Fault Detect 用戶界面控制暫存器 - 雙位ECC錯誤檢測

  • [0b0] No double-bit fault detected during UINT-driven read sequence 在UINT驅動的讀取序列期間未檢測到雙位錯誤
  • [0b1] Double-bit fault detected during UINT-driven read sequence 在UINT驅動的讀取序列期間檢測到雙位錯誤
RD_DATA0_RD_DATA0 

RD_DATA0 - RD_DATA0 Read Data 0 Register - Read Data 0 讀取數據0暫存器 - 讀取數據0.

RD_DATA1_RD_DATA1 

RD_DATA1 - RD_DATA1 Read Data 1 Register - Read Data 1 讀取數據1暫存器 - 讀取數據1.

RD_DATA2_RD_DATA2 

RD_DATA2 - RD_DATA2 Read Data 2 Register - Read Data 2 讀取數據2暫存器 - 讀取數據2.

RD_DATA3_RD_DATA3 

RD_DATA3 - RD_DATA3 Read Data 3 Register - Read Data 3 讀取數據3暫存器 - 讀取數據3.

PARITY_PARITY 

PARITY - PARITY Parity Register - Read data [136:128] 奇偶校驗暫存器 - 讀取數據[136:128].

RD_PATH_CTRL_STATUS_RD_CAPT 

RD_PATH_CTRL_STATUS - RD_CAPT Read Path Control and Status Register - Read Capture Clock Periods 讀取路徑控制和狀態暫存器 - 讀取捕獲時鐘周期

RD_PATH_CTRL_STATUS_SE_SIZE 

RD_PATH_CTRL_STATUS - SE_SIZE Read Path Control and Status Register - SE Clock Periods 讀取路徑控制和狀態暫存器 - SE時鐘周期

RD_PATH_CTRL_STATUS_ECC_ENABLEB 

RD_PATH_CTRL_STATUS - ECC_ENABLEB Read Path Control and Status Register - ECC Decoder Control 讀取路徑控制和狀態暫存器 - ECC解碼器控制

  • [0b0] ECC decoder enabled (default) ECC解碼器已啟用（默認）
  • [0b1] ECC decoder disabled ECC解碼器已禁用
RD_PATH_CTRL_STATUS_MISR_EN 

RD_PATH_CTRL_STATUS - MISR_EN Read Path Control and Status Register - MISR Enable 讀取路徑控制和狀態暫存器 - MISR啟用

  • [0b0] MISR option disabled (default) MISR選項已禁用（默認）
  • [0b1] MISR option enabled MISR選項已啟用
RD_PATH_CTRL_STATUS_CPY_PAR_EN 

RD_PATH_CTRL_STATUS - CPY_PAR_EN Read Path Control and Status Register - Copy Parity Enable 讀取路徑控制和狀態暫存器 - 複製奇偶校驗啟用

  • [0b0] Copy parity disabled 複製奇偶校驗已禁用
  • [0b1] Copy parity enabled 複製奇偶校驗已啟用
RD_PATH_CTRL_STATUS_BIST_MUX_TO_SMW 

RD_PATH_CTRL_STATUS - BIST_MUX_TO_SMW Read Path Control and Status Register - BIST Mux to SMW 讀取路徑控制和狀態暫存器 - BIST多工器到SMW.

  • [0b0] BIST drives fields BIST驅動字段
  • [0b1] SMW registers drive fields SMW暫存器驅動字段
RD_PATH_CTRL_STATUS_AD_SET 

RD_PATH_CTRL_STATUS - AD_SET Read Path Control and Status Register - Multi-Cycle Address Setup Time 讀取路徑控制和狀態暫存器 - 多周期地址設置時間

RD_PATH_CTRL_STATUS_WR_PATH_EN 

RD_PATH_CTRL_STATUS - WR_PATH_EN Read Path Control and Status Register - Write Path Enable 讀取路徑控制和狀態暫存器 - 寫入路徑啟用

  • [0b0] Writes to BIST setting registers driven by MM_WDATA 寫入由MM_WDATA驅動的BIST設置暫存器
  • [0b1] Writes to BIST setting registers driven by SMW_DIN 寫入由SMW_DIN驅動的BIST設置暫存器
RD_PATH_CTRL_STATUS_WR_PATH_ECC_EN 

RD_PATH_CTRL_STATUS - WR_PATH_ECC_EN Read Path Control and Status Register - Write Path ECC Enable 讀取路徑控制和狀態暫存器 - 寫入路徑ECC啟用

  • [0b0] ECC encoding disabled ECC編碼已禁用
  • [0b1] ECC encoding enabled ECC編碼已啟用
RD_PATH_CTRL_STATUS_DBERR_REG 

RD_PATH_CTRL_STATUS - DBERR_REG Read Path Control and Status Register - Double-Bit Error 讀取路徑控制和狀態暫存器 - 雙位錯誤

  • [0b0] Double-bit fault not detected 未檢測到雙位錯誤
  • [0b1] Double-bit fault detected on previous UINT flash read 在之前的UINT快閃讀取中檢測到雙位錯誤
RD_PATH_CTRL_STATUS_SBERR_REG 

RD_PATH_CTRL_STATUS - SBERR_REG Read Path Control and Status Register - Single-Bit Error 讀取路徑控制和狀態暫存器 - 單位錯誤

  • [0b0] Single-bit fault not detected 未檢測到單位錯誤
  • [0b1] Single-bit fault detected on previous UINT flash read 在之前的UINT快閃讀取中檢測到單位錯誤
RD_PATH_CTRL_STATUS_CPY_PHRASE_EN 

RD_PATH_CTRL_STATUS - CPY_PHRASE_EN Read Path Control and Status Register - Copy Phrase Enable 讀取路徑控制和狀態暫存器 - 複製短語啟用

  • [0b0] Copy Flash read data disabled 複製快閃讀取數據已禁用
  • [0b1] Copy Flash read data enabled 複製快閃讀取數據已啟用
RD_PATH_CTRL_STATUS_SMW_ARRAY1_SMW0_SEL 

RD_PATH_CTRL_STATUS - SMW_ARRAY1_SMW0_SEL Read Path Control and Status Register - SMW_ARRAY1_SMW0_SEL 讀取路徑控制和狀態暫存器 - SMW_ARRAY1_SMW0_SEL.

  • [0b0] Select block 0 選擇區塊0
  • [0b1] Select block 1 選擇區塊1
RD_PATH_CTRL_STATUS_BIST_ECC_EN 

RD_PATH_CTRL_STATUS - BIST_ECC_EN Read Path Control and Status Register - BIST ECC Enable 讀取路徑控制和狀態暫存器 - BIST ECC啟用

  • [0b0] ECC correction disabled ECC校正已禁用
  • [0b1] ECC correction enabled ECC校正已啟用
RD_PATH_CTRL_STATUS_LAST_READ 

RD_PATH_CTRL_STATUS - LAST_READ Read Path Control and Status Register - Last Read 讀取路徑控制和狀態暫存器 - 最後一次讀取

  • [0b0] Latest read not last in multi-address operation 最新讀取不是多地址操作中的最後一次
  • [0b1] Latest read last in multi-address operation 最新讀取是多地址操作中的最後一次
SMW_DIN0_SMW_DIN0 

SMW_DIN0 - SMW_DIN0 SMW DIN 0 Register - SMW DIN 0 SMW DIN 0暫存器 - SMW DIN 0.

SMW_DIN1_SMW_DIN1 

SMW_DIN1 - SMW_DIN1 SMW DIN 1 Register - SMW DIN 1 SMW DIN 1暫存器 - SMW DIN 1.

SMW_DIN2_SMW_DIN2 

SMW_DIN2 - SMW_DIN2 SMW DIN 2 Register - SMW DIN 2 SMW DIN 2暫存器 - SMW DIN 2.

SMW_DIN3_SMW_DIN3 

SMW_DIN3 - SMW_DIN3 SMW DIN 3 Register - SMW DIN 3 SMW DIN 3暫存器 - SMW DIN 3.

SMW_ADDR_SMW_ADDR 

SMW_ADDR - SMW_ADDR SMW Address Register - SMW Address SMW地址暫存器 - SMW地址

SMW_CMD_WAIT_CMD 

SMW_CMD_WAIT - CMD SMW Command and Wait Register - SMW Command SMW命令和等待暫存器 - SMW命令

  • [0b000] IDLE 空閒
  • [0b001] ABORT 中止
  • [0b010] SME2 to one-shot mass erase SME2到單次大量擦除
  • [0b011] SME3 to sector erase on selected array SME3到選定數組上的扇區擦除
  • [0b100] SMP1 to program phrase or page on selected array with shot disabled on previously programmed bit SMP1到選定數組上的短語或頁面程式，禁用先前程式位上的射擊
  • [0b101] Reserved for SME4 (multi-sector erase) 保留用於SME4（多扇區擦除）
  • [0b110] SMP2 to program phrase or page on selected array to repair cells of weak program after power loss SMP2到選定數組上的短語或頁面程式，以修復電源丟失後的弱程式單元
  • [0b111] Reserved 保留
SMW_CMD_WAIT_WAIT_EN 

SMW_CMD_WAIT - WAIT_EN SMW Command and Wait Register - SMW Wait Enable SMW命令和等待暫存器 - SMW等待啟用

  • [0b0] Wait feature disabled 等待功能已禁用
  • [0b1] Wait feature enabled 等待功能已啟用
SMW_CMD_WAIT_WAIT_AUTO_SET 

SMW_CMD_WAIT - WAIT_AUTO_SET SMW Command and Wait Register - SMW Wait Auto Set SMW命令和等待暫存器 - SMW等待自動設置

SMW_STATUS_SMW_ERR 

SMW_STATUS - SMW_ERR SMW Status Register - SMW Error SMW狀態暫存器 - SMW錯誤

  • [0b0] Error not detected 未檢測到錯誤
  • [0b1] Error detected 檢測到錯誤
SMW_STATUS_SMW_BUSY 

SMW_STATUS - SMW_BUSY SMW Status Register - SMW Busy SMW狀態暫存器 - SMW忙碌

  • [0b0] SMW command not active SMW命令未激活
  • [0b1] SMW command is active SMW命令已激活
SMW_STATUS_BIST_BUSY 

SMW_STATUS - BIST_BUSY SMW Status Register - BIST Busy SMW狀態暫存器 - BIST忙碌

  • [0b0] BIST Command not active BIST命令未激活
  • [0b1] BIST Command is active BIST命令已激活
SOCTRIM0_0_TRIM0_0 

SOCTRIM0_0 - TRIM0_0 SoC Trim Phrase 0 Word 0 Register - TRIM0_0 SoC修剪短語0字0暫存器 - TRIM0_0.

SOCTRIM0_1_TRIM0_1 

SOCTRIM0_1 - TRIM0_1 SoC Trim Phrase 0 Word 1 Register - TRIM0_1 SoC修剪短語0字1暫存器 - TRIM0_1.

SOCTRIM0_2_TRIM0_2 

SOCTRIM0_2 - TRIM0_2 SoC Trim Phrase 0 Word 2 Register - TRIM0_2 SoC修剪短語0字2暫存器 - TRIM0_2.

SOCTRIM0_3_TRIM0_3 

SOCTRIM0_3 - TRIM0_3 SoC Trim Phrase 0 Word 3 Register - TRIM0_3 SoC修剪短語0字3暫存器 - TRIM0_3.

SOCTRIM1_0_TRIM1_0 

SOCTRIM1_0 - TRIM1_0 SoC Trim Phrase 1 Word 0 Register - TRIM1_0 SoC修剪短語1字0暫存器 - TRIM1_0.

SOCTRIM1_1_TRIM1_1 

SOCTRIM1_1 - TRIM1_1 SoC Trim Phrase 1 Word 1 Register - TRIM1_1 SoC修剪短語1字1暫存器 - TRIM1_1.

SOCTRIM1_2_TRIM1_2 

SOCTRIM1_2 - TRIM1_2 SoC Trim Phrase 1 Word 2 Register - TRIM1_2 SoC修剪短語1字2暫存器 - TRIM1_2.

SOCTRIM1_3_TRIM1_3 

SOCTRIM1_3 - TRIM1_3 SoC Trim Phrase 1 Word 3 Register - TRIM1_3 SoC修剪短語1字3暫存器 - TRIM1_3.

SOCTRIM2_0_TRIM2_0 

SOCTRIM2_0 - TRIM2_0 SoC Trim Phrase 2 Word 0 Register - TRIM2_0 SoC修剪短語2字0暫存器 - TRIM2_0.

SOCTRIM2_1_TRIM2_1 

SOCTRIM2_1 - TRIM2_1 SoC Trim Phrase 2 Word 1 Register - TRIM2_1 SoC修剪短語2字1暫存器 - TRIM2_1.

SOCTRIM2_2_TRIM2_2 

SOCTRIM2_2 - TRIM2_2 SoC Trim Phrase 2 Word 2 Register - TRIM2_2 SoC修剪短語2字2暫存器 - TRIM2_2.

SOCTRIM2_3_TRIM2_3 

SOCTRIM2_3 - TRIM2_3 SoC Trim Phrase 2 Word 3 Register - TRIM2_3 SoC修剪短語2字3暫存器 - TRIM2_3.

SOCTRIM3_0_TRIM3_0 

SOCTRIM3_0 - TRIM3_0 SoC Trim Phrase 3 Word 0 Register - TRIM3_0 SoC修剪短語3字0暫存器 - TRIM3_0.

SOCTRIM3_1_TRIM3_1 

SOCTRIM3_1 - TRIM3_1 SoC Trim Phrase 3 Word 1 Register - TRIM3_1 SoC修剪短語3字1暫存器 - TRIM3_1.

SOCTRIM3_2_TRIM3_2 

SOCTRIM3_2 - TRIM3_2 SoC Trim Phrase 3 Word 2 Register - TRIM3_2 SoC修剪短語3字2暫存器 - TRIM3_2.

SOCTRIM3_3_TRIM3_3 

SOCTRIM3_3 - TRIM3_3 SoC Trim Phrase 3 Word 3 Register - TRIM3_3 SoC修剪短語3字3暫存器 - TRIM3_3.

SOCTRIM4_0_TRIM4_0 

SOCTRIM4_0 - TRIM4_0 SoC Trim Phrase 4 Word 0 Register - TRIM4_0 SoC修剪短語4字0暫存器 - TRIM4_0.

SOCTRIM4_1_TRIM4_1 

SOCTRIM4_1 - TRIM4_1 SoC Trim Phrase 4 Word 1 Register - TRIM4_1 SoC修剪短語4字1暫存器 - TRIM4_1.

SOCTRIM4_2_TRIM4_2 

SOCTRIM4_2 - TRIM4_2 SoC Trim Phrase 4 Word 2 Register - TRIM4_2 SoC修剪短語4字2暫存器 - TRIM4_2.

SOCTRIM4_3_TRIM4_3 

SOCTRIM4_3 - TRIM4_3 SoC Trim Phrase 4 Word 3 Register - TRIM4_3 SoC修剪短語4字3暫存器 - TRIM4_3.

SOCTRIM5_0_TRIM5_0 

SOCTRIM5_0 - TRIM5_0 SoC Trim Phrase 5 Word 0 Register - TRIM5_0 SoC修剪短語5字0暫存器 - TRIM5_0.

SOCTRIM5_1_TRIM5_1 

SOCTRIM5_1 - TRIM5_1 SoC Trim Phrase 5 Word 1 Register - TRIM5_1 SoC修剪短語5字1暫存器 - TRIM5_1.

SOCTRIM5_2_TRIM5_2 

SOCTRIM5_2 - TRIM5_2 SoC Trim Phrase 5 Word 2 Register - TRIM5_2 SoC修剪短語5字2暫存器 - TRIM5_2.

SOCTRIM5_3_TRIM5_3 

SOCTRIM5_3 - TRIM5_3 SoC Trim Phrase 5 Word 3 Register - TRIM5_3 SoC修剪短語5字3暫存器 - TRIM5_3.

SOCTRIM6_0_TRIM6_0 

SOCTRIM6_0 - TRIM6_0 SoC Trim Phrase 6 Word 0 Register - TRIM6_0 SoC修剪短語6字0暫存器 - TRIM6_0.

SOCTRIM6_1_TRIM6_1 

SOCTRIM6_1 - TRIM6_1 SoC Trim Phrase 6 Word 1 Register - TRIM6_1 SoC修剪短語6字1暫存器 - TRIM6_1.

SOCTRIM6_2_TRIM6_2 

SOCTRIM6_2 - TRIM6_2 SoC Trim Phrase 6 Word 2 Register - TRIM6_2 SoC修剪短語6字2暫存器 - TRIM6_2.

SOCTRIM6_3_TRIM6_3 

SOCTRIM6_3 - TRIM6_3 SoC Trim Phrase 6 Word 3 Register - TRIM6_3 SoC修剪短語6字3暫存器 - TRIM6_3.

SOCTRIM7_0_TRIM7_0 

SOCTRIM7_0 - TRIM7_0 SoC Trim Phrase 7 Word 0 Register - TRIM7_0 SoC修剪短語7字0暫存器 - TRIM7_0.

SOCTRIM7_1_TRIM7_1 

SOCTRIM7_1 - TRIM7_1 SoC Trim Phrase 7 Word 1 Register - TRIM7_1 SoC修剪短語7字1暫存器 - TRIM7_1.

SOCTRIM7_2_TRIM7_2 

SOCTRIM7_2 - TRIM7_2 SoC Trim Phrase 7 Word 2 Register - TRIM7_2 SoC修剪短語7字2暫存器 - TRIM7_2.

SOCTRIM7_3_TRIM7_3 

SOCTRIM7_3 - TRIM7_3 SoC Trim Phrase 7 Word 3 Register - TRIM7_3 SoC修剪短語7字3暫存器 - TRIM7_3.

R_IP_CONFIG_IPSEL0 

R_IP_CONFIG - IPSEL0 BIST Configuration Register - Block 0 Select Control BIST配置暫存器 - 區塊0選擇控制

  • [0b00] Unselect block 0 未選擇區塊0
  • [0b01] not used, reserved 未使用，保留
  • [0b10] Enable block 0 test, repair off (default) 啟用區塊0測試，修復關閉（默認）
  • [0b11] Enable block 0 test, repair on 啟用區塊0測試，修復開啟
R_IP_CONFIG_IPSEL1 

R_IP_CONFIG - IPSEL1 BIST Configuration Register - Block 1 Select Control BIST配置暫存器 - 區塊1選擇控制

  • [0b00] Unselect block 1 未選擇區塊1
  • [0b01] not used, reserved 未使用，保留
  • [0b10] Enable block 1 test, repair off (default) 啟用區塊1測試，修復關閉（默認）
  • [0b11] Enable block 1 test, repair on 啟用區塊1測試，修復開啟
R_IP_CONFIG_BIST_CDIVL 

R_IP_CONFIG - BIST_CDIVL BIST Configuration Register - Clock Divide Scalar for Long Pulse BIST配置暫存器 - 用於長脈衝的時鐘分頻標量

R_IP_CONFIG_CDIVS 

R_IP_CONFIG - CDIVS BIST Configuration Register - Number of clock cycles to generate short pulse BIST配置暫存器 - 生成短脈衝的時鐘周期數

R_IP_CONFIG_BIST_TVFY 

R_IP_CONFIG - BIST_TVFY BIST Configuration Register - Timer adjust for verify BIST配置暫存器 - 用於驗證的計時器調整

R_IP_CONFIG_TSTCTL 

R_IP_CONFIG - TSTCTL BIST Configuration Register - BIST self-test control BIST配置暫存器 - BIST自測控制

  • [0b00] Default, disable both BIST self-test and MISR 默認，禁用BIST自測和MISR
  • [0b01] Enable BIST self-test mode DOUT from macro will be forced to '0', and disable MISR. 啟用BIST自測模式，宏中的DOUT將被強制為'0'，並禁用MISR。
  • [0b10] Enable MISR 啟用MISR
  • [0b11] Enable both BIST self-test mode and MISR 啟用BIST自測模式和MISR
R_IP_CONFIG_DBGCTL 

R_IP_CONFIG - DBGCTL BIST Configuration Register - Debug feature control BIST配置暫存器 - 調試功能控制

  • [0b0] Default 默認
  • [0b1] Enable debug feature to collect failure address and data. 啟用調試功能以收集失敗地址和數據。
R_IP_CONFIG_BIST_CLK_SEL 

R_IP_CONFIG - BIST_CLK_SEL BIST Configuration Register - BIST Clock Select BIST配置暫存器 - BIST時鐘選擇

R_IP_CONFIG_SMWTST 

R_IP_CONFIG - SMWTST BIST Configuration Register - SMWR DOUT Function Control BIST配置暫存器 - SMWR DOUT功能控制

  • [0b00] Default 默認
  • [0b01] Enable SMWR self-test mode, DOUT from macro will be forced to all 0 啟用SMWR自測模式，宏中的DOUT將被強制為全0
  • [0b10] Enable SMWR self-test mode, DOUT from macro will be forced to all 1 啟用SMWR自測模式，宏中的DOUT將被強制為全1
  • [0b11] Reserved (unused) 保留（未使用）
R_IP_CONFIG_ECCEN 

R_IP_CONFIG - ECCEN BIST Configuration Register - BIST ECC Control BIST配置暫存器 - BIST ECC控制

  • [0b0] Default mode (no ECC encode or decode) 默認模式（無ECC編碼或解碼）
  • [0b1] Enable ECC encode/decode 啟用ECC編碼/解碼
R_TESTCODE_TESTCODE 

R_TESTCODE - TESTCODE BIST Test Code Register - Used to store test code information before running TMR-RST/TMRSET BIST command BIST測試代碼暫存器 - 用於在運行TMR-RST/TMRSET BIST命令之前存儲測試代碼信息

R_DFT_CTRL_DFT_XADR 

R_DFT_CTRL - DFT_XADR BIST DFT Control Register - DFT XADR Pattern BIST DFT控制暫存器 - DFT XADR模式

  • [0b0000] XADR fixed, no change at all XADR固定，完全不變
  • [0b0001] XADR increased by 1 after row. For READ operation, XADR increases by 1 after reading the last word of row. For PROG operation, XADR increases by 1 after NVSTR falls. XADR在行後增加1。對於READ操作，XADR在讀取行的最後一個字後增加1。對於PROG操作，XADR在NVSTR下降後增加1。
  • [0b0010] XADR increased for diagonal. For PROG-DIAGONAL operation, XADR is increased to create diagonal pattern. XADR增加以形成對角線。對於PROG-DIAGONAL操作，XADR增加以創建對角線模式。
  • [0b0011] XADR increased by sector. During ERASE operation, XADR increased by number of rows in a sector when NVSTR falls. XADR按扇區增加。在ERASE操作期間，XADR在NVSTR下降時按扇區中的行數增加。
  • [0b0100] XADR inversed. XADR is inversed after reading one word or after programming one row when NVSTR falls. XADR反轉。在讀取一個字或程式一行後，XADR反轉。
  • [0b0101] XADR increased by 2 after row. For READ operation, XADR is increased by 2 after reading the last word of a row. For PROG operation, XADR is increased by 2 when NVSTR falls. XADR在行後增加2。對於READ操作，XADR在讀取行的最後一個字後增加2。對於PROG操作，XADR在NVSTR下降時增加2。
  • [0b0110] XADR[0] inversed. XADR[0] is inversed after reading one word or after programming one row when NVSTR falls. XADR[0]反轉。在讀取一個字或程式一行後，XADR[0]反轉。
  • [0b0111] XADR increased by 1. For READ operations only, XADR increased by 1 after each read cycle. XADR增加1。僅對READ操作，XADR在每次讀取周期後增加1。
  • [0b1000] XADR decreased by 1 after row. For READ operations only, XADR is decreased by 1 after YADR decreases to 0. XADR在行後減少1。僅對READ操作，XADR在YADR減少到0後減少1。
  • [0b1001] XADR decreased by 1. For READ operations only, XADR is decreased by 1 after each read cycle. XADR減少1。僅對READ操作，XADR在每次讀取周期後減少1。
R_DFT_CTRL_DFT_YADR 

R_DFT_CTRL - DFT_YADR BIST DFT Control Register - DFT YADR Pattern BIST DFT控制暫存器 - DFT YADR模式

  • [0b0000] YADR fixed, no change at all YADR固定，完全不變
  • [0b0001] YADR for ICKBD. For PROG and READ operations, YADR changed to generate inverse checkerboard pattern. 用於ICKBD的YADR。對於PROG和READ操作，YADR更改以生成反向棋盤模式。
  • [0b0010] YADR for CKBD. For PROG and READ operations, YADR changed to generate checkerboard pattern. 用於CKBD的YADR。對於PROG和READ操作，YADR更改以生成棋盤模式。
  • [0b0011] YADR increased by 1. For READ operations, YADR increased by 1 after each read cycle. For PROG operations, YADR increased by 1 after YE falls. YADR增加1。對於READ操作，YADR在每次讀取周期後增加1。對於PROG操作，YADR在YE下降後增加1。
  • [0b0100] YADR increased for diagonal. For PROG-DIAGONAL operation, YADR is increased to create diagonal pattern. YADR增加以形成對角線。對於PROG-DIAGONAL操作，YADR增加以創建對角線模式。
  • [0b0101] YADR inversed. YADR is inversed after reading one word or after programming one word when YE falls. YADR反轉。在讀取一個字或程式一個字後，YADR反轉。
  • [0b0110] YADR[0] inversed. YADR[0] is inversed after reading one word or after programming one word when YE falls. YADR[0]反轉。在讀取一個字或程式一個字後，YADR[0]反轉。
  • [0b0111] YADR increased by 1 after last row. For READ operations only, YADR is increased by 1 after XADR reaches last row. 在最後一行後增加YADR。僅對READ操作，YADR在XADR到達最後一行後增加1。
  • [0b1000] YADR decreased by 1. For READ operations only, YADR is decreased by 1 after each read cycle. YADR減少1。僅對READ操作，YADR在每次讀取周期後減少1。
  • [0b1001] YADR decreased by 1 after first row. For READ operations only, YADR is decreased by 1 after XADR decreases to 0. 在第一行後減少YADR。僅對READ操作，YADR在XADR減少到0後減少1。
R_DFT_CTRL_DFT_DATA 

R_DFT_CTRL - DFT_DATA BIST DFT Control Register - DFT Data Pattern BIST DFT控制暫存器 - DFT數據模式

  • [0b0000] CKBD pattern. For READ operations only, compare DOUT with checkerboard data pattern for each read cycle. CKBD模式。僅對READ操作，將DOUT與每次讀取周期的棋盤數據模式進行比較。
  • [0b0001] ICKBD pattern. For READ operations only, compare DOUT with inverse checkerboard data pattern for each read cycle. ICKBD模式。僅對READ操作，將DOUT與每次讀取周期的反向棋盤數據模式進行比較。
  • [0b0010] Diagonal pattern. Used for READ operations only, compare DOUT to diagonal pattern. 對角線模式。僅用於READ操作，將DOUT與對角線模式進行比較。
  • [0b0011] Fixed data pattern. For READ operations, comparison to DOUT for selected groups; refer to R_ADR_CTRL[GRPSEL] for modules with multiple groups. 固定數據模式。對於READ操作，選定組的DOUT比較；參考R_ADR_CTRL[GRPSEL]以獲取具有多個組的模塊。
  • [0b0100] Random data pattern which will be generated based on the initial seed set in R_DATA; for READ operations, used for DOUT comparison of selected groups. For PROG operations, used to control DIN of selected groups. 隨機數據模式，將根據R_DATA中的初始種子生成；對於READ操作，用於選定組的DOUT比較。對於PROG操作，用於控制選定組的DIN。
  • [0b0101] DOUT based pattern. For READ operations only, DOUT of selected group will be latched in R_DATA. If more than one group is selected in R_ADR_CTRL[GRPSEL], the group with the lower index will be latched. 基於DOUT的模式。僅對READ操作，選定組的DOUT將在R_DATA中鎖存。如果在R_ADR_CTRL[GRPSEL]中選擇了多個組，則鎖存索引較低的組。
  • [0b0110] R_DATA based pattern. For READ operations, expected DOUT value of selected groups equals to R_DATA when XADR[0]==YADR[0] or ~R_DATA when XADR[0]!=YADR[0]. For PROG operations, DIN of selected groups equals R_DATA when XADR[0]==YADR[0] or ~R_DATA when XADR[0]!=YADR[0]. 基於R_DATA的模式。對於READ操作，選定組的預期DOUT值等於R_DATA，當XADR[0]==YADR[0]或~R_DATA，當XADR[0]!=YADR[0]。對於PROG操作，選定組的DIN等於R_DATA，當XADR[0]==YADR[0]或~R_DATA，當XADR[0]!=YADR[0]。
  • [0b0111] SCAN-IO pattern. For READ operations, control expected DOUT value of selected groups to SCAN-IO data pattern. For PROG operations, control DIN of selected groups to SCAN-IO data pattern. SCAN-IO模式。對於READ操作，控制選定組的預期DOUT值到SCAN-IO數據模式。對於PROG操作，控制選定組的DIN到SCAN-IO數據模式。
  • [0b1000] REPAIR set. For PROG operation to IFR1(7,1) and IFR1(7,2), R_REPAIR0_0 and R_REPAIR0_1 or R_REPAIR1_0 and R_REPAIR1_1 will control DIN. For READ operation on IFR1(7,1) and IFR1(7,2), DOUT will be compared against R_REPAIR0_0 and R_REPAIR0_1 or R_REPAIR1_0 andR_REPAIR1_1. When this option is selected, only one flash block can be selected. REPAIR設置。對於PROG操作到IFR1(7,1)和IFR1(7,2)，R_REPAIR0_0和R_REPAIR0_1或R_REPAIR1_0和R_REPAIR1_1將控制DIN。對於READ操作到IFR1(7,1)和IFR1(7,2)，DOUT將與R_REPAIR0_0和R_REPAIR0_1或R_REPAIR1_0和R_REPAIR1_1進行比較。選擇此選項時，只能選擇一個快閃區塊。
  • [0b1001] REPAIR load. For READ operation only, DOUT from IFR1(7,1) and IFR1(7,2) is loaded to R_REPAIR0 and R_REPAIR1. REPAIR加載。僅對READ操作，IFR1(7,1)和IFR1(7,2)的DOUT加載到R_REPAIR0和R_REPAIR1。
R_DFT_CTRL_CMP_MASK 

R_DFT_CTRL - CMP_MASK BIST DFT Control Register - Data Compare Mask BIST DFT控制暫存器 - 數據比較掩碼

  • [0b00] Expected data is compared to DOUT 預期數據與DOUT進行比較
  • [0b01] Expected data (only 0s are considered) are compared to DOUT 預期數據（僅考慮0）與DOUT進行比較
  • [0b10] Expected data (only 1s are considered) are compared to DOUT 預期數據（僅考慮1）與DOUT進行比較
R_DFT_CTRL_DFT_DATA_SRC 

R_DFT_CTRL - DFT_DATA_SRC BIST DFT Control Register - DFT Data Source BIST DFT控制暫存器 - DFT數據源

  • [0b0] {R_DATA_CTRL0,R_DATA_CTRL_EX[2:0],R_DATA_CTRL0,R_DATA_CTRL_EX[2:0],R_DATA_CTRL0,R_DATA_CTRL_EX[2:0],R_DATA_CTRL0} is used 使用{R_DATA_CTRL0,R_DATA_CTRL_EX[2:0],R_DATA_CTRL0,R_DATA_CTRL_EX[2:0],R_DATA_CTRL0,R_DATA_CTRL_EX[2:0],R_DATA_CTRL0}
  • [0b1] {R_DATA_CTRL3,R_DATA_CTRL2_EX[2:0],R_DATA_CTRL2,R_DATA_CTRL1_EX[2:0],R_DATA_CTRL1,R_DATA_CTRL_EX[2:0],R_DATA_CTRL0} is used 使用{R_DATA_CTRL3,R_DATA_CTRL2_EX[2:0],R_DATA_CTRL2,R_DATA_CTRL1_EX[2:0],R_DATA_CTRL1,R_DATA_CTRL_EX[2:0],R_DATA_CTRL0}
R_ADR_CTRL_GRPSEL 

R_ADR_CTRL - GRPSEL BIST Address Control Register - Data Group Select BIST地址控制暫存器 - 數據組選擇

  • [0b0000] Select no data 不選擇數據
  • [0b0001] Select data slice [34:0] 選擇數據切片[34:0]
  • [0b0010] Select data slice [69:35] 選擇數據切片[69:35]
  • [0b0100] Select data slice [104:70] 選擇數據切片[104:70]
  • [0b1000] Select data slice [136:105] 選擇數據切片[136:105]
  • [0b1111] Select data [136:0] 選擇數據[136:0]
R_ADR_CTRL_XADR 

R_ADR_CTRL - XADR BIST Address Control Register - BIST XADR BIST地址控制暫存器 - BIST XADR.

R_ADR_CTRL_YADR 

R_ADR_CTRL - YADR BIST Address Control Register - BIST YADR BIST地址控制暫存器 - BIST YADR.

R_ADR_CTRL_PROG_ATTR 

R_ADR_CTRL - PROG_ATTR BIST Address Control Register - Program Attribute BIST地址控制暫存器 - 程式屬性

  • [0b000] One YE pulse will program one data slice group 一個YE脈衝將程式一個數據切片組
  • [0b001] One YE pulse will program two data slice groups 一個YE脈衝將程式兩個數據切片組
  • [0b010] One YE pulse will program three data slice groups (reserved) 一個YE脈衝將程式三個數據切片組（保留）
  • [0b011] One YE pulse will program four data slice groups 一個YE脈衝將程式四個數據切片組
  • [0b100] One YE pulse will program five data slice groups (reserved) 一個YE脈衝將程式五個數據切片組（保留）
  • [0b101] One YE pulse will program six data slice groups (reserved) 一個YE脈衝將程式六個數據切片組（保留）
  • [0b110] One YE pulse will program seven data slice groups (reserved) 一個YE脈衝將程式七個數據切片組（保留）
  • [0b111] One YE pulse will program eight data slice groups (reserved) 一個YE脈衝將程式八個數據切片組（保留）
R_DATA_CTRL0_DATA0 

R_DATA_CTRL0 - DATA0 BIST Data Control 0 Register - BIST Data 0 Low BIST數據控制0暫存器 - BIST數據0低

R_PIN_CTRL_MAS1 

R_PIN_CTRL - MAS1 BIST Pin Control Register - Mass Erase BIST引腳控制暫存器 - 大量擦除

R_PIN_CTRL_IFREN 

R_PIN_CTRL - IFREN BIST Pin Control Register - IFR Enable BIST引腳控制暫存器 - IFR啟用

R_PIN_CTRL_IFREN1 

R_PIN_CTRL - IFREN1 BIST Pin Control Register - IFR1 Enable BIST引腳控制暫存器 - IFR1啟用

R_PIN_CTRL_REDEN 

R_PIN_CTRL - REDEN BIST Pin Control Register - Redundancy Block Enable BIST引腳控制暫存器 - 冗餘區塊啟用

R_PIN_CTRL_LVE 

R_PIN_CTRL - LVE BIST Pin Control Register - Low Voltage Enable BIST引腳控制暫存器 - 低電壓啟用

R_PIN_CTRL_PV 

R_PIN_CTRL - PV BIST Pin Control Register - Program Verify Enable BIST引腳控制暫存器 - 程式驗證啟用

R_PIN_CTRL_EV 

R_PIN_CTRL - EV BIST Pin Control Register - Erase Verify Enable BIST引腳控制暫存器 - 擦除驗證啟用

R_PIN_CTRL_WIPGM 

R_PIN_CTRL - WIPGM BIST Pin Control Register - Program Current BIST引腳控制暫存器 - 程式電流

R_PIN_CTRL_WHV 

R_PIN_CTRL - WHV BIST Pin Control Register - High Voltage Level BIST引腳控制暫存器 - 高電壓水平

R_PIN_CTRL_WMV 

R_PIN_CTRL - WMV BIST Pin Control Register - Medium Voltage Level BIST引腳控制暫存器 - 中電壓水平

R_PIN_CTRL_XE 

R_PIN_CTRL - XE BIST Pin Control Register - X Address Enable BIST引腳控制暫存器 - X地址啟用

R_PIN_CTRL_YE 

R_PIN_CTRL - YE BIST Pin Control Register - Y Address Enable BIST引腳控制暫存器 - Y地址啟用

R_PIN_CTRL_SE 

R_PIN_CTRL - SE BIST Pin Control Register - Sense Amp Enable BIST引腳控制暫存器 - 感測放大器啟用

R_PIN_CTRL_ERASE 

R_PIN_CTRL - ERASE BIST Pin Control Register - Erase Mode BIST引腳控制暫存器 - 擦除模式

R_PIN_CTRL_PROG 

R_PIN_CTRL - PROG BIST Pin Control Register - Program Mode BIST引腳控制暫存器 - 程式模式

R_PIN_CTRL_NVSTR 

R_PIN_CTRL - NVSTR BIST Pin Control Register - NVM Store BIST引腳控制暫存器 - NVM存儲

R_PIN_CTRL_SLM 

R_PIN_CTRL - SLM BIST Pin Control Register - Sleep Mode Enable BIST引腳控制暫存器 - 睡眠模式啟用

R_PIN_CTRL_RECALL 

R_PIN_CTRL - RECALL BIST Pin Control Register - Recall Trim Code BIST引腳控制暫存器 - 回憶修剪代碼

R_PIN_CTRL_HEM 

R_PIN_CTRL - HEM BIST Pin Control Register - HEM Control BIST引腳控制暫存器 - HEM控制

R_CNT_LOOP_CTRL_LOOPCNT 

R_CNT_LOOP_CTRL - LOOPCNT BIST Loop Count Control Register - Loop Count Control BIST循環計數控制暫存器 - 循環計數控制

R_CNT_LOOP_CTRL_LOOPOPT 

R_CNT_LOOP_CTRL - LOOPOPT BIST Loop Count Control Register - Loop Option BIST循環計數控制暫存器 - 循環選項

  • [0b000] Loop is disabled; selected BIST operation is run once 循環已禁用；選定的BIST操作運行一次
  • [0b001] Loop is enabled; XADR increments by 1 XADR increments by 1 for each new loop. Stops when total loop count meets LOOPCNT+1. 循環已啟用；XADR每次新循環增加1。當總循環計數達到LOOPCNT+1時停止。
  • [0b010] Loop is enabled; YADR increments by 1 YADR increments by 1 for each new loop. Stops when total loop count meets LOOPCNT+1. 循環已啟用；YADR每次新循環增加1。當總循環計數達到LOOPCNT+1時停止。
  • [0b011] Loop is enabled; XADR increments by 2 XADR increments by 2 for each new loop. Stops when total loop count meets LOOPCNT+1. 循環已啟用；XADR每次新循環增加2。當總循環計數達到LOOPCNT+1時停止。
  • [0b100] Loop is enabled; XADR increments by sector XADR increments by 16 for each new loop. Stops when total loop count meets LOOPCNT+1. 循環已啟用；XADR每次新循環按扇區增加16。當總循環計數達到LOOPCNT+1時停止。
R_CNT_LOOP_CTRL_LOOPUNIT 

R_CNT_LOOP_CTRL - LOOPUNIT BIST Loop Count Control Register - Loop Time Unit BIST循環計數控制暫存器 - 循環時間單位

  • [0b000] Clock cycles 時鐘周期
  • [0b001] 0.5 usec 0.5微秒
  • [0b010] 1 usec 1微秒
  • [0b011] 10 usec 10微秒
  • [0b100] 100 usec 100微秒
  • [0b101] 1 msec 1毫秒
  • [0b110] 10 msec 10毫秒
  • [0b111] 100 msec 100毫秒
R_CNT_LOOP_CTRL_LOOPDLY 

R_CNT_LOOP_CTRL - LOOPDLY BIST Loop Count Control Register - Loop Time Delay Scalar BIST循環計數控制暫存器 - 循環時間延遲標量

R_TIMER_CTRL_TNVSUNIT 

R_TIMER_CTRL - TNVSUNIT BIST Timer Control Register - Tnvs Time Unit BIST計時器控制暫存器 - Tnvs時間單位

  • [0b000] Clock cycles 時鐘周期
  • [0b001] 0.5 usec 0.5微秒
  • [0b010] 1 usec 1微秒
  • [0b011] 10 usec 10微秒
  • [0b100] 100 usec 100微秒
  • [0b101] 1 msec 1毫秒
  • [0b110] 10 msec 10毫秒
  • [0b111] 100 msec 100毫秒
R_TIMER_CTRL_TNVSDLY 

R_TIMER_CTRL - TNVSDLY BIST Timer Control Register - Tnvs Time Delay Scalar BIST計時器控制暫存器 - Tnvs時間延遲標量

R_TIMER_CTRL_TNVHUNIT 

R_TIMER_CTRL - TNVHUNIT BIST Timer Control Register - Tnvh Time Unit BIST計時器控制暫存器 - Tnvh時間單位

  • [0b000] Clock cycles 時鐘周期
  • [0b001] 0.5 usec 0.5微秒
  • [0b010] 1 usec 1微秒
  • [0b011] 10 usec 10微秒
  • [0b100] 100 usec 100微秒
  • [0b101] 1 msec 1毫秒
  • [0b110] 10 msec 10毫秒
  • [0b111] 100 msec 100毫秒
R_TIMER_CTRL_TNVHDLY 

R_TIMER_CTRL - TNVHDLY BIST Timer Control Register - Tnvh Time Delay Scalar BIST計時器控制暫存器 - Tnvh時間延遲標量

R_TIMER_CTRL_TPGSUNIT 

R_TIMER_CTRL - TPGSUNIT BIST Timer Control Register - Tpgs Time Unit BIST計時器控制暫存器 - Tpgs時間單位

  • [0b000] Clock cycles 時鐘周期
  • [0b001] 0.5 usec 0.5微秒
  • [0b010] 1 usec 1微秒
  • [0b011] 10 usec 10微秒
  • [0b100] 100 usec 100微秒
  • [0b101] 1 msec 1毫秒
  • [0b110] 10 msec 10毫秒
  • [0b111] 100 msec 100毫秒
R_TIMER_CTRL_TPGSDLY 

R_TIMER_CTRL - TPGSDLY BIST Timer Control Register - Tpgs Time Delay Scalar BIST計時器控制暫存器 - Tpgs時間延遲標量

R_TIMER_CTRL_TRCVUNIT 

R_TIMER_CTRL - TRCVUNIT BIST Timer Control Register - Trcv Time Unit BIST計時器控制暫存器 - Trcv時間單位

  • [0b000] Clock cycles 時鐘周期
  • [0b001] 0.5 usec 0.5微秒
  • [0b010] 1 usec 1微秒
  • [0b011] 10 usec 10微秒
  • [0b100] 100 usec 100微秒
  • [0b101] 1 msec 1毫秒
  • [0b110] 10 msec 10毫秒
  • [0b111] 100 msec 100毫秒
R_TIMER_CTRL_TRCVDLY 

R_TIMER_CTRL - TRCVDLY BIST Timer Control Register - Trcv Time Delay Scalar BIST計時器控制暫存器 - Trcv時間延遲標量

R_TIMER_CTRL_TLVSUNIT 

R_TIMER_CTRL - TLVSUNIT BIST Timer Control Register - Tlvs Time Unit BIST計時器控制暫存器 - Tlvs時間單位

  • [0b000] Clock cycles 時鐘周期
  • [0b001] 0.5 usec 0.5微秒
  • [0b010] 1 usec 1微秒
  • [0b011] 10 usec 10微秒
  • [0b100] 100 usec 100微秒
  • [0b101] 1 msec 1毫秒
  • [0b110] 10 msec 10毫秒
  • [0b111] 100 msec 100毫秒
R_TIMER_CTRL_TLVSDLY_L 

R_TIMER_CTRL - TLVSDLY_L BIST Timer Control Register - Tlvs Time Delay Scalar Low BIST計時器控制暫存器 - Tlvs時間延遲標量低

R_TEST_CTRL_BUSY 

R_TEST_CTRL - BUSY BIST Test Control Register - BIST Busy Status BIST測試控制暫存器 - BIST忙碌狀態

  • [0b0] BIST is idle BIST閒置
  • [0b1] BIST is busy BIST忙碌
R_TEST_CTRL_DEBUG 

R_TEST_CTRL - DEBUG BIST Test Control Register - BIST Debug Status BIST測試控制暫存器 - BIST調試狀態

R_TEST_CTRL_STATUS0 

R_TEST_CTRL - STATUS0 BIST Test Control Register - BIST Status 0 BIST測試控制暫存器 - BIST狀態0.

  • [0b0] BIST test passed on flash block 0 BIST測試通過快閃區塊0
  • [0b1] BIST test failed on flash block 0 BIST測試失敗快閃區塊0
R_TEST_CTRL_STATUS1 

R_TEST_CTRL - STATUS1 BIST Test Control Register - BIST status 1 BIST測試控制暫存器 - BIST狀態1.

  • [0b0] BIST test passed on flash block 1 BIST測試通過快閃區塊1
  • [0b1] BIST test failed on flash block 1 BIST測試失敗快閃區塊1
R_TEST_CTRL_DEBUGRUN 

R_TEST_CTRL - DEBUGRUN BIST Test Control Register - BIST Continue Debug Run BIST測試控制暫存器 - BIST繼續調試運行

R_TEST_CTRL_STARTRUN 

R_TEST_CTRL - STARTRUN BIST Test Control Register - Run New BIST Operation BIST測試控制暫存器 - 運行新BIST操作

R_TEST_CTRL_CMDINDEX 

R_TEST_CTRL - CMDINDEX BIST Test Control Register - BIST Command Index (code) BIST測試控制暫存器 - BIST命令索引（代碼）

R_TEST_CTRL_DISABLE_IP1 

R_TEST_CTRL - DISABLE_IP1 BIST Test Control Register - BIST Disable IP1 BIST測試控制暫存器 - BIST禁用IP1.

R_ABORT_LOOP_ABORT_LOOP 

R_ABORT_LOOP - ABORT_LOOP BIST Abort Loop Register - Abort Loop BIST中止循環暫存器 - 中止循環

  • [0b0] No effect 無效果
  • [0b1] Abort BIST loop commands and force the loop counter to return to 0x0 中止BIST循環命令並強制循環計數器返回到0x0
R_ADR_QUERY_YADRFAIL 

R_ADR_QUERY - YADRFAIL BIST Address Query Register - Failing YADR BIST地址查詢暫存器 - 失敗的YADR.

R_ADR_QUERY_XADRFAIL 

R_ADR_QUERY - XADRFAIL BIST Address Query Register - Failing XADR BIST地址查詢暫存器 - 失敗的XADR.

R_DOUT_QUERY0_DOUTFAIL 

R_DOUT_QUERY0 - DOUTFAIL BIST DOUT Query 0 Register - Failing DOUT Low BIST DOUT查詢0暫存器 - 失敗的DOUT低

R_SMW_QUERY_SMWLOOP 

R_SMW_QUERY - SMWLOOP BIST SMW Query Register - SMW Total Loop Count BIST SMW查詢暫存器 - SMW總循環計數

R_SMW_QUERY_SMWLAST 

R_SMW_QUERY - SMWLAST BIST SMW Query Register - SMW Last Voltage Setting BIST SMW查詢暫存器 - SMW最後電壓設置

R_SMW_SETTING0_SMWPARM0 

R_SMW_SETTING0 - SMWPARM0 BIST SMW Setting 0 Register - SMW Parameter Set 0 BIST SMW設置0暫存器 - SMW參數集0.

R_SMW_SETTING1_SMWPARM1 

R_SMW_SETTING1 - SMWPARM1 BIST SMW Setting 1 Register - SMW Parameter Set 1 BIST SMW設置1暫存器 - SMW參數集1.

R_SMP_WHV0_SMPWHV0 

R_SMP_WHV0 - SMPWHV0 BIST SMP WHV Setting 0 Register - SMP WHV Parameter Set 0 BIST SMP WHV設置0暫存器 - SMP WHV參數集0.

R_SMP_WHV1_SMPWHV1 

R_SMP_WHV1 - SMPWHV1 BIST SMP WHV Setting 1 Register - SMP WHV Parameter Set 1 BIST SMP WHV設置1暫存器 - SMP WHV參數集1.

R_SME_WHV0_SMEWHV0 

R_SME_WHV0 - SMEWHV0 BIST SME WHV Setting 0 Register - SME WHV Parameter Set 0 BIST SME WHV設置0暫存器 - SME WHV參數集0.

R_SME_WHV1_SMEWHV1 

R_SME_WHV1 - SMEWHV1 BIST SME WHV Setting 1 Register - SME WHV Parameter Set 1 BIST SME WHV設置1暫存器 - SME WHV參數集1.

R_SMW_SETTING2_SMWPARM2 

R_SMW_SETTING2 - SMWPARM2 BIST SMW Setting 2 Register - SMW Parameter Set 2 BIST SMW設置2暫存器 - SMW參數集2.

R_D_MISR0_DATASIG0 

R_D_MISR0 - DATASIG0 BIST DIN MISR 0 Register - Data Signature BIST DIN MISR 0暫存器 - 數據簽名

R_A_MISR0_ADRSIG0 

R_A_MISR0 - ADRSIG0 BIST Address MISR 0 Register - Address Signature BIST地址MISR 0暫存器 - 地址簽名

R_C_MISR0_CTRLSIG0 

R_C_MISR0 - CTRLSIG0 BIST Control MISR 0 Register - Control Signature BIST控制MISR 0暫存器 - 控制簽名

R_SMW_SETTING3_SMWPARM3 

R_SMW_SETTING3 - SMWPARM3 BIST SMW Setting 3 Register - SMW Parameter Set 3 BIST SMW設置3暫存器 - SMW參數集3.

R_DATA_CTRL1_DATA1 

R_DATA_CTRL1 - DATA1 BIST Data Control 1 Register - BIST Data 1 Low BIST數據控制1暫存器 - BIST數據1低

R_DATA_CTRL2_DATA2 

R_DATA_CTRL2 - DATA2 BIST Data Control 2 Register - BIST Data 2 Low BIST數據控制2暫存器 - BIST數據2低

R_DATA_CTRL3_DATA3 

R_DATA_CTRL3 - DATA3 BIST Data Control 3 Register - BIST Data 3 Low BIST數據控制3暫存器 - BIST數據3低

R_REPAIR0_0_RDIS0_0 

R_REPAIR0_0 - RDIS0_0 BIST Repair 0 for Block 0 Register - Control Repair 0 in Block 0. BIST修復0區塊0暫存器 - 控制區塊0中的修復0。

  • [0b0] Repair address is valid 修復地址有效
  • [0b1] Repair address is not valid 修復地址無效
R_REPAIR0_0_RADR0_0 

R_REPAIR0_0 - RADR0_0 BIST Repair 0 for Block 0 Register - XADR for Repair 0 in Block 0 BIST修復0區塊0暫存器 - 區塊0中的修復0的XADR.

R_REPAIR0_1_RDIS0_1 

R_REPAIR0_1 - RDIS0_1 BIST Repair 1 Block 0 Register - Control Repair 1 in Block 0. BIST修復1區塊0暫存器 - 控制區塊0中的修復1。

  • [0b0] Repair address is valid 修復地址有效
  • [0b1] Repair address is not valid 修復地址無效
R_REPAIR0_1_RADR0_1 

R_REPAIR0_1 - RADR0_1 BIST Repair 1 Block 0 Register - XADR for Repair 1 in Block 0. BIST修復1區塊0暫存器 - 區塊0中的修復1的XADR.

R_REPAIR1_0_RDIS1_0 

R_REPAIR1_0 - RDIS1_0 BIST Repair 0 Block 1 Register - Control Repair 0 in Block 1. BIST修復0區塊1暫存器 - 控制區塊1中的修復0。

  • [0b0] Repair address is valid 修復地址有效
  • [0b1] Repair address is not valid 修復地址無效
R_REPAIR1_0_RADR1_0 

R_REPAIR1_0 - RADR1_0 BIST Repair 0 Block 1 Register - XADR for Repair 0 in Block 1. BIST修復0區塊1暫存器 - 區塊1中的修復0的XADR.

R_REPAIR1_1_RDIS1_1 

R_REPAIR1_1 - RDIS1_1 BIST Repair 1 Block 1 Register - Control Repair 1 in Block 1. BIST修復1區塊1暫存器 - 控制區塊1中的修復1。

  • [0b0] Repair address is valid 修復地址有效
  • [0b1] Repair address is not valid 修復地址無效
R_REPAIR1_1_RADR1_1 

R_REPAIR1_1 - RADR1_1 BIST Repair 1 Block 1 Register - XADR for Repair 1 in Block 1. BIST修復1區塊1暫存器 - 區塊1中的修復1的XADR.

R_DATA_CTRL0_EX_DATA0X 

R_DATA_CTRL0_EX - DATA0X BIST Data Control 0 Extension Register - BIST Data 0 High BIST數據控制0擴展暫存器 - BIST數據0高

R_TIMER_CTRL_EX_TLVSDLY_H 

R_TIMER_CTRL_EX - TLVSDLY_H BIST Timer Control Extension Register - Tlvs Time Delay Scalar High BIST計時器控制擴展暫存器 - Tlvs時間延遲標量高

R_DOUT_QUERY1_DOUT 

R_DOUT_QUERY1 - DOUT BIST DOUT Query 1 Register - Failing DOUT High BIST DOUT查詢1暫存器 - 失敗的DOUT高

R_D_MISR1_DATASIG1 

R_D_MISR1 - DATASIG1 BIST DIN MISR 1 Register - MISR Data Signature High BIST DIN MISR 1暫存器 - MISR數據簽名高

R_A_MISR1_ADRSIG1 

R_A_MISR1 - ADRSIG1 BIST Address MISR 1 Register - MISR Address Signature High BIST地址MISR 1暫存器 - MISR地址簽名高

R_C_MISR1_CTRLSIG1 

R_C_MISR1 - CTRLSIG1 BIST Control MISR 1 Register - MISR Control Signature High BIST控制MISR 1暫存器 - MISR控制簽名高

R_DATA_CTRL1_EX_DATA1X 

R_DATA_CTRL1_EX - DATA1X BIST Data Control 1 Extension Register - BIST Data 1 High BIST數據控制1擴展暫存器 - BIST數據1高

R_DATA_CTRL2_EX_DATA2X 

R_DATA_CTRL2_EX - DATA2X BIST Data Control 2 Extension Register - BIST Data 2 High BIST數據控制2擴展暫存器 - BIST數據2高

R_DATA_CTRL3_EX_DATA3X 

R_DATA_CTRL3_EX - DATA3X BIST Data Control 3 Extension Register - BIST Data 3 High BIST數據控制3擴展暫存器 - BIST數據3高

SMW_TIMER_OPTION_SMW_CDIVL 

SMW_TIMER_OPTION - SMW_CDIVL Clock Divide Scalar for Long Pulse 用於長脈衝的時鐘分頻標量

SMW_TIMER_OPTION_SMW_TVFY 

SMW_TIMER_OPTION - SMW_TVFY SMW Timer Option Register - Timer Adjust for Verify SMW計時器選項暫存器 - 用於驗證的計時器調整

SMW_SETTING_OPTION0_MV_INIT 

SMW_SETTING_OPTION0 - MV_INIT SMW Setting Option 0 Register - Medium Voltage Level Select Initial SMW設置選項0暫存器 - 中電壓水平選擇初始

SMW_SETTING_OPTION0_MV_END 

SMW_SETTING_OPTION0 - MV_END SMW Setting Option 0 Register - Medium Voltage Level Select Final SMW設置選項0暫存器 - 中電壓水平選擇最終

SMW_SETTING_OPTION0_MV_MISC 

SMW_SETTING_OPTION0 - MV_MISC SMW Setting Option 0 Register - Medium Voltage Control Misc SMW設置選項0暫存器 - 中電壓控制雜項

SMW_SETTING_OPTION0_IPGM_INIT 

SMW_SETTING_OPTION0 - IPGM_INIT SMW Setting Option 0 Register - Program Current Control Initial SMW設置選項0暫存器 - 程式電流控制初始

SMW_SETTING_OPTION0_IPGM_END 

SMW_SETTING_OPTION0 - IPGM_END SMW Setting Option 0 Register - Program Current Control Final SMW設置選項0暫存器 - 程式電流控制最終

SMW_SETTING_OPTION0_IPGM_MISC 

SMW_SETTING_OPTION0 - IPGM_MISC SMW Setting Option 0 Register - Program Current Control Misc SMW設置選項0暫存器 - 程式電流控制雜項

SMW_SETTING_OPTION2_THVS_CTRL 

SMW_SETTING_OPTION2 - THVS_CTRL SMW Setting Option 2 Register - Thvs control SMW設置選項2暫存器 - Thvs控制

SMW_SETTING_OPTION2_TRCV_CTRL 

SMW_SETTING_OPTION2 - TRCV_CTRL SMW Setting Option 2 Register - Trcv Control SMW設置選項2暫存器 - Trcv控制

SMW_SETTING_OPTION2_XTRA_ERS 

SMW_SETTING_OPTION2 - XTRA_ERS SMW Setting Option 2 Register - Number of Post Shots for SME SMW設置選項2暫存器 - SME的後射次數

SMW_SETTING_OPTION2_XTRA_PGM 

SMW_SETTING_OPTION2 - XTRA_PGM SMW Setting Option 2 Register - Number of Post Shots for SMP SMW設置選項2暫存器 - SMP的後射次數

SMW_SETTING_OPTION2_WHV_CNTR 

SMW_SETTING_OPTION2 - WHV_CNTR SMW Setting Option 2 Register - WHV Counter SMW設置選項2暫存器 - WHV計數器

SMW_SETTING_OPTION2_POST_TERS 

SMW_SETTING_OPTION2 - POST_TERS SMW Setting Option 2 Register - Post Ters Time SMW設置選項2暫存器 - 後Ters時間

  • [0b000] 50 usec 50微秒
  • [0b001] 100 usec 100微秒
  • [0b010] 200 usec 200微秒
  • [0b011] 300 usec 300微秒
  • [0b100] 500 usec 500微秒
  • [0b101] 1 msec 1毫秒
  • [0b110] 1.5 msec 1.5毫秒
  • [0b111] 2 msec 2毫秒
SMW_SETTING_OPTION2_POST_TPGM 

SMW_SETTING_OPTION2 - POST_TPGM SMW Setting Option 2 Register - Post Tpgm Time SMW設置選項2暫存器 - 後Tpgm時間

  • [0b00] 1 usec 1微秒
  • [0b01] 2 usec 2微秒
  • [0b10] 4 usec 4微秒
  • [0b11] 8 usec 8微秒
SMW_SETTING_OPTION2_VFY_OPT 

SMW_SETTING_OPTION2 - VFY_OPT SMW Setting Option 2 Register - Verify Option SMW設置選項2暫存器 - 驗證選項

  • [0b00] Skip verify for post shot only, verify for all other shots 僅跳過後射的驗證，驗證所有其他射擊
  • [0b01] Skip verify for the 1st and post shots 跳過第1次和後射的驗證
  • [0b10] Skip the 1st, 2nd, and post shots 跳過第1次、第2次和後射的驗證
  • [0b11] Skip verify for all shots 跳過所有射擊的驗證
SMW_SETTING_OPTION2_TPGM_OPT 

SMW_SETTING_OPTION2 - TPGM_OPT SMW Setting Option 2 Register - Tpgm Option SMW設置選項2暫存器 - Tpgm選項

  • [0b00] Fixed Tpgm for all shots, except post shot 固定Tpgm用於所有射擊，除了後射
  • [0b01] Increase Tpgm option by 1 for each loop until Tpgm reaches 4 usec 每次循環增加1個Tpgm選項，直到Tpgm達到4微秒
  • [0b10] Increase Tpgm option by 1 for each loop until Tpgm reaches 8 usec 每次循環增加1個Tpgm選項，直到Tpgm達到8微秒
  • [0b11] Unused 未使用
SMW_SETTING_OPTION2_MASK0_OPT 

SMW_SETTING_OPTION2 - MASK0_OPT SMW Setting Option 2 Register - MASK0_OPT SMW設置選項2暫存器 - MASK0_OPT.

  • [0b0] Mask programmed bits passing PV until extra shot 掩蓋程式位直到額外射擊通過PV
  • [0b1] Always program bits even if they pass PV 即使通過PV也始終程式位
SMW_SETTING_OPTION2_DIS_PRER 

SMW_SETTING_OPTION2 - DIS_PRER SMW Setting Option 2 Register - Disable pre-PV Read before First Program Shot SMW設置選項2暫存器 - 禁用第一次程式射擊前的預PV讀取

  • [0b0] Enable pre-PV read before first program shot 啟用第一次程式射擊前的預PV讀取
  • [0b1] Disable pre-PV read before first program shot 禁用第一次程式射擊前的預PV讀取
SMW_SETTING_OPTION3_HEM_WHV_CNTR 

SMW_SETTING_OPTION3 - HEM_WHV_CNTR SMW Setting Option 3 Register - WHV_COUNTER for HEM-erase Cycle SMW設置選項3暫存器 - 用於HEM擦除周期的WHV計數器

SMW_SETTING_OPTION3_HEM_MAX_ERS 

SMW_SETTING_OPTION3 - HEM_MAX_ERS SMW Setting Option 3 Register - HEM Max Erase Shot Count SMW設置選項3暫存器 - HEM最大擦除射擊次數

SMW_SMP_WHV_OPTION0_SMP_WHV_OPT0 

SMW_SMP_WHV_OPTION0 - SMP_WHV_OPT0 SMW SMP WHV Option 0 Register - Smart Program WHV Option Low SMW SMP WHV選項0暫存器 - 智能程式WHV選項低

SMW_SME_WHV_OPTION0_SME_WHV_OPT0 

SMW_SME_WHV_OPTION0 - SME_WHV_OPT0 SMW SME WHV Option 0 Register - Smart Erase WHV Option Low SMW SME WHV選項0暫存器 - 智能擦除WHV選項低

SMW_SETTING_OPTION1_TERS_CTRL0 

SMW_SETTING_OPTION1 - TERS_CTRL0 SMW Setting Option 1 Register - Ters Control SMW設置選項1暫存器 - Ters控制

  • [0b000] 50 usec 50微秒
  • [0b001] 100 usec 100微秒
  • [0b010] 200 usec 200微秒
  • [0b011] 300 usec 300微秒
  • [0b100] 500 usec 500微秒
  • [0b101] 1 msec 1毫秒
  • [0b110] 1.5 msec 1.5毫秒
  • [0b111] 2 msec 2毫秒
SMW_SETTING_OPTION1_TPGM_CTRL 

SMW_SETTING_OPTION1 - TPGM_CTRL SMW Setting Option 1 Register - Tpgm Control SMW設置選項1暫存器 - Tpgm控制

  • [0b00] 1 usec 1微秒
  • [0b01] 2 usec 2微秒
  • [0b10] 4 usec 4微秒
  • [0b11] 8 usec 8微秒
SMW_SETTING_OPTION1_TNVS_CTRL 

SMW_SETTING_OPTION1 - TNVS_CTRL SMW Setting Option 1 Register - Tnvs Control SMW設置選項1暫存器 - Tnvs控制

  • [0b000] 5 usec 5微秒
  • [0b001] 8 usec 8微秒
  • [0b010] 11 usec 11微秒
  • [0b011] 14 usec 14微秒
  • [0b100] 17 usec 17微秒
  • [0b101] 20 usec 20微秒
  • [0b110] 23 usec 23微秒
  • [0b111] 26 usec 26微秒
SMW_SETTING_OPTION1_TNVH_CTRL 

SMW_SETTING_OPTION1 - TNVH_CTRL SMW Setting Option 1 Register - Tnvh Control SMW設置選項1暫存器 - Tnvh控制

  • [0b000] 2 usec 2微秒
  • [0b001] 2.5 usec 2.5微秒
  • [0b010] 3 usec 3微秒
  • [0b011] 3.5 usec 3.5微秒
  • [0b100] 4 usec 4微秒
  • [0b101] 4.5 usec 4.5微秒
  • [0b110] 5 usec 5微秒
  • [0b111] 5.5 usec 5.5微秒
SMW_SETTING_OPTION1_TPGS_CTRL 

SMW_SETTING_OPTION1 - TPGS_CTRL SMW Setting Option 1 Register - Tpgs Control SMW設置選項1暫存器 - Tpgs控制

  • [0b000] 1 usec 1微秒
  • [0b001] 2 usec 2微秒
  • [0b010] 3 usec 3微秒
  • [0b011] 4 usec 4微秒
  • [0b100] 5 usec 5微秒
  • [0b101] 6 usec 6微秒
  • [0b110] 7 usec 7微秒
  • [0b111] 8 usec 8微秒
SMW_SETTING_OPTION1_MAX_ERASE 

SMW_SETTING_OPTION1 - MAX_ERASE SMW Setting Option 1 Register - Number of Erase Shots SMW設置選項1暫存器 - 擦除射擊次數

SMW_SETTING_OPTION1_MAX_PROG 

SMW_SETTING_OPTION1 - MAX_PROG SMW Setting Option 1 Register - Number of Program Shots SMW設置選項1暫存器 - 程式射擊次數

SMW_SMP_WHV_OPTION1_SMP_WHV_OPT1 

SMW_SMP_WHV_OPTION1 - SMP_WHV_OPT1 SMW SMP WHV Option 1 Register - Smart Program WHV Option High SMW SMP WHV選項1暫存器 - 智能程式WHV選項高

SMW_SME_WHV_OPTION1_SME_WHV_OPT1 

SMW_SME_WHV_OPTION1 - SME_WHV_OPT1 SMW SME WHV Option 1 Register - Smart Erase WHV Option High SMW SME WHV選項1暫存器 - 智能擦除WHV選項高

REPAIR0_0_RDIS0_0 

REPAIR0_0 - RDIS0_0 FMU Repair 0 Block 0 Register - RDIS0_0 FMU修復0區塊0暫存器 - RDIS0_0.

  • [0b0] Repair address is valid 修復地址有效
  • [0b1] Repair address is not valid 修復地址無效
REPAIR0_0_RADR0_0 

REPAIR0_0 - RADR0_0 FMU Repair 0 Block 0 Register - RADR0_0 FMU修復0區塊0暫存器 - RADR0_0.

REPAIR0_1_RDIS0_1 

REPAIR0_1 - RDIS0_1 FMU Repair 1 Block 0 Register - RDIS0_1 FMU修復1區塊0暫存器 - RDIS0_1.

  • [0b0] Repair address is valid 修復地址有效
  • [0b1] Repair address is not valid 修復地址無效
REPAIR0_1_RADR0_1 

REPAIR0_1 - RADR0_1 FMU Repair 1 Block 0 Register - RADR0_1 FMU修復1區塊0暫存器 - RADR0_1.

REPAIR1_0_RDIS1_0 

REPAIR1_0 - RDIS1_0 FMU Repair 0 Block 1 Register - RDIS1_0 FMU修復0區塊1暫存器 - RDIS1_0.

  • [0b0] Repair address is valid 修復地址有效
  • [0b1] Repair address is not valid 修復地址無效
REPAIR1_0_RADR1_0 

REPAIR1_0 - RADR1_0 FMU Repair 0 Block 1 Register - RADR1_0 FMU修復0區塊1暫存器 - RADR1_0.

REPAIR1_1_RDIS1_1 

REPAIR1_1 - RDIS1_1 FMU Repair 1 Block 1 Register - RDIS1_1 FMU修復1區塊1暫存器 - RDIS1_1.

  • [0b0] Repair address is valid 修復地址有效
  • [0b1] Repair address is not valid 修復地址無效
REPAIR1_1_RADR1_1 

REPAIR1_1 - RADR1_1 FMU Repair 1 Block 1 Register - RADR1_1 FMU修復1區塊1暫存器 - RADR1_1.

SMW_HB_SIGNALS_SMW_ARRAY 

SMW_HB_SIGNALS - SMW_ARRAY SMW HB Signals Register - SMW Region Select SMW HB信號暫存器 - SMW區域選擇

  • [0b000] Main array 主數組
  • [0b001] IFR space only or main (and REDEN space) with IFR space for mass erase 僅IFR空間或主（和REDEN空間）與IFR空間進行大量擦除
  • [0b010] IFR1 space IFR1空間
  • [0b100] REDEN space REDEN空間
SMW_HB_SIGNALS_USER_IFREN1 

SMW_HB_SIGNALS - USER_IFREN1 SMW HB Signals Register - IFR1 Enable SMW HB信號暫存器 - IFR1啟用

  • [0b0] IFREN1 input to the flash array is driven LOW IFREN1輸入到快閃數組被驅動為低
  • [0b1] IFREN1 input to the flash array is driven HIGH IFREN1輸入到快閃數組被驅動為高
SMW_HB_SIGNALS_USER_PV 

SMW_HB_SIGNALS - USER_PV SMW HB Signals Register - Program Verify SMW HB信號暫存器 - 程式驗證

  • [0b0] PV input to the flash array is driven LOW PV輸入到快閃數組被驅動為低
  • [0b1] PV input to the flash array is driven HIGH PV輸入到快閃數組被驅動為高
SMW_HB_SIGNALS_USER_EV 

SMW_HB_SIGNALS - USER_EV SMW HB Signals Register - Erase Verify SMW HB信號暫存器 - 擦除驗證

  • [0b0] EV input to the flash array is driven LOW EV輸入到快閃數組被驅動為低
  • [0b1] EV input to the flash array is driven HIGH EV輸入到快閃數組被驅動為高
SMW_HB_SIGNALS_USER_IFREN 

SMW_HB_SIGNALS - USER_IFREN SMW HB Signals Register - IFR Enable SMW HB信號暫存器 - IFR啟用

  • [0b0] IFREN input to the flash array is driven LOW IFREN輸入到快閃數組被驅動為低
  • [0b1] IFREN input to the flash array is driven HIGH IFREN輸入到快閃數組被驅動為高
SMW_HB_SIGNALS_USER_REDEN 

SMW_HB_SIGNALS - USER_REDEN SMW HB Signals Register - Repair Read Enable SMW HB信號暫存器 - 修復讀取啟用

  • [0b0] REDEN input to the flash array is driven LOW REDEN輸入到快閃數組被驅動為低
  • [0b1] REDEN input to the flash array is driven HIGH REDEN輸入到快閃數組被驅動為高
SMW_HB_SIGNALS_USER_HEM 

SMW_HB_SIGNALS - USER_HEM SMW HB Signals Register - High Endurance Enable SMW HB信號暫存器 - 高耐久啟用

  • [0b0] HEM input to SMW / BIST PIN_CTRL[24] is driven LOW HEM輸入到SMW / BIST PIN_CTRL[24]被驅動為低
  • [0b1] HEM input to SMW / BIST PIN_CTRL[24] is driven HIGH HEM輸入到SMW / BIST PIN_CTRL[24]被驅動為高
BIST_DUMP_CTRL_BIST_DONE 

BIST_DUMP_CTRL - BIST_DONE BIST Datadump Control Register - BIST Done BIST數據轉儲控制暫存器 - BIST完成

  • [0b0] The BIST (or data dump) is running BIST（或數據轉儲）正在運行
  • [0b1] The BIST (or data dump) has completed BIST（或數據轉儲）已完成
BIST_DUMP_CTRL_BIST_FAIL 

BIST_DUMP_CTRL - BIST_FAIL BIST Datadump Control Register - BIST Fail BIST數據轉儲控制暫存器 - BIST失敗

  • [0b0] The last BIST operation completed successfully (or could not fail) 最後一次BIST操作成功完成（或無法失敗）
  • [0b1] The last BIST operation failed 最後一次BIST操作失敗
BIST_DUMP_CTRL_DATADUMP 

BIST_DUMP_CTRL - DATADUMP BIST Datadump Control Register - Data Dump Enable BIST數據轉儲控制暫存器 - 數據轉儲啟用

BIST_DUMP_CTRL_DATADUMP_TRIG 

BIST_DUMP_CTRL - DATADUMP_TRIG BIST Datadump Control Register - Data Dump Trigger BIST數據轉儲控制暫存器 - 數據轉儲觸發

BIST_DUMP_CTRL_DATADUMP_PATT 

BIST_DUMP_CTRL - DATADUMP_PATT BIST Datadump Control Register - Data Dump Pattern Select BIST數據轉儲控制暫存器 - 數據轉儲模式選擇

  • [0b00] All ones 全1
  • [0b01] All zeroes 全0
  • [0b10] Checkerboard 棋盤
  • [0b11] Inverse checkerboard 反向棋盤
BIST_DUMP_CTRL_DATADUMP_MRGEN 

BIST_DUMP_CTRL - DATADUMP_MRGEN BIST Datadump Control Register - Data Dump Margin Enable BIST數據轉儲控制暫存器 - 數據轉儲邊際啟用

  • [0b0] Normal read pulse shape 正常讀取脈衝形狀
  • [0b1] Margin read pulse shape 邊際讀取脈衝形狀
BIST_DUMP_CTRL_DATADUMP_MRGTYPE 

BIST_DUMP_CTRL - DATADUMP_MRGTYPE BIST Datadump Control Register - Data Dump Margin Type BIST數據轉儲控制暫存器 - 數據轉儲邊際類型

  • [0b0] DIN method used 使用DIN方法
  • [0b1] TM method used 使用TM方法
ATX_PIN_CTRL_TM_TO_ATX 

ATX_PIN_CTRL - TM_TO_ATX ATX Pin Control Register - TM to ATX ATX引腳控制暫存器 - TM到ATX.

  • [0b00000001] TM[0] to ATX0 TM[0]到ATX0
  • [0b00000010] TM[1] to ATX0 TM[1]到ATX0
  • [0b00000100] TM[2] to ATX0 TM[2]到ATX0
  • [0b00001000] TM[3] to ATX0 TM[3]到ATX0
  • [0b00010000] TM[0] to ATX1 TM[0]到ATX1
  • [0b00100000] TM[1] to ATX1 TM[1]到ATX1
  • [0b01000000] TM[2] to ATX1 TM[2]到ATX1
  • [0b10000000] TM[3] to ATX1 TM[3]到ATX1
FAILCNT_FAILCNT 

FAILCNT - FAILCNT Fail Count Register - Fail Count 失敗計數暫存器 - 失敗計數

PGM_PULSE_CNT0_PGM_CNT0 

PGM_PULSE_CNT0 - PGM_CNT0 Block 0 Program Pulse Count Register - Program Pulse Count 區塊0程式脈衝計數暫存器 - 程式脈衝計數

PGM_PULSE_CNT1_PGM_CNT1 

PGM_PULSE_CNT1 - PGM_CNT1 Block 1 Program Pulse Count Register - Program Pulse Count 區塊1程式脈衝計數暫存器 - 程式脈衝計數

ERS_PULSE_CNT_ERS_CNT0 

ERS_PULSE_CNT - ERS_CNT0 Erase Pulse Count Register - Block 0 Erase Pulse Count 擦除脈衝計數暫存器 - 區塊0擦除脈衝計數

ERS_PULSE_CNT_ERS_CNT1 

ERS_PULSE_CNT - ERS_CNT1 Erase Pulse Count Register - Block 1 Erase Pulse Count 擦除脈衝計數暫存器 - 區塊1擦除脈衝計數

MAX_PULSE_CNT_LAST_PCNT 

MAX_PULSE_CNT - LAST_PCNT Maximum Pulse Count Register - Last SMW Operation's Pulse Count 最大脈衝計數暫存器 - 最後一次SMW操作的脈衝計數

MAX_PULSE_CNT_MAX_ERS_CNT 

MAX_PULSE_CNT - MAX_ERS_CNT Maximum Pulse Count Register - Maximum Erase Pulse Count 最大脈衝計數暫存器 - 最大擦除脈衝計數

MAX_PULSE_CNT_MAX_PGM_CNT 

MAX_PULSE_CNT - MAX_PGM_CNT Maximum Pulse Count Register - Maximum Program Pulse Count 最大脈衝計數暫存器 - 最大程式脈衝計數

PORT_CTRL_BDONE_SEL 

PORT_CTRL - BDONE_SEL Port Control Register - BIST Done Select 端口控制暫存器 - BIST完成選擇

  • [0b00] Select internal bist_done signal from current module instantiation 從當前模塊實例化中選擇內部bist_done信號
  • [0b01] Select ipt_bist_fail signal from current module instantiation 從當前模塊實例化中選擇ipt_bist_fail信號
  • [0b10] Select ipt_bist_done signal from other module instantiation 從其他模塊實例化中選擇ipt_bist_done信號
  • [0b11] Select AND of internal bist_done signal from current module instantiation with ipt_bist_done signal from other module instantiation 從當前模塊實例化中選擇內部bist_done信號與其他模塊實例化中的ipt_bist_done信號的AND
PORT_CTRL_BSDO_SEL 

PORT_CTRL - BSDO_SEL Port Control Register - BIST Serial Data Output Select 端口控制暫存器 - BIST串行數據輸出選擇

  • [0b00] Select internal bist_sdo signal from current module instantiation 從當前模塊實例化中選擇內部bist_sdo信號
  • [0b01] Select ipt_bist_done signal from current module instantiation 從當前模塊實例化中選擇ipt_bist_done信號
  • [0b10] Select ipt_bist_sdo signal from other module instantiation 從其他模塊實例化中選擇ipt_bist_sdo信號
  • [0b11] Select ipt_bist_done signal from other module instantiation 從其他模塊實例化中選擇ipt_bist_done信號

函式說明文件

◆ operator+()

unsigned int mcxa153::chip::fmu::operator+ ( Shift e)
constexpr
參數
e
傳回值
constexpr unsigned int