命名空間(Namespaces)
namespace	ctimer0

namespace	ctimer1

namespace	ctimer2

namespace	gpio0

namespace	gpio1

namespace	gpio2

namespace	gpio3

namespace	lpi2c0

namespace	lpspi0

namespace	lpspi1

namespace	lpuart0

namespace	lpuart1

namespace	lpuart2

列舉型態
enum struct	Mux : uint32 { P0_0_GPIO = genMuxAlt(core::mux::MuxPortPin::P0_0, 0) , P0_0_TMS_SWDIO = genMuxAlt(core::mux::MuxPortPin::P0_0, 1) , P0_0_LPUART0_RTS_B = genMuxAlt(core::mux::MuxPortPin::P0_0, 2) , P0_0_LPSPI0_PCS0 = genMuxAlt(core::mux::MuxPortPin::P0_0, 3) , P0_0_CT_INP0 = genMuxAlt(core::mux::MuxPortPin::P0_0, 4) , P0_1_GPIO = genMuxAlt(core::mux::MuxPortPin::P0_1, 0) , P0_1_TCLK_SWCLK = genMuxAlt(core::mux::MuxPortPin::P0_1, 1) , P0_1_LPUART0_CTS_B = genMuxAlt(core::mux::MuxPortPin::P0_1, 2) , P0_1_LPSPI0_SDI = genMuxAlt(core::mux::MuxPortPin::P0_1, 3) , P0_1_CT_INP1 = genMuxAlt(core::mux::MuxPortPin::P0_1, 4) , P0_2_GPIO = genMuxAlt(core::mux::MuxPortPin::P0_2, 0) , P0_2_TDO_SWO = genMuxAlt(core::mux::MuxPortPin::P0_2, 1) , P0_2_LPUART0_RXD = genMuxAlt(core::mux::MuxPortPin::P0_2, 2) , P0_2_LPSPI0_SCK = genMuxAlt(core::mux::MuxPortPin::P0_2, 3) , P0_2_CT0_MAT0 = genMuxAlt(core::mux::MuxPortPin::P0_2, 4) , P0_2_UTICK_CAP0 = genMuxAlt(core::mux::MuxPortPin::P0_2, 5) , P0_2_I3C0_PUR = genMuxAlt(core::mux::MuxPortPin::P0_2, 10) , P0_3_GPIO = genMuxAlt(core::mux::MuxPortPin::P0_3, 0) , P0_3_TDI = genMuxAlt(core::mux::MuxPortPin::P0_3, 1) , P0_3_LPUART0_TXD = genMuxAlt(core::mux::MuxPortPin::P0_3, 2) , P0_3_LPSPI0_SDO = genMuxAlt(core::mux::MuxPortPin::P0_3, 3) , P0_3_CT0_MAT1 = genMuxAlt(core::mux::MuxPortPin::P0_3, 4) , P0_3_UTICK_CAP1 = genMuxAlt(core::mux::MuxPortPin::P0_3, 5) , P0_3_CMP0_OUT = genMuxAlt(core::mux::MuxPortPin::P0_3, 8) , P0_6_GPIO = genMuxAlt(core::mux::MuxPortPin::P0_6, 0) , P0_6_LPI2C0_HREQ = genMuxAlt(core::mux::MuxPortPin::P0_6, 2) , P0_6_LPSPI0_PCS1 = genMuxAlt(core::mux::MuxPortPin::P0_6, 3) , P0_6_CT_INP2 = genMuxAlt(core::mux::MuxPortPin::P0_6, 4) , P0_6_CMP1_OUT = genMuxAlt(core::mux::MuxPortPin::P0_6, 8) , P0_6_CLKOUT = genMuxAlt(core::mux::MuxPortPin::P0_6, 12) , P0_16_GPIO = genMuxAlt(core::mux::MuxPortPin::P0_16, 0) , P0_16_LPI2C0_SDA = genMuxAlt(core::mux::MuxPortPin::P0_16, 2) , P0_16_LPSPI0_PCS2 = genMuxAlt(core::mux::MuxPortPin::P0_16, 3) , P0_16_CT0_MAT0 = genMuxAlt(core::mux::MuxPortPin::P0_16, 4) , P0_16_UTICK_CAP2 = genMuxAlt(core::mux::MuxPortPin::P0_16, 5) , P0_16_I3C0_SDA = genMuxAlt(core::mux::MuxPortPin::P0_16, 10) , P0_17_GPIO = genMuxAlt(core::mux::MuxPortPin::P0_17, 0) , P0_17_LPI2C0_SCL = genMuxAlt(core::mux::MuxPortPin::P0_17, 2) , P0_17_LPSPI0_PCS3 = genMuxAlt(core::mux::MuxPortPin::P0_17, 3) , P0_17_CT0_MAT1 = genMuxAlt(core::mux::MuxPortPin::P0_17, 4) , P0_17_UTICK_CAP3 = genMuxAlt(core::mux::MuxPortPin::P0_17, 5) , P0_17_I3C0_SCL = genMuxAlt(core::mux::MuxPortPin::P0_17, 10) , P1_0_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_0, 0) , P1_0_TRIG_IN0 = genMuxAlt(core::mux::MuxPortPin::P1_0, 1) , P1_0_LPSPI0_SDO = genMuxAlt(core::mux::MuxPortPin::P1_0, 2) , P1_0_LPI2C0_SDA = genMuxAlt(core::mux::MuxPortPin::P1_0, 3) , P1_0_CT_INP4 = genMuxAlt(core::mux::MuxPortPin::P1_0, 4) , P1_0_CT0_MAT2 = genMuxAlt(core::mux::MuxPortPin::P1_0, 5) , P1_1_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_1, 0) , P1_1_TRIG_IN1 = genMuxAlt(core::mux::MuxPortPin::P1_1, 1) , P1_1_LPSPI0_SCK = genMuxAlt(core::mux::MuxPortPin::P1_1, 2) , P1_1_LPI2C0_SCL = genMuxAlt(core::mux::MuxPortPin::P1_1, 3) , P1_1_CT_INP5 = genMuxAlt(core::mux::MuxPortPin::P1_1, 4) , P1_1_CT0_MAT3 = genMuxAlt(core::mux::MuxPortPin::P1_1, 5) , P1_2_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_2, 0) , P1_2_TRIG_OUT0 = genMuxAlt(core::mux::MuxPortPin::P1_2, 1) , P1_2_LPSPI0_SDI = genMuxAlt(core::mux::MuxPortPin::P1_2, 2) , P1_2_LPI2C0_SDAS = genMuxAlt(core::mux::MuxPortPin::P1_2, 3) , P1_2_CT1_MAT0 = genMuxAlt(core::mux::MuxPortPin::P1_2, 4) , P1_2_CT_INP0 = genMuxAlt(core::mux::MuxPortPin::P1_2, 5) , P1_3_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_3, 0) , P1_3_TRIG_OUT1 = genMuxAlt(core::mux::MuxPortPin::P1_3, 1) , P1_3_LPSPI0_PCS0 = genMuxAlt(core::mux::MuxPortPin::P1_3, 2) , P1_3_LPI2C0_SCLS = genMuxAlt(core::mux::MuxPortPin::P1_3, 3) , P1_3_CT1_MAT1 = genMuxAlt(core::mux::MuxPortPin::P1_3, 4) , P1_3_CT_INP1 = genMuxAlt(core::mux::MuxPortPin::P1_3, 5) , P1_4_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_4, 0) , P1_4_FREQME_CLK_IN0 = genMuxAlt(core::mux::MuxPortPin::P1_4, 1) , P1_4_LPSPI0_PCS3 = genMuxAlt(core::mux::MuxPortPin::P1_4, 2) , P1_4_LPUART2_RXD = genMuxAlt(core::mux::MuxPortPin::P1_4, 3) , P1_4_CT1_MAT2 = genMuxAlt(core::mux::MuxPortPin::P1_4, 4) , P1_5_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_5, 0) , P1_5_FREQME_CLK_IN1 = genMuxAlt(core::mux::MuxPortPin::P1_5, 1) , P1_5_LPSPI0_PCS2 = genMuxAlt(core::mux::MuxPortPin::P1_5, 2) , P1_5_LPUART2_TXD = genMuxAlt(core::mux::MuxPortPin::P1_5, 3) , P1_5_CT1_MAT3 = genMuxAlt(core::mux::MuxPortPin::P1_5, 4) , P1_6_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_6, 0) , P1_6_TRIG_IN2 = genMuxAlt(core::mux::MuxPortPin::P1_6, 1) , P1_6_LPSPI0_PCS1 = genMuxAlt(core::mux::MuxPortPin::P1_6, 2) , P1_6_LPUART2_RTS_B = genMuxAlt(core::mux::MuxPortPin::P1_6, 3) , P1_6_CT_INP6 = genMuxAlt(core::mux::MuxPortPin::P1_6, 4) , P1_7_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_7, 0) , P1_7_TRIG_OUT2 = genMuxAlt(core::mux::MuxPortPin::P1_7, 1) , P1_7_LPUART2_CTS_B = genMuxAlt(core::mux::MuxPortPin::P1_7, 3) , P1_7_CT_INP7 = genMuxAlt(core::mux::MuxPortPin::P1_7, 4) , P1_8_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_8, 0) , P1_8_LPUART1_RXD = genMuxAlt(core::mux::MuxPortPin::P1_8, 2) , P1_8_LPI2C0_SDA = genMuxAlt(core::mux::MuxPortPin::P1_8, 3) , P1_8_CT_INP8 = genMuxAlt(core::mux::MuxPortPin::P1_8, 4) , P1_8_CT0_MAT2 = genMuxAlt(core::mux::MuxPortPin::P1_8, 5) , P1_8_I3C0_SDA = genMuxAlt(core::mux::MuxPortPin::P1_8, 10) , P1_9_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_9, 0) , P1_9_LPUART1_TXD = genMuxAlt(core::mux::MuxPortPin::P1_9, 2) , P1_9_LPI2C0_SCL = genMuxAlt(core::mux::MuxPortPin::P1_9, 3) , P1_9_CT_INP9 = genMuxAlt(core::mux::MuxPortPin::P1_9, 4) , P1_9_CT0_MAT3 = genMuxAlt(core::mux::MuxPortPin::P1_9, 5) , P1_9_I3C0_SCL = genMuxAlt(core::mux::MuxPortPin::P1_9, 10) , P1_10_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_10, 0) , P1_10_LPUART1_RTS_B = genMuxAlt(core::mux::MuxPortPin::P1_10, 2) , P1_10_LPI2C0_SDAS = genMuxAlt(core::mux::MuxPortPin::P1_10, 3) , P1_10_CT2_MAT0 = genMuxAlt(core::mux::MuxPortPin::P1_10, 4) , P1_11_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_11, 0) , P1_11_TRIG_OUT2 = genMuxAlt(core::mux::MuxPortPin::P1_11, 1) , P1_11_LPUART1_CTS_B = genMuxAlt(core::mux::MuxPortPin::P1_11, 2) , P1_11_LPI2C0_SCLS = genMuxAlt(core::mux::MuxPortPin::P1_11, 3) , P1_11_CT2_MAT1 = genMuxAlt(core::mux::MuxPortPin::P1_11, 4) , P1_11_I3C0_PUR = genMuxAlt(core::mux::MuxPortPin::P1_11, 10) , P1_12_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_12, 0) , P1_12_LPUART2_RXD = genMuxAlt(core::mux::MuxPortPin::P1_12, 3) , P1_12_CT2_MAT2 = genMuxAlt(core::mux::MuxPortPin::P1_12, 4) , P1_13_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_13, 0) , P1_13_TRIG_IN3 = genMuxAlt(core::mux::MuxPortPin::P1_13, 1) , P1_13_LPUART2_TXD = genMuxAlt(core::mux::MuxPortPin::P1_13, 3) , P1_13_CT2_MAT3 = genMuxAlt(core::mux::MuxPortPin::P1_13, 4) , P1_29_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_29, 0) , P1_29_RESET_B = genMuxAlt(core::mux::MuxPortPin::P1_29, 1) , P1_29_SPC_LPREQ = genMuxAlt(core::mux::MuxPortPin::P1_29, 2) , P1_30_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_30, 0) , P1_30_TRIG_OUT3 = genMuxAlt(core::mux::MuxPortPin::P1_30, 1) , P1_30_LPI2C0_SDA = genMuxAlt(core::mux::MuxPortPin::P1_30, 3) , P1_30_CT_INP16 = genMuxAlt(core::mux::MuxPortPin::P1_30, 4) , P1_30_I3C0_SDA = genMuxAlt(core::mux::MuxPortPin::P1_30, 10) , P1_31_GPIO = genMuxAlt(core::mux::MuxPortPin::P1_31, 0) , P1_31_TRIG_IN4 = genMuxAlt(core::mux::MuxPortPin::P1_31, 1) , P1_31_LPI2C0_SCL = genMuxAlt(core::mux::MuxPortPin::P1_31, 3) , P1_31_CT_INP17 = genMuxAlt(core::mux::MuxPortPin::P1_31, 4) , P1_31_I3C0_SCL = genMuxAlt(core::mux::MuxPortPin::P1_31, 10) , P2_0_GPIO = genMuxAlt(core::mux::MuxPortPin::P2_0, 0) , P2_0_TRIG_IN6 = genMuxAlt(core::mux::MuxPortPin::P2_0, 1) , P2_0_LPUART0_RXD = genMuxAlt(core::mux::MuxPortPin::P2_0, 2) , P2_0_CT_INP16 = genMuxAlt(core::mux::MuxPortPin::P2_0, 4) , P2_0_CT2_MAT0 = genMuxAlt(core::mux::MuxPortPin::P2_0, 5) , P2_1_GPIO = genMuxAlt(core::mux::MuxPortPin::P2_1, 0) , P2_1_TRIG_IN7 = genMuxAlt(core::mux::MuxPortPin::P2_1, 1) , P2_1_LPUART0_TXD = genMuxAlt(core::mux::MuxPortPin::P2_1, 2) , P2_1_CT_INP17 = genMuxAlt(core::mux::MuxPortPin::P2_1, 4) , P2_1_CT2_MAT1 = genMuxAlt(core::mux::MuxPortPin::P2_1, 5) , P2_2_GPIO = genMuxAlt(core::mux::MuxPortPin::P2_2, 0) , P2_2_TRIG_IN6 = genMuxAlt(core::mux::MuxPortPin::P2_2, 1) , P2_2_LPUART0_RTS_B = genMuxAlt(core::mux::MuxPortPin::P2_2, 2) , P2_2_LPUART2_TXD = genMuxAlt(core::mux::MuxPortPin::P2_2, 3) , P2_2_CT_INP12 = genMuxAlt(core::mux::MuxPortPin::P2_2, 4) , P2_2_CT2_MAT2 = genMuxAlt(core::mux::MuxPortPin::P2_2, 5) , P2_3_GPIO = genMuxAlt(core::mux::MuxPortPin::P2_3, 0) , P2_3_TRIG_IN7 = genMuxAlt(core::mux::MuxPortPin::P2_3, 1) , P2_3_LPUART0_CTS_B = genMuxAlt(core::mux::MuxPortPin::P2_3, 2) , P2_3_LPUART2_RXD = genMuxAlt(core::mux::MuxPortPin::P2_3, 3) , P2_3_CT_INP13 = genMuxAlt(core::mux::MuxPortPin::P2_3, 4) , P2_3_CT2_MAT3 = genMuxAlt(core::mux::MuxPortPin::P2_3, 5) , P2_4_GPIO = genMuxAlt(core::mux::MuxPortPin::P2_4, 0) , P2_4_CT_INP14 = genMuxAlt(core::mux::MuxPortPin::P2_4, 1) , P2_4_CT1_MAT0 = genMuxAlt(core::mux::MuxPortPin::P2_4, 2) , P2_5_GPIO = genMuxAlt(core::mux::MuxPortPin::P2_5, 0) , P2_5_CT_INP15 = genMuxAlt(core::mux::MuxPortPin::P2_5, 1) , P2_5_CT1_MAT1 = genMuxAlt(core::mux::MuxPortPin::P2_5, 2) , P2_6_GPIO = genMuxAlt(core::mux::MuxPortPin::P2_6, 0) , P2_6_TRIG_OUT4 = genMuxAlt(core::mux::MuxPortPin::P2_6, 1) , P2_6_LPSPI1_PCS1 = genMuxAlt(core::mux::MuxPortPin::P2_6, 2) , P2_6_CT_INP18 = genMuxAlt(core::mux::MuxPortPin::P2_6, 4) , P2_6_CT1_MAT2 = genMuxAlt(core::mux::MuxPortPin::P2_6, 5) , P2_7_GPIO = genMuxAlt(core::mux::MuxPortPin::P2_7, 0) , P2_7_TRIG_IN5 = genMuxAlt(core::mux::MuxPortPin::P2_7, 1) , P2_7_CT_INP19 = genMuxAlt(core::mux::MuxPortPin::P2_7, 4) , P2_7_CT1_MAT3 = genMuxAlt(core::mux::MuxPortPin::P2_7, 5) , P2_12_GPIO = genMuxAlt(core::mux::MuxPortPin::P2_12, 0) , P2_12_USB0_VBUS_DET = genMuxAlt(core::mux::MuxPortPin::P2_12, 1) , P2_12_LPSPI1_SCK = genMuxAlt(core::mux::MuxPortPin::P2_12, 2) , P2_12_LPUART1_RXD = genMuxAlt(core::mux::MuxPortPin::P2_12, 3) , P2_12_CT0_MAT0 = genMuxAlt(core::mux::MuxPortPin::P2_12, 5) , P2_13_GPIO = genMuxAlt(core::mux::MuxPortPin::P2_13, 0) , P2_13_TRIG_IN8 = genMuxAlt(core::mux::MuxPortPin::P2_13, 1) , P2_13_LPSPI1_SDO = genMuxAlt(core::mux::MuxPortPin::P2_13, 2) , P2_13_LPUART1_TXD = genMuxAlt(core::mux::MuxPortPin::P2_13, 3) , P2_13_CT0_MAT1 = genMuxAlt(core::mux::MuxPortPin::P2_13, 5) , P2_16_GPIO = genMuxAlt(core::mux::MuxPortPin::P2_16, 0) , P2_16_LPSPI1_SDI = genMuxAlt(core::mux::MuxPortPin::P2_16, 2) , P2_16_LPUART1_RTS_B = genMuxAlt(core::mux::MuxPortPin::P2_16, 3) , P2_16_CT0_MAT2 = genMuxAlt(core::mux::MuxPortPin::P2_16, 5) , P3_0_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_0, 0) , P3_0_TRIG_IN0 = genMuxAlt(core::mux::MuxPortPin::P3_0, 1) , P3_0_CT_INP16 = genMuxAlt(core::mux::MuxPortPin::P3_0, 4) , P3_0_PWM0_A0 = genMuxAlt(core::mux::MuxPortPin::P3_0, 5) , P3_1_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_1, 0) , P3_1_TRIG_IN1 = genMuxAlt(core::mux::MuxPortPin::P3_1, 1) , P3_1_CT_INP17 = genMuxAlt(core::mux::MuxPortPin::P3_1, 4) , P3_1_PWM0_B0 = genMuxAlt(core::mux::MuxPortPin::P3_1, 5) , P3_1_FREQME_CLK_OUT0 = genMuxAlt(core::mux::MuxPortPin::P3_1, 12) , P3_6_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_6, 0) , P3_6_CLKOUT = genMuxAlt(core::mux::MuxPortPin::P3_6, 1) , P3_6_LPSPI1_PCS3 = genMuxAlt(core::mux::MuxPortPin::P3_6, 2) , P3_6_PWM0_A0 = genMuxAlt(core::mux::MuxPortPin::P3_6, 5) , P3_6_FREQME_CLK_OUT1 = genMuxAlt(core::mux::MuxPortPin::P3_6, 12) , P3_7_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_7, 0) , P3_7_TRIG_IN2 = genMuxAlt(core::mux::MuxPortPin::P3_7, 1) , P3_7_LPSPI1_PCS2 = genMuxAlt(core::mux::MuxPortPin::P3_7, 2) , P3_7_PWM0_B0 = genMuxAlt(core::mux::MuxPortPin::P3_7, 5) , P3_8_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_8, 0) , P3_8_TRIG_IN3 = genMuxAlt(core::mux::MuxPortPin::P3_8, 1) , P3_8_LPSPI1_SDO = genMuxAlt(core::mux::MuxPortPin::P3_8, 2) , P3_8_LPUART1_RXD = genMuxAlt(core::mux::MuxPortPin::P3_8, 3) , P3_8_CT_INP4 = genMuxAlt(core::mux::MuxPortPin::P3_8, 4) , P3_8_PWM0_A1 = genMuxAlt(core::mux::MuxPortPin::P3_8, 5) , P3_8_CLKOUT = genMuxAlt(core::mux::MuxPortPin::P3_8, 12) , P3_9_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_9, 0) , P3_9_TRIG_IN4 = genMuxAlt(core::mux::MuxPortPin::P3_9, 1) , P3_9_LPSPI1_SDI = genMuxAlt(core::mux::MuxPortPin::P3_9, 2) , P3_9_LPUART1_TXD = genMuxAlt(core::mux::MuxPortPin::P3_9, 3) , P3_9_CT_INP5 = genMuxAlt(core::mux::MuxPortPin::P3_9, 4) , P3_9_PWM0_B1 = genMuxAlt(core::mux::MuxPortPin::P3_9, 5) , P3_10_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_10, 0) , P3_10_TRIG_IN5 = genMuxAlt(core::mux::MuxPortPin::P3_10, 1) , P3_10_LPSPI1_SCK = genMuxAlt(core::mux::MuxPortPin::P3_10, 2) , P3_10_LPUART1_RTS_B = genMuxAlt(core::mux::MuxPortPin::P3_10, 3) , P3_10_CT1_MAT0 = genMuxAlt(core::mux::MuxPortPin::P3_10, 4) , P3_10_PWM0_A2 = genMuxAlt(core::mux::MuxPortPin::P3_10, 5) , P3_11_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_11, 0) , P3_11_TRIG_IN6 = genMuxAlt(core::mux::MuxPortPin::P3_11, 1) , P3_11_LPSPI1_PCS0 = genMuxAlt(core::mux::MuxPortPin::P3_11, 2) , P3_11_LPUART1_CTS_B = genMuxAlt(core::mux::MuxPortPin::P3_11, 3) , P3_11_CT1_MAT1 = genMuxAlt(core::mux::MuxPortPin::P3_11, 4) , P3_11_PWM0_B2 = genMuxAlt(core::mux::MuxPortPin::P3_11, 5) , P3_12_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_12, 0) , P3_12_LPUART2_RTS_B = genMuxAlt(core::mux::MuxPortPin::P3_12, 2) , P3_12_CT1_MAT2 = genMuxAlt(core::mux::MuxPortPin::P3_12, 4) , P3_12_PWM0_X0 = genMuxAlt(core::mux::MuxPortPin::P3_12, 5) , P3_13_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_13, 0) , P3_13_LPUART2_CTS_B = genMuxAlt(core::mux::MuxPortPin::P3_13, 2) , P3_13_CT1_MAT3 = genMuxAlt(core::mux::MuxPortPin::P3_13, 4) , P3_13_PWM0_X1 = genMuxAlt(core::mux::MuxPortPin::P3_13, 5) , P3_14_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_14, 0) , P3_14_LPUART2_RXD = genMuxAlt(core::mux::MuxPortPin::P3_14, 2) , P3_14_CT_INP6 = genMuxAlt(core::mux::MuxPortPin::P3_14, 4) , P3_14_PWM0_X2 = genMuxAlt(core::mux::MuxPortPin::P3_14, 5) , P3_15_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_15, 0) , P3_15_LPUART2_TXD = genMuxAlt(core::mux::MuxPortPin::P3_15, 2) , P3_15_CT_INP7 = genMuxAlt(core::mux::MuxPortPin::P3_15, 4) , P3_27_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_27, 0) , P3_27_TRIG_OUT7 = genMuxAlt(core::mux::MuxPortPin::P3_27, 1) , P3_27_LPI2C0_SCL = genMuxAlt(core::mux::MuxPortPin::P3_27, 2) , P3_27_CT_INP13 = genMuxAlt(core::mux::MuxPortPin::P3_27, 4) , P3_28_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_28, 0) , P3_28_TRIG_IN11 = genMuxAlt(core::mux::MuxPortPin::P3_28, 1) , P3_28_LPI2C0_SDA = genMuxAlt(core::mux::MuxPortPin::P3_28, 2) , P3_28_CT_INP12 = genMuxAlt(core::mux::MuxPortPin::P3_28, 4) , P3_29_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_29, 0) , P3_29_ISPMODE_N = genMuxAlt(core::mux::MuxPortPin::P3_29, 1) , P3_29_CT_INP3 = genMuxAlt(core::mux::MuxPortPin::P3_29, 4) , P3_30_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_30, 0) , P3_30_TRIG_OUT6 = genMuxAlt(core::mux::MuxPortPin::P3_30, 1) , P3_30_CT0_MAT2 = genMuxAlt(core::mux::MuxPortPin::P3_30, 4) , P3_31_GPIO = genMuxAlt(core::mux::MuxPortPin::P3_31, 0) , P3_31_TRIG_IN10 = genMuxAlt(core::mux::MuxPortPin::P3_31, 1) , P3_31_CT0_MAT3 = genMuxAlt(core::mux::MuxPortPin::P3_31, 4) , NONE = 0xFFFFFFFF }
	MCXA153 引腳多功能選擇列舉更多...

enum struct	MuxPortPin : uint16 { P0_0 = genMuxPortPin(0, 0) , P0_1 = genMuxPortPin(0, 1) , P0_2 = genMuxPortPin(0, 2) , P0_3 = genMuxPortPin(0, 3) , P0_6 = genMuxPortPin(0, 6) , P0_16 = genMuxPortPin(0, 16) , P0_17 = genMuxPortPin(0, 17) , P1_0 = genMuxPortPin(1, 0) , P1_1 = genMuxPortPin(1, 1) , P1_2 = genMuxPortPin(1, 2) , P1_3 = genMuxPortPin(1, 3) , P1_4 = genMuxPortPin(1, 4) , P1_5 = genMuxPortPin(1, 5) , P1_6 = genMuxPortPin(1, 6) , P1_7 = genMuxPortPin(1, 7) , P1_8 = genMuxPortPin(1, 8) , P1_9 = genMuxPortPin(1, 9) , P1_10 = genMuxPortPin(1, 10) , P1_11 = genMuxPortPin(1, 11) , P1_12 = genMuxPortPin(1, 12) , P1_13 = genMuxPortPin(1, 13) , P1_29 = genMuxPortPin(1, 29) , P1_30 = genMuxPortPin(1, 30) , P1_31 = genMuxPortPin(1, 31) , P2_0 = genMuxPortPin(2, 0) , P2_1 = genMuxPortPin(2, 1) , P2_2 = genMuxPortPin(2, 2) , P2_3 = genMuxPortPin(2, 3) , P2_4 = genMuxPortPin(2, 4) , P2_5 = genMuxPortPin(2, 5) , P2_6 = genMuxPortPin(2, 6) , P2_7 = genMuxPortPin(2, 7) , P2_12 = genMuxPortPin(2, 12) , P2_13 = genMuxPortPin(2, 13) , P2_16 = genMuxPortPin(2, 16) , P3_0 = genMuxPortPin(3, 0) , P3_1 = genMuxPortPin(3, 1) , P3_6 = genMuxPortPin(3, 6) , P3_7 = genMuxPortPin(3, 7) , P3_8 = genMuxPortPin(3, 8) , P3_9 = genMuxPortPin(3, 9) , P3_10 = genMuxPortPin(3, 10) , P3_11 = genMuxPortPin(3, 11) , P3_12 = genMuxPortPin(3, 12) , P3_13 = genMuxPortPin(3, 13) , P3_14 = genMuxPortPin(3, 14) , P3_15 = genMuxPortPin(3, 15) , P3_27 = genMuxPortPin(3, 27) , P3_28 = genMuxPortPin(3, 28) , P3_29 = genMuxPortPin(3, 29) , P3_30 = genMuxPortPin(3, 30) , P3_31 = genMuxPortPin(3, 31) }
	MCXA153 引腳埠位編碼列舉更多...

函式
constexpr uint32	operator+ (Mux e)
	Mux 枚舉轉換為 uint32.

constexpr uint16	operator+ (MuxPortPin e)
	MuxPortPin 枚舉轉換為 uint16.

詳細描述

SPDX-License-Identifier: MIT

列舉型態說明文件

◆ Mux

enum struct mcxa153::core::mux::Mux : uint32

strong

MCXA153 引腳多功能選擇列舉

定義 MCXA153 微控制器的引腳多功能複用配置。每個值包含：

埠位元組 (Port/Pin)：標識實體引腳位置
替代功能編號 (Alt)：選擇該引腳的功能模式

格式：PX_Y_FUNCTION，其中：

X：GPIO埠號 (0-3)
Y：引腳號 (0-31)
FUNCTION：功能名稱

註: 使用 genMuxAlt() 函數組合埠引腳和替代功能編號

列舉值
P0_0_GPIO	P0_0 GPIO模式
P0_0_TMS_SWDIO	P0_0 JTAG測試模式選擇/SWD資料輸入輸出
P0_0_LPUART0_RTS_B	P0_0 LPUART0請求發送反向
P0_0_LPSPI0_PCS0	P0_0 LPSPI0片選0.
P0_0_CT_INP0	P0_0 定時器輸入0. P0_0 定時器輸入0
P0_1_GPIO	P0_1 GPIO模式
P0_1_TCLK_SWCLK	P0_1 JTAG測試時脈/SWD時脈
P0_1_LPUART0_CTS_B	P0_1 LPUART0清除發送反向
P0_1_LPSPI0_SDI	P0_1 LPSPI0串列資料輸入
P0_1_CT_INP1	P0_1 定時器輸入1.
P0_2_GPIO	P0_2 GPIO模式
P0_2_TDO_SWO	P0_2 JTAG測試資料輸出/SWD輸出
P0_2_LPUART0_RXD	P0_2 LPUART0接收資料
P0_2_LPSPI0_SCK	P0_2 LPSPI0串列時脈
P0_2_CT0_MAT0	P0_2 定時器0匹配輸出0.
P0_2_UTICK_CAP0	P0_2 微定時器捕獲0.
P0_2_I3C0_PUR	P0_2 I3C0上拉電阻
P0_3_GPIO	P0_3 GPIO模式
P0_3_TDI	P0_3 JTAG測試資料輸入
P0_3_LPUART0_TXD	P0_3 LPUART0傳送資料
P0_3_LPSPI0_SDO	P0_3 LPSPI0串列資料輸出
P0_3_CT0_MAT1	P0_3 定時器0匹配輸出1.
P0_3_UTICK_CAP1	P0_3 微定時器捕獲1.
P0_3_CMP0_OUT	P0_3 比較器0輸出
P0_6_GPIO	P0_6 GPIO模式
P0_6_LPI2C0_HREQ	P0_6 LPI2C0主機請求
P0_6_LPSPI0_PCS1	P0_6 LPSPI0片選1.
P0_6_CT_INP2	P0_6 定時器輸入2.
P0_6_CMP1_OUT	P0_6 比較器1輸出
P0_6_CLKOUT	P0_6 時脈輸出
P0_16_GPIO	P0_16 GPIO模式
P0_16_LPI2C0_SDA	P0_16 LPI2C0串列資料線
P0_16_LPSPI0_PCS2	P0_16 LPSPI0片選2.
P0_16_CT0_MAT0	P0_16 定時器0匹配輸出0.
P0_16_UTICK_CAP2	P0_16 微定時器捕獲2.
P0_16_I3C0_SDA	P0_16 I3C0串列資料線
P0_17_GPIO	P0_17 GPIO模式
P0_17_LPI2C0_SCL	P0_17 LPI2C0串列時脈線
P0_17_LPSPI0_PCS3	P0_17 LPSPI0片選3.
P0_17_CT0_MAT1	P0_17 定時器0匹配輸出1. P0_17 定時器0匹配輸出1
P0_17_UTICK_CAP3	P0_17 微定時器捕獲3.
P0_17_I3C0_SCL	P0_17 I3C0串列時脈線
P1_0_GPIO	P1_0 GPIO模式
P1_0_TRIG_IN0	P1_0 觸發輸入0.
P1_0_LPSPI0_SDO	P1_0 LPSPI0串列資料輸出
P1_0_LPI2C0_SDA	P1_0 LPI2C0串列資料線
P1_0_CT_INP4	P1_0 定時器輸入4.
P1_0_CT0_MAT2	P1_0 定時器0匹配輸出2.
P1_1_GPIO	P1_1 GPIO模式
P1_1_TRIG_IN1	P1_1 觸發輸入1.
P1_1_LPSPI0_SCK	P1_1 LPSPI0串列時脈
P1_1_LPI2C0_SCL	P1_1 LPI2C0串列時脈線
P1_1_CT_INP5	P1_1 定時器輸入5.
P1_1_CT0_MAT3	P1_1 定時器0匹配輸出3.
P1_2_GPIO	P1_2 GPIO模式
P1_2_TRIG_OUT0	P1_2 觸發輸出0.
P1_2_LPSPI0_SDI	P1_2 LPSPI0串列資料輸入
P1_2_LPI2C0_SDAS	P1_2 LPI2C0串列資料同步
P1_2_CT1_MAT0	P1_2 定時器1匹配輸出0.
P1_2_CT_INP0	P1_2 定時器輸入0.
P1_3_GPIO	P1_3 GPIO模式
P1_3_TRIG_OUT1	P1_3 觸發輸出1.
P1_3_LPSPI0_PCS0	P1_3 LPSPI0片選0.
P1_3_LPI2C0_SCLS	P1_3 LPI2C0串列時脈同步
P1_3_CT1_MAT1	P1_3 定時器1匹配輸出1.
P1_3_CT_INP1	P1_3 定時器輸入1.
P1_4_GPIO	P1_4 GPIO模式
P1_4_FREQME_CLK_IN0	P1_4 頻率測量時脈輸入0.
P1_4_LPSPI0_PCS3	P1_4 LPSPI0片選3.
P1_4_LPUART2_RXD	P1_4 LPUART2接收資料
P1_4_CT1_MAT2	P1_4 定時器1匹配輸出2.
P1_5_GPIO	P1_5 GPIO模式
P1_5_FREQME_CLK_IN1	P1_5 頻率測量時脈輸入1.
P1_5_LPSPI0_PCS2	P1_5 LPSPI0片選2.
P1_5_LPUART2_TXD	P1_5 LPUART2傳送資料
P1_5_CT1_MAT3	P1_5 定時器1匹配輸出3.
P1_6_GPIO	P1_6 GPIO模式
P1_6_TRIG_IN2	P1_6 觸發輸入2.
P1_6_LPSPI0_PCS1	P1_6 LPSPI0片選1.
P1_6_LPUART2_RTS_B	P1_6 LPUART2請求發送反向
P1_6_CT_INP6	P1_6 定時器輸入6.
P1_7_GPIO	P1_7 GPIO模式
P1_7_TRIG_OUT2	P1_7 觸發輸出2.
P1_7_LPUART2_CTS_B	P1_7 LPUART2清除發送反向
P1_7_CT_INP7	P1_7 定時器輸入7.
P1_8_GPIO	P1_8 GPIO模式
P1_8_LPUART1_RXD	P1_8 LPUART1接收資料
P1_8_LPI2C0_SDA	P1_8 LPI2C0串列資料線
P1_8_CT_INP8	P1_8 定時器輸入8.
P1_8_CT0_MAT2	P1_8 定時器0匹配輸出2.
P1_8_I3C0_SDA	P1_8 I3C0串列資料線
P1_9_GPIO	P1_9 GPIO模式
P1_9_LPUART1_TXD	P1_9 LPUART1傳送資料
P1_9_LPI2C0_SCL	P1_9 LPI2C0串列時脈線
P1_9_CT_INP9	P1_9 定時器輸入9.
P1_9_CT0_MAT3	P1_9 定時器0匹配輸出3.
P1_9_I3C0_SCL	P1_9 I3C0串列時脈線
P1_10_GPIO	P1_10 GPIO模式
P1_10_LPUART1_RTS_B	P1_10 LPUART1請求發送反向
P1_10_LPI2C0_SDAS	P1_10 LPI2C0串列資料同步
P1_10_CT2_MAT0	P1_10 定時器2匹配輸出0.
P1_11_GPIO	P1_11 GPIO模式
P1_11_TRIG_OUT2	P1_11 觸發輸出2.
P1_11_LPUART1_CTS_B	P1_11 LPUART1清除發送反向
P1_11_LPI2C0_SCLS	P1_11 LPI2C0串列時脈同步
P1_11_CT2_MAT1	P1_11 定時器2匹配輸出1.
P1_11_I3C0_PUR	P1_11 I3C0上拉電阻
P1_12_GPIO	P1_12 GPIO模式
P1_12_LPUART2_RXD	P1_12 LPUART2接收資料
P1_12_CT2_MAT2	P1_12 定時器2匹配輸出2.
P1_13_GPIO	P1_13 GPIO模式
P1_13_TRIG_IN3	P1_13 觸發輸入3.
P1_13_LPUART2_TXD	P1_13 LPUART2傳送資料
P1_13_CT2_MAT3	P1_13 定時器2匹配輸出3.
P1_29_GPIO	P1_29 GPIO模式
P1_29_RESET_B	P1_29 重置輸入
P1_29_SPC_LPREQ	P1_29 系統低功耗請求
P1_30_GPIO	P1_30 GPIO模式
P1_30_TRIG_OUT3	P1_30 觸發輸出3.
P1_30_LPI2C0_SDA	P1_30 LPI2C0串列資料線
P1_30_CT_INP16	P1_30 定時器輸入16.
P1_30_I3C0_SDA	P1_30 I3C0串列資料線
P1_31_GPIO	P1_31 GPIO模式
P1_31_TRIG_IN4	P1_31 觸發輸入4.
P1_31_LPI2C0_SCL	P1_31 LPI2C0串列時脈線
P1_31_CT_INP17	P1_31 定時器輸入17.
P1_31_I3C0_SCL	P1_31 I3C0串列時脈線 P1_31 I3C0串列時脈線
P2_0_GPIO	P2_0 GPIO模式
P2_0_TRIG_IN6	P2_0 觸發輸入6.
P2_0_LPUART0_RXD	P2_0 LPUART0接收資料
P2_0_CT_INP16	P2_0 定時器輸入16.
P2_0_CT2_MAT0	P2_0 定時器2匹配輸出0.
P2_1_GPIO	P2_1 GPIO模式
P2_1_TRIG_IN7	P2_1 觸發輸入7.
P2_1_LPUART0_TXD	P2_1 LPUART0傳送資料
P2_1_CT_INP17	P2_1 定時器輸入17.
P2_1_CT2_MAT1	P2_1 定時器2匹配輸出1.
P2_2_GPIO	P2_2 GPIO模式
P2_2_TRIG_IN6	P2_2 觸發輸入6.
P2_2_LPUART0_RTS_B	P2_2 LPUART0請求發送反向
P2_2_LPUART2_TXD	P2_2 LPUART2傳送資料
P2_2_CT_INP12	P2_2 定時器輸入12.
P2_2_CT2_MAT2	P2_2 定時器2匹配輸出2.
P2_3_GPIO	P2_3 GPIO模式
P2_3_TRIG_IN7	P2_3 觸發輸入7.
P2_3_LPUART0_CTS_B	P2_3 LPUART0清除發送反向
P2_3_LPUART2_RXD	P2_3 LPUART2接收資料
P2_3_CT_INP13	P2_3 定時器輸入13.
P2_3_CT2_MAT3	P2_3 定時器2匹配輸出3.
P2_6_GPIO	P2_6 GPIO模式
P2_6_TRIG_OUT4	P2_6 觸發輸出4.
P2_6_LPSPI1_PCS1	P2_6 LPSPI1片選1.
P2_6_CT_INP18	P2_6 定時器輸入18.
P2_6_CT1_MAT2	P2_6 定時器1匹配輸出2.
P2_7_GPIO	P2_7 GPIO模式
P2_7_TRIG_IN5	P2_7 觸發輸入5.
P2_7_CT_INP19	P2_7 定時器輸入19.
P2_7_CT1_MAT3	P2_7 定時器1匹配輸出3.
P2_12_GPIO	P2_12 GPIO模式
P2_12_USB0_VBUS_DET	P2_12 USB VBUS檢測
P2_12_LPSPI1_SCK	P2_12 LPSPI1串列時脈
P2_12_LPUART1_RXD	P2_12 LPUART1接收資料
P2_12_CT0_MAT0	P2_12 定時器0匹配輸出0.
P2_13_GPIO	P2_13 GPIO模式
P2_13_TRIG_IN8	P2_13 觸發輸入8.
P2_13_LPSPI1_SDO	P2_13 LPSPI1串列資料輸出
P2_13_LPUART1_TXD	P2_13 LPUART1傳送資料
P2_13_CT0_MAT1	P2_13 定時器0匹配輸出1.
P2_16_GPIO	P2_16 GPIO模式
P2_16_LPSPI1_SDI	P2_16 LPSPI1串列資料輸入
P2_16_LPUART1_RTS_B	P2_16 LPUART1請求發送反向
P2_16_CT0_MAT2	P2_16 定時器0匹配輸出2. P2_16 定時器0匹配輸出2
P3_0_GPIO	P3_0 GPIO模式
P3_0_TRIG_IN0	P3_0 觸發輸入0.
P3_0_CT_INP16	P3_0 定時器輸入16.
P3_0_PWM0_A0	P3_0 PWM通道A0.
P3_1_GPIO	P3_1 GPIO模式
P3_1_TRIG_IN1	P3_1 觸發輸入1.
P3_1_CT_INP17	P3_1 定時器輸入17.
P3_1_PWM0_B0	P3_1 PWM通道B0.
P3_1_FREQME_CLK_OUT0	P3_1 頻率測量時脈輸出0.
P3_6_GPIO	P3_6 GPIO模式
P3_6_CLKOUT	P3_6 時脈輸出
P3_6_LPSPI1_PCS3	P3_6 LPSPI1片選3.
P3_6_PWM0_A0	P3_6 PWM通道A0.
P3_6_FREQME_CLK_OUT1	P3_6 頻率測量時脈輸出1.
P3_7_GPIO	P3_7 GPIO模式
P3_7_TRIG_IN2	P3_7 觸發輸入2.
P3_7_LPSPI1_PCS2	P3_7 LPSPI1片選2.
P3_7_PWM0_B0	P3_7 PWM通道B0.
P3_8_GPIO	P3_8 GPIO模式
P3_8_TRIG_IN3	P3_8 觸發輸入3.
P3_8_LPSPI1_SDO	P3_8 LPSPI1串列資料輸出
P3_8_LPUART1_RXD	P3_8 LPUART1接收資料
P3_8_CT_INP4	P3_8 定時器輸入4.
P3_8_PWM0_A1	P3_8 PWM通道A1.
P3_8_CLKOUT	P3_8 時脈輸出
P3_9_GPIO	P3_9 GPIO模式
P3_9_TRIG_IN4	P3_9 觸發輸入4. P3_9 觸發輸入4
P3_9_LPSPI1_SDI	P3_9 LPSPI1串列資料輸入
P3_9_LPUART1_TXD	P3_9 LPUART1傳送資料
P3_9_CT_INP5	P3_9 定時器輸入5.
P3_9_PWM0_B1	P3_9 PWM通道B1.
P3_10_GPIO	P3_10 GPIO模式
P3_10_TRIG_IN5	P3_10 觸發輸入5.
P3_10_LPSPI1_SCK	P3_10 LPSPI1串列時脈
P3_10_LPUART1_RTS_B	P3_10 LPUART1請求發送反向
P3_10_CT1_MAT0	P3_10 定時器1匹配輸出0.
P3_10_PWM0_A2	P3_10 PWM通道A2.
P3_11_GPIO	P3_11 GPIO模式
P3_11_TRIG_IN6	P3_11 觸發輸入6.
P3_11_LPSPI1_PCS0	P3_11 LPSPI1片選0.
P3_11_LPUART1_CTS_B	P3_11 LPUART1清除發送反向
P3_11_CT1_MAT1	P3_11 定時器1匹配輸出1.
P3_11_PWM0_B2	P3_11 PWM通道B2.
P3_12_GPIO	P3_12 GPIO模式
P3_12_LPUART2_RTS_B	P3_12 LPUART2請求發送反向
P3_12_CT1_MAT2	P3_12 定時器1匹配輸出2.
P3_12_PWM0_X0	P3_12 PWM故障輸入0.
P3_13_GPIO	P3_13 GPIO模式
P3_13_LPUART2_CTS_B	P3_13 LPUART2清除發送反向
P3_13_CT1_MAT3	P3_13 定時器1匹配輸出3.
P3_13_PWM0_X1	P3_13 PWM故障輸入1.
P3_14_GPIO	P3_14 GPIO模式
P3_14_LPUART2_RXD	P3_14 LPUART2接收資料
P3_14_CT_INP6	P3_14 定時器輸入6.
P3_14_PWM0_X2	P3_14 PWM故障輸入2.
P3_15_GPIO	P3_15 GPIO模式
P3_15_LPUART2_TXD	P3_15 LPUART2傳送資料
P3_15_CT_INP7	P3_15 定時器輸入7.
P3_27_GPIO	P3_27 GPIO模式
P3_27_TRIG_OUT7	P3_27 觸發輸出7.
P3_27_LPI2C0_SCL	P3_27 LPI2C0串列時脈線
P3_27_CT_INP13	P3_27 定時器輸入13.
P3_28_GPIO	P3_28 GPIO模式
P3_28_TRIG_IN11	P3_28 觸發輸入11.
P3_28_LPI2C0_SDA	P3_28 LPI2C0串列資料線
P3_28_CT_INP12	P3_28 定時器輸入12.
P3_29_GPIO	P3_29 GPIO模式
P3_29_ISPMODE_N	P3_29 ISP模式選擇反向
P3_29_CT_INP3	P3_29 定時器輸入3.
P3_30_GPIO	P3_30 GPIO模式
P3_30_TRIG_OUT6	P3_30 觸發輸出6.
P3_30_CT0_MAT2	P3_30 定時器0匹配輸出2.
P3_31_GPIO	P3_31 GPIO模式
P3_31_TRIG_IN10	P3_31 觸發輸入10.
P3_31_CT0_MAT3	P3_31 定時器0匹配輸出3.
NONE	無效的多工器設定

◆ MuxPortPin

enum struct mcxa153::core::mux::MuxPortPin : uint16

strong

MCXA153 引腳埠位編碼列舉

定義 MCXA153 微控制器的引腳標識符，用於引腳多功能複用配置。每個值編碼了埠號和引腳號資訊：

位元[15:8]：保留
位元[9:8]：GPIO埠號 (0-3)
位元[4:0]：引腳號 (0-31)

註: 使用 genMuxPortPin(port, pin) 函數產生編碼值

列舉值
P0_0	GPIO埠0引腳0.
P0_1	GPIO埠0引腳1.
P0_2	GPIO埠0引腳2.
P0_3	GPIO埠0引腳3.
P0_6	GPIO埠0引腳6.
P0_16	GPIO埠0引腳16.
P0_17	GPIO埠0引腳17.
P1_0	GPIO埠1引腳0.
P1_1	GPIO埠1引腳1.
P1_2	GPIO埠1引腳2.
P1_3	GPIO埠1引腳3.
P1_4	GPIO埠1引腳4.
P1_5	GPIO埠1引腳5.
P1_6	GPIO埠1引腳6.
P1_7	GPIO埠1引腳7.
P1_8	GPIO埠1引腳8.
P1_9	GPIO埠1引腳9.
P1_10	GPIO埠1引腳10.
P1_11	GPIO埠1引腳11.
P1_12	GPIO埠1引腳12.
P1_13	GPIO埠1引腳13.
P1_29	GPIO埠1引腳29.
P1_30	GPIO埠1引腳30.
P1_31	GPIO埠1引腳31.
P2_0	GPIO埠2引腳0.
P2_1	GPIO埠2引腳1.
P2_2	GPIO埠2引腳2.
P2_3	GPIO埠2引腳3.
P2_4	GPIO埠2引腳4.
P2_5	GPIO埠2引腳5.
P2_6	GPIO埠2引腳6.
P2_7	GPIO埠2引腳7.
P2_12	GPIO埠2引腳12.
P2_13	GPIO埠2引腳13.
P2_16	GPIO埠2引腳16.
P3_0	GPIO埠3引腳0.
P3_1	GPIO埠3引腳1.
P3_6	GPIO埠3引腳6.
P3_7	GPIO埠3引腳7.
P3_8	GPIO埠3引腳8.
P3_9	GPIO埠3引腳9.
P3_10	GPIO埠3引腳10.
P3_11	GPIO埠3引腳11.
P3_12	GPIO埠3引腳12.
P3_13	GPIO埠3引腳13.
P3_14	GPIO埠3引腳14.
P3_15	GPIO埠3引腳15. GPIO埠3引腳15
P3_27	GPIO埠3引腳27.
P3_28	GPIO埠3引腳28.
P3_29	GPIO埠3引腳29.
P3_30	GPIO埠3引腳30.
P3_31	GPIO埠3引腳31.

函式說明文件

◆ operator+() [1/2]

uint32 mcxa153::core::mux::operator+ ( Mux e )

constexpr

Mux 枚舉轉換為 uint32.

將 Mux 枚舉值轉換為 uint32 以便於處理和存儲。

參數

e Mux 枚舉值

傳回值: 對應的 uint32 值

◆ operator+() [2/2]

uint16 mcxa153::core::mux::operator+ ( MuxPortPin e )

constexpr

MuxPortPin 枚舉轉換為 uint16.

將 MuxPortPin 枚舉值轉換為 uint16 以便於處理和存儲。