mcxa153::chip::lpuart 命名空間(Namespace)參考文件

複合項目
class	LPUART
	MCXA153 低功耗通用非同步收發器 (Low Power Universal Asynchronous Receiver/Transmitter) 控制器靜態工具類別 更多...
struct	Register
	LPUART 週邊暫存器存取層 更多...

列舉型態
enum struct	Mask : unsigned int {   VERID_FEATURE = 0xFFFFU , VERID_MINOR = 0xFF0000U , VERID_MAJOR = 0xFF000000U , PARAM_TXFIFO = 0xFFU ,   PARAM_RXFIFO = 0xFF00U , GLOBAL_RST = 0x2U , PINCFG_TRGSEL = 0x3U , BAUD_SBR = 0x1FFFU ,   BAUD_SBNS = 0x2000U , BAUD_RXEDGIE = 0x4000U , BAUD_LBKDIE = 0x8000U , BAUD_RESYNCDIS = 0x10000U ,   BAUD_BOTHEDGE = 0x20000U , BAUD_MATCFG = 0xC0000U , BAUD_RIDMAE = 0x100000U , BAUD_RDMAE = 0x200000U ,   BAUD_TDMAE = 0x800000U , BAUD_OSR = 0x1F000000U , BAUD_M10 = 0x20000000U , BAUD_MAEN2 = 0x40000000U ,   BAUD_MAEN1 = 0x80000000U , STAT_LBKFE = 0x1U , STAT_AME = 0x2U , STAT_MA2F = 0x4000U ,   STAT_MA1F = 0x8000U , STAT_PF = 0x10000U , STAT_FE = 0x20000U , STAT_NF = 0x40000U ,   STAT_OR = 0x80000U , STAT_IDLE = 0x100000U , STAT_RDRF = 0x200000U , STAT_TC = 0x400000U ,   STAT_TDRE = 0x800000U , STAT_RAF = 0x1000000U , STAT_LBKDE = 0x2000000U , STAT_BRK13 = 0x4000000U ,   STAT_RWUID = 0x8000000U , STAT_RXINV = 0x10000000U , STAT_MSBF = 0x20000000U , STAT_RXEDGIF = 0x40000000U ,   STAT_LBKDIF = 0x80000000U , CTRL_PT = 0x1U , CTRL_PE = 0x2U , CTRL_ILT = 0x4U ,   CTRL_WAKE = 0x8U , CTRL_M = 0x10U , CTRL_RSRC = 0x20U , CTRL_DOZEEN = 0x40U ,   CTRL_LOOPS = 0x80U , CTRL_IDLECFG = 0x700U , CTRL_M7 = 0x800U , CTRL_MA2IE = 0x4000U ,   CTRL_MA1IE = 0x8000U , CTRL_SBK = 0x10000U , CTRL_RWU = 0x20000U , CTRL_RE = 0x40000U ,   CTRL_TE = 0x80000U , CTRL_ILIE = 0x100000U , CTRL_RIE = 0x200000U , CTRL_TCIE = 0x400000U ,   CTRL_TIE = 0x800000U , CTRL_PEIE = 0x1000000U , CTRL_FEIE = 0x2000000U , CTRL_NEIE = 0x4000000U ,   CTRL_ORIE = 0x8000000U , CTRL_TXINV = 0x10000000U , CTRL_TXDIR = 0x20000000U , CTRL_R9T8 = 0x40000000U ,   CTRL_R8T9 = 0x80000000U , DATA_R0T0 = 0x1U , DATA_R1T1 = 0x2U , DATA_R2T2 = 0x4U ,   DATA_R3T3 = 0x8U , DATA_R4T4 = 0x10U , DATA_R5T5 = 0x20U , DATA_R6T6 = 0x40U ,   DATA_R7T7 = 0x80U , DATA_R8T8 = 0x100U , DATA_R9T9 = 0x200U , DATA_LINBRK = 0x400U ,   DATA_IDLINE = 0x800U , DATA_RXEMPT = 0x1000U , DATA_FRETSC = 0x2000U , DATA_PARITYE = 0x4000U ,   DATA_NOISY = 0x8000U , MATCH_MA1 = 0x3FFU , MATCH_MA2 = 0x3FF0000U , MODIR_TXCTSE = 0x1U ,   MODIR_TXRTSE = 0x2U , MODIR_TXRTSPOL = 0x4U , MODIR_RXRTSE = 0x8U , MODIR_TXCTSC = 0x10U ,   MODIR_TXCTSSRC = 0x20U , MODIR_RTSWATER = 0x300U , MODIR_TNP = 0x30000U , MODIR_IREN = 0x40000U ,   FIFO_RXFIFOSIZE = 0x7U , FIFO_RXFE = 0x8U , FIFO_TXFIFOSIZE = 0x70U , FIFO_TXFE = 0x80U ,   FIFO_RXUFE = 0x100U , FIFO_TXOFE = 0x200U , FIFO_RXIDEN = 0x1C00U , FIFO_RXFLUSH = 0x4000U ,   FIFO_TXFLUSH = 0x8000U , FIFO_RXUF = 0x10000U , FIFO_TXOF = 0x20000U , FIFO_RXEMPT = 0x400000U ,   FIFO_TXEMPT = 0x800000U , WATER_TXWATER = 0x3U , WATER_TXCOUNT = 0x700U , WATER_RXWATER = 0x30000U ,   WATER_RXCOUNT = 0x7000000U , DATARO_DATA = 0xFFFFU }
	LPUART 暫存器位元遮罩枚舉 更多...
enum struct	Shift : unsigned int {   VERID_FEATURE = 0U , VERID_MINOR = 16U , VERID_MAJOR = 24U , PARAM_TXFIFO = 0U ,   PARAM_RXFIFO = 8U , GLOBAL_RST = 1U , PINCFG_TRGSEL = 0U , BAUD_SBR = 0U ,   BAUD_SBNS = 13U , BAUD_RXEDGIE = 14U , BAUD_LBKDIE = 15U , BAUD_RESYNCDIS = 16U ,   BAUD_BOTHEDGE = 17U , BAUD_MATCFG = 18U , BAUD_RIDMAE = 20U , BAUD_RDMAE = 21U ,   BAUD_TDMAE = 23U , BAUD_OSR = 24U , BAUD_M10 = 29U , BAUD_MAEN2 = 30U ,   BAUD_MAEN1 = 31U , STAT_LBKFE = 0U , STAT_AME = 1U , STAT_MA2F = 14U ,   STAT_MA1F = 15U , STAT_PF = 16U , STAT_FE = 17U , STAT_NF = 18U ,   STAT_OR = 19U , STAT_IDLE = 20U , STAT_RDRF = 21U , STAT_TC = 22U ,   STAT_TDRE = 23U , STAT_RAF = 24U , STAT_LBKDE = 25U , STAT_BRK13 = 26U ,   STAT_RWUID = 27U , STAT_RXINV = 28U , STAT_MSBF = 29U , STAT_RXEDGIF = 30U ,   STAT_LBKDIF = 31U , CTRL_PT = 0U , CTRL_PE = 1U , CTRL_ILT = 2U ,   CTRL_WAKE = 3U , CTRL_M = 4U , CTRL_RSRC = 5U , CTRL_DOZEEN = 6U ,   CTRL_LOOPS = 7U , CTRL_IDLECFG = 8U , CTRL_M7 = 11U , CTRL_MA2IE = 14U ,   CTRL_MA1IE = 15U , CTRL_SBK = 16U , CTRL_RWU = 17U , CTRL_RE = 18U ,   CTRL_TE = 19U , CTRL_ILIE = 20U , CTRL_RIE = 21U , CTRL_TCIE = 22U ,   CTRL_TIE = 23U , CTRL_PEIE = 24U , CTRL_FEIE = 25U , CTRL_NEIE = 26U ,   CTRL_ORIE = 27U , CTRL_TXINV = 28U , CTRL_TXDIR = 29U , CTRL_R9T8 = 30U ,   CTRL_R8T9 = 31U , DATA_R0T0 = 0U , DATA_R1T1 = 1U , DATA_R2T2 = 2U ,   DATA_R3T3 = 3U , DATA_R4T4 = 4U , DATA_R5T5 = 5U , DATA_R6T6 = 6U ,   DATA_R7T7 = 7U , DATA_R8T8 = 8U , DATA_R9T9 = 9U , DATA_LINBRK = 10U ,   DATA_IDLINE = 11U , DATA_RXEMPT = 12U , DATA_FRETSC = 13U , DATA_PARITYE = 14U ,   DATA_NOISY = 15U , MATCH_MA1 = 0U , MATCH_MA2 = 16U , MODIR_TXCTSE = 0U ,   MODIR_TXRTSE = 1U , MODIR_TXRTSPOL = 2U , MODIR_RXRTSE = 3U , MODIR_TXCTSC = 4U ,   MODIR_TXCTSSRC = 5U , MODIR_RTSWATER = 8U , MODIR_TNP = 16U , MODIR_IREN = 18U ,   FIFO_RXFIFOSIZE = 0U , FIFO_RXFE = 3U , FIFO_TXFIFOSIZE = 4U , FIFO_TXFE = 7U ,   FIFO_RXUFE = 8U , FIFO_TXOFE = 9U , FIFO_RXIDEN = 10U , FIFO_RXFLUSH = 14U ,   FIFO_TXFLUSH = 15U , FIFO_RXUF = 16U , FIFO_TXOF = 17U , FIFO_RXEMPT = 22U ,   FIFO_TXEMPT = 23U , WATER_TXWATER = 0U , WATER_TXCOUNT = 8U , WATER_RXWATER = 16U ,   WATER_RXCOUNT = 24U , DATARO_DATA = 0U }
	LPUART 暫存器位元位移枚舉 更多...

函式
constexpr unsigned int	operator+ (Mask e)
constexpr unsigned int	operator+ (Shift e)
	Shift Operator Overloading - Convert Enum To Unsigned Integer.

變數
Register *const	LPUART0
Register *const	LPUART1
Register *const	LPUART2
Register *const	LPUART [3] = {LPUART0, LPUART1, LPUART2}

詳細描述

Copyright (c) 2020 ZxyKira All rights reserved.

SPDX-License-Identifier: MIT

列舉型態說明文件

Mask

enum struct mcxa153::chip::lpuart::Mask : unsigned int

strong

LPUART 暫存器位元遮罩枚舉

此枚舉定義了 LPUART (Low Power Universal Asynchronous Receiver-Transmitter) 週邊各暫存器的位元欄位遮罩值， 用於位元操作、欄位存取和暫存器配置。每個遮罩對應特定暫存器的特定位元欄位。

註

使用 unsigned int 作為底層型別以匹配 32 位元暫存器

遮罩值可用於位元運算，如 AND、OR、XOR 等操作

列舉值
VERID_FEATURE	VERID - FEATURE. Version ID - Feature Identification Number [0b0000000000000001]Standard feature set [0b0000000000000011]Standard feature set with MODEM and IrDA support
VERID_MINOR	VERID - MINOR. Version ID - Minor Version Number
VERID_MAJOR	VERID - MAJOR. Version ID - Major Version Number
PARAM_TXFIFO	PARAM - TXFIFO. Parameter - Transmit FIFO Size
PARAM_RXFIFO	PARAM - RXFIFO. Parameter - Receive FIFO Size
GLOBAL_RST	GLOBAL - RST. Global - Software Reset [0b0]Not reset [0b1]Reset
PINCFG_TRGSEL	PINCFG - TRGSEL. Pin Configuration - Trigger Select [0b00]Input trigger disabled [0b01]Input trigger used instead of the RXD pin input [0b10]Input trigger used instead of the CTS_B pin input [0b11]Input trigger used to modulate the TXD pin output, which (after TXINV configuration) is internally ANDed with the input trigger
BAUD_SBR	BAUD - SBR. Baud Rate - Baud Rate Modulo Divisor
BAUD_SBNS	BAUD - SBNS. Baud Rate - Stop Bit Number Select [0b0]One stop bit [0b1]Two stop bits
BAUD_RXEDGIE	BAUD - RXEDGIE. Baud Rate - RX Input Active Edge Interrupt Enable [0b0]Disable [0b1]Enable
BAUD_LBKDIE	BAUD - LBKDIE. Baud Rate - LIN Break Detect Interrupt Enable [0b0]Disable [0b1]Enable
BAUD_RESYNCDIS	BAUD - RESYNCDIS. Baud Rate - Resynchronization Disable [0b0]Enable [0b1]Disable
BAUD_BOTHEDGE	BAUD - BOTHEDGE. Baud Rate - Both Edge Sampling [0b0]Rising edge [0b1]Both rising and falling edges
BAUD_MATCFG	BAUD - MATCFG. Baud Rate - Match Configuration [0b00]Address match wake-up [0b01]Idle match wake-up [0b10]Match on and match off [0b11]Enables RWU on data match and match on or off for the transmitter CTS input
BAUD_RIDMAE	BAUD - RIDMAE. Baud Rate - Receiver Idle DMA Enable [0b0]Disable [0b1]Enable
BAUD_RDMAE	BAUD - RDMAE. Baud Rate - Receiver Full DMA Enable [0b0]Disable [0b1]Enable
BAUD_TDMAE	BAUD - TDMAE. Baud Rate - Transmitter DMA Enable [0b0]Disable [0b1]Enable
BAUD_OSR	BAUD - OSR. Baud Rate - Oversampling Ratio [0b00000]Results in an OSR of 16 [0b00001]Reserved [0b00010]Reserved [0b00011]Results in an OSR of 4 (requires BAUD[BOTHEDGE] to be 1) [0b00100]Results in an OSR of 5 (requires BAUD[BOTHEDGE] to be 1) [0b00101]Results in an OSR of 6 (requires BAUD[BOTHEDGE] to be 1) [0b00110]Results in an OSR of 7 (requires BAUD[BOTHEDGE] to be 1) [0b00111]Results in an OSR of 8 [0b01000]Results in an OSR of 9 [0b01001]Results in an OSR of 10 [0b01010]Results in an OSR of 11 [0b01011]Results in an OSR of 12 [0b01100]Results in an OSR of 13 [0b01101]Results in an OSR of 14 [0b01110]Results in an OSR of 15 [0b01111]Results in an OSR of 16 [0b10000]Results in an OSR of 17 [0b10001]Results in an OSR of 18 [0b10010]Results in an OSR of 19 [0b10011]Results in an OSR of 20 [0b10100]Results in an OSR of 21 [0b10101]Results in an OSR of 22 [0b10110]Results in an OSR of 23 [0b10111]Results in an OSR of 24 [0b11000]Results in an OSR of 25 [0b11001]Results in an OSR of 26 [0b11010]Results in an OSR of 27 [0b11011]Results in an OSR of 28 [0b11100]Results in an OSR of 29 [0b11101]Results in an OSR of 30 [0b11110]Results in an OSR of 31 [0b11111]Results in an OSR of 32
BAUD_M10	BAUD - M10. Baud Rate - 10-Bit Mode Select [0b0]Receiver and transmitter use 7-bit to 9-bit data characters [0b1]Receiver and transmitter use 10-bit data characters
BAUD_MAEN2	BAUD - MAEN2. Baud Rate - Match Address Mode Enable 2 [0b0]Disable [0b1]Enable
BAUD_MAEN1	BAUD - MAEN1. Baud Rate - Match Address Mode Enable 1 [0b0]Disable [0b1]Enable
STAT_LBKFE	STAT - LBKFE. Status - LIN Break Flag Enable [0b0]Disable [0b1]Enable
STAT_AME	STAT - AME. Status - Address Mark Enable [0b0]Disable [0b1]Enable
STAT_MA2F	STAT - MA2F. Status - Match 2 Flag [0b0]Not equal to MA2 [0b1]Equal to MA2 [0b0]No effect [0b1]Clear the flag
STAT_MA1F	STAT - MA1F. Status - Match 1 Flag [0b0]Not equal to MA1 [0b1]Equal to MA1 [0b0]No effect [0b1]Clear the flag
STAT_PF	STAT - PF. Status - Parity Error Flag [0b0]No parity error detected [0b1]Parity error detected [0b0]No effect [0b1]Clear the flag
STAT_FE	STAT - FE. Status - Framing Error Flag [0b0]No framing error detected (this does not guarantee that the framing is correct) [0b1]Framing error detected [0b0]No effect [0b1]Clear the flag
STAT_NF	STAT - NF. Status - Noise Flag [0b0]No noise detected [0b1]Noise detected [0b0]No effect [0b1]Clear the flag
STAT_OR	STAT - OR. Status - Receiver Overrun Flag [0b0]No overrun [0b1]Receive overrun (new LPUART data is lost) [0b0]No effect [0b1]Clear the flag
STAT_IDLE	STAT - IDLE. Status - Idle Line Flag [0b0]Idle line detected [0b1]Idle line not detected [0b0]No effect [0b1]Clear the flag
STAT_RDRF	STAT - RDRF. Status - Receive Data Register Full Flag [0b0]Equal to or less than watermark [0b1]Greater than watermark
STAT_TC	STAT - TC. Status - Transmission Complete Flag [0b0]Transmitter active [0b1]Transmitter idle
STAT_TDRE	STAT - TDRE. Status - Transmit Data Register Empty Flag [0b0]Greater than watermark [0b1]Equal to or less than watermark
STAT_RAF	STAT - RAF - Receiver Active Flag. [0b0]Idle, waiting for a start bit [0b1]Receiver active (RXD pin input not idle)
STAT_LBKDE	STAT - LBKDE. Status - LIN Break Detection Enable [0b0]Disable [0b1]Enable
STAT_BRK13	STAT - BRK13. Status - Break Character Generation Length [0b0]9 to 13 bit times [0b1]12 to 15 bit times
STAT_RWUID	STAT - RWUID. Status - Receive Wake Up Idle Detect [0b0]STAT[IDLE] does not become 1 [0b1]STAT[IDLE] becomes 1
STAT_RXINV	STAT - RXINV. Status - Receive Data Inversion [0b0]Inverted [0b1]Not inverted
STAT_MSBF	STAT - MSBF. Status - MSB First [0b0]LSB [0b1]MSB
STAT_RXEDGIF	STAT - RXEDGIF. Status - RXD Pin Active Edge Interrupt Flag [0b0]Not occurred [0b1]Occurred [0b0]No effect [0b1]Clear the flag
STAT_LBKDIF	STAT - LBKDIF. Status - LIN Break Detect Interrupt Flag [0b0]Not detected [0b1]Detected [0b0]No effect [0b1]Clear the flag
CTRL_PT	CTRL - PT. Control - Parity Type [0b0]Even parity [0b1]Odd parity
CTRL_PE	CTRL - PE. Control - Parity Enable [0b0]Disable [0b1]Enable
CTRL_ILT	CTRL - ILT. Control - Idle Line Type Select [0b0]After the start bit [0b1]After the stop bit
CTRL_WAKE	CTRL - WAKE. Control - Receiver Wake-Up Method Select [0b0]Idle [0b1]Mark
CTRL_M	CTRL - M. Control - 9-Bit Or 8-Bit Mode Select [0b0]8-bit [0b1]9-bit
CTRL_RSRC	CTRL - RSRC. Control - Receiver Source Select [0b0]Internal Loopback mode [0b1]Single-wire mode
CTRL_DOZEEN	CTRL - DOZEEN. Control - Doze Mode [0b0]Enable [0b1]Disable
CTRL_LOOPS	CTRL - LOOPS. Control - Loop Mode Select [0b0]Normal operation: RXD and TXD use separate pins [0b1]Loop mode or Single-Wire mode
CTRL_IDLECFG	CTRL - IDLECFG. Control - Idle Configuration [0b000]1 [0b001]2 [0b010]4 [0b011]8 [0b100]16 [0b101]32 [0b110]64 [0b111]128
CTRL_M7	CTRL - M7. Control - 7-Bit Mode Select [0b0]8-bit to 10-bit [0b1]7-bit
CTRL_MA2IE	CTRL - MA2IE. Control - Match 2 (MA2F) Interrupt Enable [0b0]Disable [0b1]Enable
CTRL_MA1IE	CTRL - MA1IE. Control - Match 1 (MA1F) Interrupt Enable [0b0]Disable [0b1]Enable
CTRL_SBK	CTRL - SBK. Control - Send Break [0b0]Normal transmitter operation [0b1]Queue break character(s) to be sent
CTRL_RWU	CTRL - RWU. Control - Receiver Wake-Up Control [0b0]Normal receiver operation [0b1]LPUART receiver in standby, waiting for a wake-up condition
CTRL_RE	CTRL - RE. Control - Receiver Enable [0b0]Disable [0b1]Enable
CTRL_TE	CTRL - TE. Control - Transmitter Enable [0b0]Disable [0b1]Enable
CTRL_ILIE	CTRL - ILIE. Control - Idle Line Interrupt Enable [0b0]Disable [0b1]Enable
CTRL_RIE	CTRL - RIE. Control - Receiver Interrupt Enable [0b0]Disable [0b1]Enable
CTRL_TCIE	CTRL - TCIE. Control - Transmission Complete Interrupt Enable [0b0]Disable [0b1]Enable
CTRL_TIE	CTRL - TIE. Control - Transmit Interrupt Enable [0b0]Disable [0b1]Enable
CTRL_PEIE	CTRL - PEIE. Control - Parity Error Interrupt Enable [0b0]Disable [0b1]Enable
CTRL_FEIE	CTRL - FEIE. Control - Framing Error Interrupt Enable [0b0]Disable [0b1]Enable
CTRL_NEIE	CTRL - NEIE. Control - Noise Error Interrupt Enable [0b0]Disable [0b1]Enable
CTRL_ORIE	CTRL - ORIE. Control - Overrun Interrupt Enable [0b0]Disable [0b1]Enable
CTRL_TXINV	CTRL - TXINV. Control - Transmit Data Inversion [0b0]Not inverted [0b1]Inverted
CTRL_TXDIR	CTRL - TXDIR. Control - TXD Pin Direction in Single-Wire Mode [0b0]Input [0b1]Output
CTRL_R9T8	CTRL - R9T8. Control - Receive Bit 9 Transmit Bit 8
CTRL_R8T9	CTRL - R8T9. Control - Receive Bit 8 Transmit Bit 9
DATA_R0T0	DATA - R0T0. Data - Read receive FIFO bit 0 or write transmit FIFO bit 0
DATA_R1T1	DATA - R1T1. Data - Read receive FIFO bit 1 or write transmit FIFO bit 1
DATA_R2T2	DATA - R2T2. Data - Read receive FIFO bit 2 or write transmit FIFO bit 2
DATA_R3T3	DATA - R3T3. Data - Read receive FIFO bit 3 or write transmit FIFO bit 3
DATA_R4T4	DATA - R4T4. Data - Read receive FIFO bit 4 or write transmit FIFO bit 4
DATA_R5T5	DATA - R5T5. Data - Read receive FIFO bit 5 or write transmit FIFO bit 5
DATA_R6T6	DATA - R6T6. Data - Read receive FIFO bit 6 or write transmit FIFO bit 6
DATA_R7T7	DATA - R7T7. Data - Read receive FIFO bit 7 or write transmit FIFO bit 7
DATA_R8T8	DATA - R8T8. Data - Read receive FIFO bit 8 or write transmit FIFO bit 8
DATA_R9T9	DATA - R9T9. Data - Read receive FIFO bit 9 or write transmit FIFO bit 9
DATA_LINBRK	DATA - LINBRK. Data - LIN Break [0b0]Not detected [0b1]Detected
DATA_IDLINE	DATA - IDLINE. Data - Idle Line [0b0]Not idle [0b1]Idle
DATA_RXEMPT	DATA - RXEMPT. Data - Receive Buffer Empty [0b0]Valid data [0b1]Invalid data and empty
DATA_FRETSC	DATA - FRETSC. Data - Frame Error Transmit Special Character [0b0]Received without a frame error on reads or transmits a normal character on writes [0b1]Received with a frame error on reads or transmits an idle or break character on writes
DATA_PARITYE	DATA - PARITYE. Data - Parity Error [0b0]Received without a parity error [0b1]Received with a parity error
DATA_NOISY	DATA - NOISY. Data - Noisy Data Received [0b0]Received without noise [0b1]Received with noise
MATCH_MA1	MATCH - MA1. Match Address - Match Address 1
MATCH_MA2	MATCH - MA2. Match Address - Match Address 2
MODIR_TXCTSE	MODIR - TXCTSE. MODEM IrDA - Transmitter CTS Enable [0b0]Disable [0b1]Enable
MODIR_TXRTSE	MODIR - TXRTSE. MODEM IrDA - Transmitter RTS Enable [0b0]Disable [0b1]Enable
MODIR_TXRTSPOL	MODIR - TXRTSPOL. MODEM IrDA - Transmitter RTS Polarity [0b0]Active low [0b1]Active high
MODIR_RXRTSE	MODIR - RXRTSE. MODEM IrDA - Receiver RTS Enable [0b0]Disable [0b1]Enable
MODIR_TXCTSC	MODIR - TXCTSC. MODEM IrDA - Transmit CTS Configuration [0b0]Sampled at the start of each character [0b1]Sampled when the transmitter is idle
MODIR_TXCTSSRC	MODIR - TXCTSSRC. MODEM IrDA - Transmit CTS Source [0b0]The CTS_B pin [0b1]An internal connection to the receiver address match result
MODIR_RTSWATER	MODIR - RTSWATER. MODEM IrDA - Receive RTS Configuration
MODIR_TNP	MODIR - TNP. MODEM IrDA - Transmitter Narrow Pulse [0b00]1 / OSR [0b01]2 / OSR [0b10]3 / OSR [0b11]4 / OSR
MODIR_IREN	MODIR - IREN. MODEM IrDA - IR Enable [0b0]Disable [0b1]Enable
FIFO_RXFIFOSIZE	FIFO - RXFIFOSIZE. FIFO - Receive FIFO Buffer Depth [0b000]1 [0b001]4 [0b010]8 [0b011]16 [0b100]32 [0b101]64 [0b110]128 [0b111]256
FIFO_RXFE	FIFO - RXFE. FIFO - Receive FIFO Enable [0b0]Disable [0b1]Enable
FIFO_TXFIFOSIZE	FIFO - TXFIFOSIZE. FIFO - Transmit FIFO Buffer Depth [0b000]1 [0b001]4 [0b010]8 [0b011]16 [0b100]32 [0b101]64 [0b110]128 [0b111]256
FIFO_TXFE	FIFO - TXFE. FIFO - Transmit FIFO Enable [0b0]Disable [0b1]Enable
FIFO_RXUFE	FIFO - RXUFE. FIFO - Receive FIFO Underflow Interrupt Enable [0b0]Disable [0b1]Enable
FIFO_TXOFE	FIFO - TXOFE. FIFO - Transmit FIFO Overflow Interrupt Enable [0b0]Disable [0b1]Enable
FIFO_RXIDEN	FIFO - RXIDEN. FIFO - Receiver Idle Empty Enable [0b000]Disable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle [0b001]Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for one character [0b010]Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for two characters [0b011]Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for four characters [0b100]Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for eight characters [0b101]Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 16 characters [0b110]Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 32 characters [0b111]Enable STAT[RDRF] to become 1 because of partially filled FIFO when the receiver is idle for 64 characters
FIFO_RXFLUSH	FIFO - RXFLUSH. FIFO - Receive FIFO Flush [0b0]No effect [0b1]All data flushed out
FIFO_TXFLUSH	FIFO - TXFLUSH. FIFO - Transmit FIFO Flush [0b0]No effect [0b1]All data flushed out
FIFO_RXUF	FIFO - RXUF. FIFO - Receiver FIFO Underflow Flag [0b0]No underflow [0b1]Underflow [0b0]No effect [0b1]Clear the flag
FIFO_TXOF	FIFO - TXOF. FIFO - Transmitter FIFO Overflow Flag [0b0]No overflow [0b1]Overflow [0b0]No effect [0b1]Clear the flag
FIFO_RXEMPT	FIFO - RXEMPT. FIFO - Receive FIFO Or Buffer Empty [0b0]Not empty [0b1]Empty
FIFO_TXEMPT	FIFO - TXEMPT. FIFO - Transmit FIFO Or Buffer Empty [0b0]Not empty [0b1]Empty
WATER_TXWATER	WATER - TXWATER. Watermark - Transmit Watermark
WATER_TXCOUNT	WATER - TXCOUNT. Watermark - Transmit Counter
WATER_RXWATER	WATER - RXWATER. Watermark - Receive Watermark
WATER_RXCOUNT	WATER - RXCOUNT. Watermark - Receive Counter
DATARO_DATA	DATARO - DATA. Data Read-Only - Receive Data

Shift

enum struct mcxa153::chip::lpuart::Shift : unsigned int

strong

LPUART 暫存器位元位移枚舉

定義了 LPUART (Low Power UART) 週邊各暫存器位元欄位的位移量， 用於位元操作和暫存器欄位存取。每個位移量對應特定暫存器的特定位元欄位起始位置。

註

使用 unsigned int 作為底層型別以提供足夠的位移範圍

位移值通常與位元遮罩配合使用進行暫存器操作

包含版本資訊、參數配置、控制狀態和資料傳輸等各方面的位元欄位

列舉值
VERID_FEATURE	VERID - Feature Identification Number. Version ID Feature Identification Number 版本ID特徵識別碼 [0b0000000000000001] Standard feature set 標準功能集 [0b0000000000000011] Standard feature set with MODEM and IrDA support 含MODEM與IrDA支援的標準功能集
VERID_MINOR	VERID - Minor Version Number. Version ID Minor Version Number 版本ID次要版本號
VERID_MAJOR	VERID - Major Version Number. Version ID Major Version Number 版本ID主要版本號
PARAM_TXFIFO	PARAM - Transmit FIFO Size. Parameter Transmit FIFO Size 參數傳輸FIFO大小
PARAM_RXFIFO	PARAM - Receive FIFO Size. Parameter Receive FIFO Size 參數接收FIFO大小
GLOBAL_RST	GLOBAL - Software Reset. Global Software Reset 全域軟體重置 [0b0] Not reset 未重置 [0b1] Reset 重置
PINCFG_TRGSEL	PINCFG - Trigger Select. Pin Configuration Trigger Select 引腳配置觸發選擇 [0b00] Input trigger disabled 輸入觸發禁用 [0b01] Input trigger used instead of the RXD pin input 輸入觸發取代RXD引腳輸入 [0b10] Input trigger used instead of the CTS_B pin input 輸入觸發取代CTS_B引腳輸入 [0b11] Input trigger used to modulate the TXD pin output 輸入觸發用於調製TXD引腳輸出
BAUD_SBR	BAUD - Baud Rate Modulo Divisor. Baud Rate Baud Rate Modulo Divisor 鮑率模數除數
BAUD_SBNS	BAUD - Stop Bit Number Select. Baud Rate Stop Bit Number Select 鮑率停止位元數選擇 [0b0] One stop bit 一個停止位元 [0b1] Two stop bits 兩個停止位元
BAUD_RXEDGIE	BAUD - RX Input Active Edge Interrupt Enable. Baud Rate RX Input Active Edge Interrupt Enable 鮑率RX輸入有效邊緣中斷啟用 [0b0] Disable 停用 [0b1] Enable 啟用
BAUD_LBKDIE	BAUD - LIN Break Detect Interrupt Enable. Baud Rate LIN Break Detect Interrupt Enable 鮑率LIN中斷檢測啟用 [0b0] Disable 停用 [0b1] Enable 啟用
BAUD_RESYNCDIS	BAUD - Resynchronization Disable. Baud Rate Resynchronization Disable 鮑率重新同步禁用 [0b0] Enable 啟用 [0b1] Disable 停用
BAUD_BOTHEDGE	BAUD - Both Edge Sampling. Baud Rate Both Edge Sampling 鮑率雙邊緣採樣 [0b0] Rising edge 上升邊緣 [0b1] Both rising and falling edges 上升與下降邊緣
BAUD_MATCFG	BAUD - Match Configuration. Baud Rate Match Configuration 鮑率匹配配置 [0b00] Address match wake-up 位址匹配喚醒 [0b01] Idle match wake-up 空閒匹配喚醒 [0b10] Match on and match off 匹配開啟與關閉 [0b11] Enables RWU on data match and match on or off 啟用RWU於資料匹配並匹配開啟或關閉
BAUD_RIDMAE	BAUD - Receiver Idle DMA Enable. Baud Rate Receiver Idle DMA Enable 鮑率接收空閒DMA啟用 [0b0] Disable 停用 [0b1] Enable 啟用
BAUD_RDMAE	BAUD - Receiver Full DMA Enable. Baud Rate Receiver Full DMA Enable 鮑率接收滿DMA啟用 [0b0] Disable 停用 [0b1] Enable 啟用
BAUD_TDMAE	BAUD - Transmitter DMA Enable. Baud Rate Transmitter DMA Enable 鮑率傳輸DMA啟用 [0b0] Disable 停用 [0b1] Enable 啟用
BAUD_OSR	BAUD - Oversampling Ratio. Baud Rate Oversampling Ratio 鮑率過採樣比率 [0b00000] Results in an OSR of 16 過採樣比率為16 [0b00001] Reserved 保留 [0b00010] Reserved 保留 [0b00011] Results in an OSR of 4 過採樣比率為4 [0b00100] Results in an OSR of 5 過採樣比率為5 [0b00101] Results in an OSR of 6 過採樣比率為6 [0b00110] Results in an OSR of 7 過採樣比率為7 [0b00111] Results in an OSR of 8 過採樣比率為8 [0b01000] Results in an OSR of 9 過採樣比率為9 [0b01001] Results in an OSR of 10 過採樣比率為10 [0b01010] Results in an OSR of 11 過採樣比率為11 [0b01011] Results in an OSR of 12 過採樣比率為12 [0b01100] Results in an OSR of 13 過採樣比率為13 [0b01101] Results in an OSR of 14 過採樣比率為14 [0b01110] Results in an OSR of 15 過採樣比率為15 [0b01111] Results in an OSR of 16 過採樣比率為16 [0b10000] Results in an OSR of 17 過採樣比率為17 [0b10001] Results in an OSR of 18 過採樣比率為18 [0b10010] Results in an OSR of 19 過採樣比率為19 [0b10011] Results in an OSR of 20 過採樣比率為20 [0b10100] Results in an OSR of 21 過採樣比率為21 [0b10101] Results in an OSR of 22 過採樣比率為22 [0b10110] Results in an OSR of 23 過採樣比率為23 [0b10111] Results in an OSR of 24 過採樣比率為24 [0b11000] Results in an OSR of 25 過採樣比率為25 [0b11001] Results in an OSR of 26 過採樣比率為26 [0b11010] Results in an OSR of 27 過採樣比率為27 [0b11011] Results in an OSR of 28 過採樣比率為28 [0b11100] Results in an OSR of 29 過採樣比率為29 [0b11101] Results in an OSR of 30 過採樣比率為30 [0b11110] Results in an OSR of 31 過採樣比率為31 [0b11111] Results in an OSR of 32 過採樣比率為32
BAUD_M10	BAUD - 10-Bit Mode Select. Baud Rate 10-Bit Mode Select 鮑率10位元模式選擇 [0b0] Receiver and transmitter use 7-bit to 9-bit data characters 接收器和傳輸器使用7位元到9位元資料字元 [0b1] Receiver and transmitter use 10-bit data characters 接收器和傳輸器使用10位元資料字元
BAUD_MAEN2	BAUD - Match Address Mode Enable 2. Baud Rate Match Address Mode Enable 2 Configuration 鮑率匹配位址模式2啟用配置 [0b0] Disable 停用 [0b1] Enable 啟用
BAUD_MAEN1	BAUD - Match Address Mode Enable 1. Baud Rate Match Address Mode Enable 1 Configuration 鮑率匹配位址模式1啟用配置 [0b0] Disable 停用 [0b1] Enable 啟用
STAT_LBKFE	STAT_LBKFE - LIN Break Flag Enable. Status register LIN break flag enable control. 狀態暫存器LIN中斷旗標致能控制。 [0b0] Disable LIN break flag 停用LIN中斷旗標 [0b1] Enable LIN break flag 啟用LIN中斷旗標
STAT_AME	STAT_AME - Address Mark Enable. Status register address mark enable control. 狀態暫存器位址標記致能控制。 [0b0] Disable address mark detection 停用位址標記檢測 [0b1] Enable address mark detection 啟用位址標記檢測
STAT_MA2F	STAT_MA2F - Match 2 Flag. Status register match 2 flag control. 狀態暫存器匹配2旗標控制。 [0b0] Not equal to MA2 不等於MA2 [0b1] Equal to MA2 等於MA2 [0b0] No effect 無效 [0b1] Clear the flag 清除旗標
STAT_MA1F	STAT_MA1F - Match 1 Flag. Status register match 1 flag control. 狀態暫存器匹配1旗標控制。 [0b0] Not equal to MA1 不等於MA1 [0b1] Equal to MA1 等於MA1 [0b0] No effect 無效 [0b1] Clear the flag 清除旗標
STAT_PF	STAT_PF - Parity Error Flag. Status register parity error flag control. 狀態暫存器奇偶校驗錯誤旗標控制。 [0b0] No parity error detected 未檢測到奇偶校驗錯誤 [0b1] Parity error detected 檢測到奇偶校驗錯誤 [0b0] No effect 無效 [0b1] Clear the flag 清除旗標
STAT_FE	STAT_FE - Framing Error Flag. Status register framing error flag control. 狀態暫存器幀錯誤旗標控制。 [0b0] No framing error detected 未檢測到幀錯誤 [0b1] Framing error detected 檢測到幀錯誤 [0b0] No effect 無效 [0b1] Clear the flag 清除旗標
STAT_NF	STAT_NF - Noise Flag. Status register noise flag control. 狀態暫存器噪聲旗標控制。 [0b0] No noise detected 未檢測到噪聲 [0b1] Noise detected 檢測到噪聲 [0b0] No effect 無效 [0b1] Clear the flag 清除旗標
STAT_OR	STAT_OR - Receiver Overrun Flag. Status register receiver overrun flag control. 狀態暫存器接收器溢出旗標控制。 [0b0] No overrun 無溢出 [0b1] Receive overrun 接收溢出 [0b0] No effect 無效 [0b1] Clear the flag 清除旗標
STAT_IDLE	STAT_IDLE - Idle Line Flag. Status register idle line flag control. 狀態暫存器空閒線旗標控制。 [0b0] Idle line detected 檢測到空閒線 [0b1] Idle line not detected 未檢測到空閒線 [0b0] No effect 無效 [0b1] Clear the flag 清除旗標
STAT_RDRF	STAT_RDRF - Receive Data Register Full Flag. Status register receive data register full flag control. 狀態暫存器接收數據暫存器滿旗標控制。 [0b0] Equal to or less than watermark 等於或小於水位線 [0b1] Greater than watermark 大於水位線
STAT_TC	STAT_TC - Transmission Complete Flag. Status register transmission complete flag control. 狀態暫存器傳輸完成旗標控制。 [0b0] Transmitter active 傳輸器活躍 [0b1] Transmitter idle 傳輸器空閒
STAT_TDRE	STAT_TDRE - Transmit Data Register Empty Flag. Status register transmit data register empty flag control. 狀態暫存器傳輸數據暫存器空旗標控制。 [0b0] Greater than watermark 大於水位線 [0b1] Equal to or less than watermark 等於或小於水位線
STAT_RAF	STAT_RAF - Receiver Active Flag. Status register receiver active flag control. 狀態暫存器接收器活躍旗標控制。 [0b0] Idle, waiting for a start bit 空閒，等待起始位 [0b1] Receiver active 接收器活躍
STAT_LBKDE	STAT_LBKDE - LIN Break Detection Enable. Status register LIN break detection enable control. 狀態暫存器LIN中斷檢測致能控制。 [0b0] Disable 停用 [0b1] Enable 啟用
STAT_BRK13	STAT_BRK13 - Break Character Generation Length. Status register break character generation length control. 狀態暫存器中斷字符生成長度控制。 [0b0] 9 to 13 bit times 9到13位時間 [0b1] 12 to 15 bit times 12到15位時間
STAT_RWUID	STAT_RWUID - Receive Wake Up Idle Detect. Status register receive wake up idle detect control. 狀態暫存器接收喚醒空閒檢測控制。 [0b0] STAT[IDLE] does not become 1 STAT[IDLE]不變為1 [0b1] STAT[IDLE] becomes 1 STAT[IDLE]變為1
STAT_RXINV	STAT_RXINV - Receive Data Inversion. Status register receive data inversion control. 狀態暫存器接收數據反轉控制。 [0b0] Inverted 反轉 [0b1] Not inverted 未反轉
STAT_MSBF	STAT_MSBF - MSB First. Status register MSB first control. 狀態暫存器MSB優先控制。 [0b0] LSB LSB [0b1] MSB MSB
STAT_RXEDGIF	STAT_RXEDGIF - RXD Pin Active Edge Interrupt Flag. Status register RXD pin active edge interrupt flag control. 狀態暫存器RXD引腳活躍邊緣中斷旗標控制。 [0b0] Not occurred 未發生 [0b1] Occurred 發生 [0b0] No effect 無效 [0b1] Clear the flag 清除旗標
STAT_LBKDIF	STAT_LBKDIF - LIN Break Detect Interrupt Flag. Status register LIN break detect interrupt flag control. 狀態暫存器LIN中斷檢測中斷旗標控制。 [0b0] Not detected 未檢測到 [0b1] Detected 檢測到 [0b0] No effect 無效 [0b1] Clear the flag 清除旗標
CTRL_PT	CTRL_PT - Parity Type. Control register parity type control. 控制暫存器奇偶校驗類型控制。 [0b0] Even parity 偶校驗 [0b1] Odd parity 奇校驗
CTRL_PE	CTRL_PE - Parity Enable. Control register parity enable control. 控制暫存器奇偶校驗致能控制。 [0b0] Disable 停用 [0b1] Enable 啟用
CTRL_ILT	CTRL_ILT - Idle Line Type Select. Control register idle line type select control. 控制暫存器空閒線類型選擇控制。 [0b0] After the start bit 起始位後 [0b1] After the stop bit 停止位後
CTRL_WAKE	CTRL_WAKE - Receiver Wake-Up Method Select. Control register receiver wake-up method select control. 控制暫存器接收器喚醒方法選擇控制。 [0b0] Idle 空閒 [0b1] Mark 標記
CTRL_M	CTRL_M - 9-Bit Or 8-Bit Mode Select. Control register 9-bit or 8-bit mode select control. 控制暫存器9位或8位模式選擇控制。 [0b0] 8-bit 8位 [0b1] 9-bit 9位
CTRL_RSRC	CTRL_RSRC - Receiver Source Select. Control register receiver source select control. 控制暫存器接收器來源選擇控制。 [0b0] Internal Loopback mode 內部回環模式 [0b1] Single-wire mode 單線模式
CTRL_DOZEEN	CTRL_DOZEEN - Doze Mode. Control register doze mode control. 控制暫存器打盹模式控制。 [0b0] Enable 啟用 [0b1] Disable 停用
CTRL_LOOPS	CTRL_LOOPS - Loop Mode Select. Control register loop mode select control. 控制暫存器回環模式選擇控制。 [0b0] Normal operation 正常操作 [0b1] Loop mode or Single-Wire mode 回環模式或單線模式
CTRL_IDLECFG	CTRL_IDLECFG - Idle Configuration. Control register idle configuration control. 控制暫存器空閒配置控制。 [0b000] 1 1 [0b001] 2 2 [0b010] 4 4 [0b011] 8 8 [0b100] 16 16 [0b101] 32 32 [0b110] 64 64 [0b111] 128 128
CTRL_M7	CTRL_M7 - 7-Bit Mode Select. Control register 7-bit mode select control. 控制暫存器7位模式選擇控制。 [0b0] 8-bit to 10-bit 8位到10位 [0b1] 7-bit 7位
CTRL_MA2IE	CTRL_MA2IE - Match 2 (MA2F) Interrupt Enable. Control register match 2 (MA2F) interrupt enable control. 控制暫存器匹配2(MA2F)中斷致能控制。 [0b0] Disable 停用 [0b1] Enable 啟用
CTRL_MA1IE	CTRL_MA1IE - Match 1 (MA1F) Interrupt Enable. Control register match 1 (MA1F) interrupt enable control. 控制暫存器匹配1(MA1F)中斷致能控制。 [0b0] Disable 停用 [0b1] Enable 啟用
CTRL_SBK	CTRL_SBK - Send Break. Control register send break control. 控制暫存器發送中斷控制。 [0b0] Normal transmitter operation 正常傳輸器操作 [0b1] Queue break character(s) to be sent 排隊發送中斷字符
CTRL_RWU	CTRL_RWU - Receiver Wake-Up Control. Control register receiver wake-up control. 控制暫存器接收器喚醒控制。 [0b0] Normal receiver operation 正常接收器操作 [0b1] LPUART receiver in standby LPUART接收器待機
CTRL_RE	CTRL_RE - Receiver Enable. Control register receiver enable control. 控制暫存器接收器致能控制。 [0b0] Disable 停用 [0b1] Enable 啟用
CTRL_TE	CTRL_TE - Transmitter Enable. Control register transmitter enable control. 控制暫存器傳輸器致能控制。 [0b0] Disable 停用 [0b1] Enable 啟用
CTRL_ILIE	CTRL_ILIE - Idle Line Interrupt Enable. Control register idle line interrupt enable control. 控制暫存器空閒線中斷致能控制。 [0b0] Disable 停用 [0b1] Enable 啟用
CTRL_RIE	CTRL_RIE - Receiver Interrupt Enable. Control register receiver interrupt enable control. 控制暫存器接收器中斷致能控制。 [0b0] Disable 停用 [0b1] Enable 啟用
CTRL_TCIE	CTRL_TCIE - Transmission Complete Interrupt Enable. Control register transmission complete interrupt enable control. 控制暫存器傳輸完成中斷致能控制。 [0b0] Disable 停用 [0b1] Enable 啟用
CTRL_TIE	CTRL_TIE - Transmit Interrupt Enable. Control register transmit interrupt enable control. 控制暫存器傳輸中斷致能控制。 [0b0] Disable 停用 [0b1] Enable 啟用
CTRL_PEIE	CTRL_PEIE - Parity Error Interrupt Enable. Control register parity error interrupt enable control. 控制暫存器奇偶校驗錯誤中斷致能控制。 [0b0] Disable 停用 [0b1] Enable 啟用
CTRL_FEIE	CTRL_FEIE - Framing Error Interrupt Enable. Control register framing error interrupt enable control. 控制暫存器幀錯誤中斷致能控制。 [0b0] Disable 停用 [0b1] Enable 啟用
CTRL_NEIE	CTRL_NEIE - Noise Error Interrupt Enable. Control register noise error interrupt enable control. 控制暫存器噪聲錯誤中斷致能控制。 [0b0] Disable 停用 [0b1] Enable 啟用
CTRL_ORIE	CTRL_ORIE - Overrun Interrupt Enable. Control register overrun interrupt enable control. 控制暫存器溢出中斷致能控制。 [0b0] Disable 停用 [0b1] Enable 啟用
CTRL_TXINV	CTRL_TXINV - Transmit Data Inversion. Control register transmit data inversion control. 控制暫存器傳輸數據反轉控制。 [0b0] Not inverted 未反轉 [0b1] Inverted 反轉
CTRL_TXDIR	CTRL_TXDIR - TXD Pin Direction in Single-Wire Mode. Control register TXD pin direction in single-wire mode control. 控制暫存器TXD引腳方向在單線模式控制。 [0b0] Input 輸入 [0b1] Output 輸出
CTRL_R9T8	CTRL_R9T8 - Receive Bit 9 Transmit Bit 8. Control register receive bit 9 transmit bit 8 control. 控制暫存器接收位9傳輸位8控制。
CTRL_R8T9	CTRL_R8T9 - Receive Bit 8 Transmit Bit 9. Control register receive bit 8 transmit bit 9 control. 控制暫存器接收位8傳輸位9控制。
DATA_R0T0	DATA_R0T0 - Read Receive FIFO Bit 0 or Write Transmit FIFO Bit 0. Data register read receive FIFO bit 0 or write transmit FIFO bit 0 control. 數據暫存器讀取接收FIFO位0或寫入傳輸FIFO位0控制。
DATA_R1T1	DATA_R1T1 - Read Receive FIFO Bit 1 or Write Transmit FIFO Bit 1. Data register read receive FIFO bit 1 or write transmit FIFO bit 1 control. 數據暫存器讀取接收FIFO位1或寫入傳輸FIFO位1控制。
DATA_R2T2	DATA_R2T2 - Read Receive FIFO Bit 2 or Write Transmit FIFO Bit 2. Data register read receive FIFO bit 2 or write transmit FIFO bit 2 control. 數據暫存器讀取接收FIFO位2或寫入傳輸FIFO位2控制。
DATA_R3T3	DATA_R3T3 - Read Receive FIFO Bit 3 or Write Transmit FIFO Bit 3. Data register read receive FIFO bit 3 or write transmit FIFO bit 3 control. 數據暫存器讀取接收FIFO位3或寫入傳輸FIFO位3控制。
DATA_R4T4	DATA_R4T4 - Read Receive FIFO Bit 4 or Write Transmit FIFO Bit 4. Data register read receive FIFO bit 4 or write transmit FIFO bit 4 control. 數據暫存器讀取接收FIFO位4或寫入傳輸FIFO位4控制。
DATA_R5T5	DATA_R5T5 - Read Receive FIFO Bit 5 or Write Transmit FIFO Bit 5. Data register read receive FIFO bit 5 or write transmit FIFO bit 5 control. 數據暫存器讀取接收FIFO位5或寫入傳輸FIFO位5控制。
DATA_R6T6	DATA_R6T6 - Read Receive FIFO Bit 6 or Write Transmit FIFO Bit 6. Data register read receive FIFO bit 6 or write transmit FIFO bit 6 control. 數據暫存器讀取接收FIFO位6或寫入傳輸FIFO位6控制。
DATA_R7T7	DATA_R7T7 - Read Receive FIFO Bit 7 or Write Transmit FIFO Bit 7. Data register read receive FIFO bit 7 or write transmit FIFO bit 7 control. 數據暫存器讀取接收FIFO位7或寫入傳輸FIFO位7控制。
DATA_R8T8	DATA_R8T8 - Read Receive FIFO Bit 8 or Write Transmit FIFO Bit 8. Data register read receive FIFO bit 8 or write transmit FIFO bit 8 control. 數據暫存器讀取接收FIFO位8或寫入傳輸FIFO位8控制。
DATA_R9T9	DATA_R9T9 - Read Receive FIFO Bit 9 or Write Transmit FIFO Bit 9. Data register read receive FIFO bit 9 or write transmit FIFO bit 9 control. 數據暫存器讀取接收FIFO位9或寫入傳輸FIFO位9控制。
DATA_LINBRK	DATA_LINBRK - LIN Break. Data register LIN break control. 數據暫存器LIN中斷控制。 [0b0] Not detected 未檢測到 [0b1] Detected 檢測到
DATA_IDLINE	DATA_IDLINE - Idle Line. Data register idle line control. 數據暫存器空閒線控制。 [0b0] Not idle 未空閒 [0b1] Idle 空閒
DATA_RXEMPT	DATA_RXEMPT - Receive Buffer Empty. Data register receive buffer empty control. 數據暫存器接收緩衝區空控制。 [0b0] Valid data 有效數據 [0b1] Invalid data and empty 無效數據且空
DATA_FRETSC	DATA_FRETSC - Frame Error Transmit Special Character. Data register frame error transmit special character control. 數據暫存器幀錯誤傳輸特殊字符控制。 [0b0] Received without a frame error 無幀錯誤接收 [0b1] Received with a frame error 有幀錯誤接收
DATA_PARITYE	DATA_PARITYE - Parity Error. Data register parity error control. 數據暫存器奇偶校驗錯誤控制。 [0b0] Received without a parity error 無奇偶校驗錯誤接收 [0b1] Received with a parity error 有奇偶校驗錯誤接收
DATA_NOISY	DATA_NOISY - Noisy Data Received. Data register noisy data received control. 數據暫存器噪聲數據接收控制。 [0b0] Received without noise 無噪聲接收 [0b1] Received with noise 有噪聲接收
MATCH_MA1	MATCH_MA1 - Match Address 1. Match register match address 1 control. 匹配暫存器匹配地址1控制。
MATCH_MA2	MATCH_MA2 - Match Address 2. Match register match address 2 control. 匹配暫存器匹配地址2控制。
MODIR_TXCTSE	MODIR_TXCTSE - Transmitter CTS Enable. MODEM IrDA transmitter CTS enable control. MODEM IrDA傳輸器CTS致能控制。 [0b0] Disable 停用 [0b1] Enable 啟用
MODIR_TXRTSE	MODIR_TXRTSE - Transmitter RTS Enable. MODEM IrDA transmitter RTS enable control. MODEM IrDA傳輸器RTS致能控制。 [0b0] Disable 停用 [0b1] Enable 啟用
MODIR_TXRTSPOL	MODIR_TXRTSPOL - Transmitter RTS Polarity. MODEM IrDA transmitter RTS polarity control. MODEM IrDA傳輸器RTS極性控制。 [0b0] Active low 低電平活躍 [0b1] Active high 高電平活躍
MODIR_RXRTSE	MODIR_RXRTSE - Receiver RTS Enable. MODEM IrDA receiver RTS enable control. MODEM IrDA接收器RTS致能控制。 [0b0] Disable 停用 [0b1] Enable 啟用
MODIR_TXCTSC	MODIR_TXCTSC - Transmit CTS Configuration. MODEM IrDA transmit CTS configuration control. MODEM IrDA傳輸CTS配置控制。 [0b0] Sampled at the start of each character 每個字符開始時取樣 [0b1] Sampled when the transmitter is idle 傳輸器空閒時取樣
MODIR_TXCTSSRC	MODIR_TXCTSSRC - Transmit CTS Source. MODEM IrDA transmit CTS source control. MODEM IrDA傳輸CTS來源控制。 [0b0] The CTS_B pin CTS_B引腳 [0b1] An internal connection to the receiver address match result 與接收器地址匹配結果的內部連接
MODIR_RTSWATER	MODIR_RTSWATER - Receive RTS Configuration. MODEM IrDA receive RTS configuration control. MODEM IrDA接收RTS配置控制。
MODIR_TNP	MODIR_TNP - Transmitter Narrow Pulse. MODEM IrDA transmitter narrow pulse control. MODEM IrDA傳輸器窄脈衝控制。 [0b00] 1 / OSR 1 / OSR [0b01] 2 / OSR 2 / OSR [0b10] 3 / OSR 3 / OSR [0b11] 4 / OSR 4 / OSR
MODIR_IREN	MODIR_IREN - IR Enable. MODEM IrDA IR enable control. MODEM IrDA紅外致能控制。 [0b0] Disable 停用 [0b1] Enable 啟用
FIFO_RXFIFOSIZE	FIFO_RXFIFOSIZE - Receive FIFO Buffer Depth. FIFO receive FIFO buffer depth control. FIFO接收FIFO緩衝區深度控制。 [0b000] 1 1 [0b001] 4 4 [0b010] 8 8 [0b011] 16 16 [0b100] 32 32 [0b101] 64 64 [0b110] 128 128 [0b111] 256 256
FIFO_RXFE	FIFO_RXFE - Receive FIFO Enable. FIFO receive FIFO enable control. FIFO接收FIFO致能控制。 [0b0] Disable 停用 [0b1] Enable 啟用
FIFO_TXFIFOSIZE	FIFO_TXFIFOSIZE - Transmit FIFO Buffer Depth. FIFO transmit FIFO buffer depth control. FIFO傳輸FIFO緩衝區深度控制。 [0b000] 1 1 [0b001] 4 4 [0b010] 8 8 [0b011] 16 16 [0b100] 32 32 [0b101] 64 64 [0b110] 128 128 [0b111] 256 256
FIFO_TXFE	FIFO_TXFE - Transmit FIFO Enable. FIFO transmit FIFO enable control. FIFO傳輸FIFO致能控制。 [0b0] Disable 停用 [0b1] Enable 啟用
FIFO_RXUFE	FIFO_RXUFE - Receive FIFO Underflow Interrupt Enable. FIFO receive FIFO underflow interrupt enable control. FIFO接收FIFO下溢中斷致能控制。 [0b0] Disable 停用 [0b1] Enable 啟用
FIFO_TXOFE	FIFO_TXOFE - Transmit FIFO Overflow Interrupt Enable. FIFO transmit FIFO overflow interrupt enable control. FIFO傳輸FIFO溢出中斷致能控制。 [0b0] Disable 停用 [0b1] Enable 啟用
FIFO_RXIDEN	FIFO_RXIDEN - Receiver Idle Empty Enable. FIFO receiver idle empty enable control. FIFO接收器空閒空致能控制。 [0b000] Disable 停用 [0b001] Enable for one character 啟用一個字符 [0b010] Enable for two characters 啟用兩個字符 [0b011] Enable for four characters 啟用四個字符 [0b100] Enable for eight characters 啟用八個字符 [0b101] Enable for 16 characters 啟用16個字符 [0b110] Enable for 32 characters 啟用32個字符 [0b111] Enable for 64 characters 啟用64個字符
FIFO_RXFLUSH	FIFO_RXFLUSH - Receive FIFO Flush. FIFO receive FIFO flush control. FIFO接收FIFO刷新控制。 [0b0] No effect 無效 [0b1] All data flushed out 所有數據刷新
FIFO_TXFLUSH	FIFO_TXFLUSH - Transmit FIFO Flush. FIFO transmit FIFO flush control. FIFO傳輸FIFO刷新控制。 [0b0] No effect 無效 [0b1] All data flushed out 所有數據刷新
FIFO_RXUF	FIFO_RXUF - Receiver FIFO Underflow Flag. FIFO receiver FIFO underflow flag control. FIFO接收FIFO下溢旗標控制。 [0b0] No underflow 無下溢 [0b1] Underflow 下溢 [0b0] No effect 無效 [0b1] Clear the flag 清除旗標
FIFO_TXOF	FIFO_TXOF - Transmitter FIFO Overflow Flag. FIFO transmitter FIFO overflow flag control. FIFO傳輸FIFO溢出旗標控制。 [0b0] No overflow 無溢出 [0b1] Overflow 溢出 [0b0] No effect 無效 [0b1] Clear the flag 清除旗標
FIFO_RXEMPT	FIFO_RXEMPT - Receive FIFO Or Buffer Empty. FIFO receive FIFO or buffer empty control. FIFO接收FIFO或緩衝區空控制。 [0b0] Not empty 非空 [0b1] Empty 空
FIFO_TXEMPT	FIFO_TXEMPT - Transmit FIFO Or Buffer Empty. FIFO transmit FIFO or buffer empty control. FIFO傳輸FIFO或緩衝區空控制。 [0b0] Not empty 非空 [0b1] Empty 空
WATER_TXWATER	WATER_TXWATER - Transmit Watermark. Watermark register transmit watermark control. 水位暫存器傳輸水位控制。
WATER_TXCOUNT	WATER_TXCOUNT - Transmit Counter. Watermark register transmit counter control. 水位暫存器傳輸計數器控制。
WATER_RXWATER	WATER_RXWATER - Receive Watermark. Watermark register receive watermark control. 水位暫存器接收水位控制。
WATER_RXCOUNT	WATER_RXCOUNT - Receive Counter. Watermark register receive counter control. 水位暫存器接收計數器控制。
DATARO_DATA	DATARO_DATA - Receive Data. Data read-only register receive data control. 數據只讀暫存器接收數據控制。

函式說明文件

operator+()

unsigned int mcxa153::chip::lpuart::operator+ ( Shift e )

constexpr

Shift Operator Overloading - Convert Enum To Unsigned Integer.

Converts the shift enum value to an unsigned integer. 將位移列舉值轉換為無符號整數。

參數

e	Shift enum to convert 要轉換的位移列舉

傳回值

constexpr unsigned int Converted unsigned integer value 轉換後的無符號整數值

變數說明文件

LPUART0

Register* const mcxa153::chip::lpuart::LPUART0

初值:

=
      reinterpret_cast<Register*>(mcxa153::chip::Processor::BASE_LPUART0)

LPUART1

Register* const mcxa153::chip::lpuart::LPUART1

初值:

=
      reinterpret_cast<Register*>(mcxa153::chip::Processor::BASE_LPUART1)

LPUART2

Register* const mcxa153::chip::lpuart::LPUART2

初值:

=
      reinterpret_cast<Register*>(mcxa153::chip::Processor::BASE_LPUART2)