trdc/Register.h

 
#ifndef MCXA153_BBB2D802_CFE3_48B8_998B_1016F2D66F03
#define MCXA153_BBB2D802_CFE3_48B8_998B_1016F2D66F03
 
/* ***************************************************************************************
 * Include
 */
#include "mframe.h"
 
//----------------------------------------------------------------------------------------
 
//----------------------------------------------------------------------------------------
 
/* ***************************************************************************************
 * Namespace
 */
namespace mcxa153::chip::trdc {
  struct Register;
}  // namespace mcxa153::chip::trdc
 
/* ***************************************************************************************
 * Class/Interface/Struct/Enum
 */
 
struct mcxa153::chip::trdc::Register {
  /* offset: 0x0, array step: 0x1CC */
  struct {
    __IO uint32 mbc_mem_glbcfg[4]; 
    __IO uint32 mbc_nse_blk_index; 
    __O uint32 mbc_nse_blk_set; 
    __O uint32 mbc_nse_blk_clr; 
    __O uint32 mbc_nse_blk_clr_all; 
    __IO uint32 mbc_memn_glbac[8]; 
    __IO uint32 mbc_dom0_mem0_blk_cfg_w[2]; 
    uint8 reserved_0[248];
 
    __IO uint32 mbc_dom0_mem0_blk_nse_w[1]; 
    uint8 reserved_1[60];
 
    __IO uint32 mbc_dom0_mem1_blk_cfg_w[1]; 
    uint8 reserved_2[28];
 
    __IO uint32 mbc_dom0_mem1_blk_nse_w[1]; 
    uint8 reserved_3[4];
 
    __IO uint32 mbc_dom0_mem2_blk_cfg_w[1]; 
    uint8 reserved_4[28];
 
    __IO uint32 mbc_dom0_mem2_blk_nse_w[1]; 
  } mbc_index[1];
};
 
/* ***************************************************************************************
 * End of file
 */
 
#endif /* MCXA153_BBB2D802_CFE3_48B8_998B_1016F2D66F03 */