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port/Shift.h
1
7#ifndef MCXA153_BBD6B536_1670_42A7_8CD2_2C94F33F057D
8#define MCXA153_BBD6B536_1670_42A7_8CD2_2C94F33F057D
9
10/* ***************************************************************************************
11 * Include
12 */
13#include "mframe.h"
14
15//----------------------------------------------------------------------------------------
16
17//----------------------------------------------------------------------------------------
18
19/* ***************************************************************************************
20 * Namespace
21 */
22namespace mcxa153::chip::port {
23 enum struct Shift : unsigned int;
24
34 constexpr unsigned int operator+(Shift e) {
35 return static_cast<unsigned int>(e);
36 }
37} // namespace mcxa153::chip::port
38
39/* ***************************************************************************************
40 * Class/Interface/Struct/Enum
41 */
42
55enum struct mcxa153::chip::port::Shift : unsigned int {
64 VERID_FEATURE = 0U,
65
72 VERID_MINOR = 16U,
73
80 VERID_MAJOR = 24U,
81
88 GPCLR_GPWD = 0U,
89
100 GPCLR_GPWE0 = 16U,
101
112 GPCLR_GPWE1 = 17U,
113
124 GPCLR_GPWE2 = 18U,
125
136 GPCLR_GPWE3 = 19U,
137
148 GPCLR_GPWE4 = 20U,
149
160 GPCLR_GPWE5 = 21U,
161
172 GPCLR_GPWE6 = 22U,
173
184 GPCLR_GPWE7 = 23U,
185
196 GPCLR_GPWE8 = 24U,
197
208 GPCLR_GPWE9 = 25U,
209
220 GPCLR_GPWE10 = 26U,
221
232 GPCLR_GPWE11 = 27U,
233
244 GPCLR_GPWE12 = 28U,
245
256 GPCLR_GPWE13 = 29U,
257
268 GPCLR_GPWE14 = 30U,
269
280 GPCLR_GPWE15 = 31U,
281
288 GPCHR_GPWD = 0U,
289
300 GPCHR_GPWE16 = 16U,
301
312 GPCHR_GPWE17 = 17U,
313
324 GPCHR_GPWE18 = 18U,
325
336 GPCHR_GPWE19 = 19U,
337
348 GPCHR_GPWE20 = 20U,
349
360 GPCHR_GPWE21 = 21U,
361
372 GPCHR_GPWE22 = 22U,
373
384 GPCHR_GPWE23 = 23U,
385
396 GPCHR_GPWE24 = 24U,
397
408 GPCHR_GPWE25 = 25U,
409
420 GPCHR_GPWE26 = 26U,
421
432 GPCHR_GPWE27 = 27U,
433
444 GPCHR_GPWE28 = 28U,
445
456 GPCHR_GPWE29 = 29U,
457
468 GPCHR_GPWE30 = 30U,
469
480 GPCHR_GPWE31 = 31U,
481
492 CONFIG_RANGE = 0U,
493
500 CALIB0_NCAL = 0U,
501
508 CALIB0_PCAL = 16U,
509
516 CALIB1_NCAL = 0U,
517
524 CALIB1_PCAL = 16U,
525
536 PCR_PS = 0U,
537
548 PCR_PE = 1U,
549
560 PCR_PV = 2U,
561
572 PCR_SRE = 3U,
573
584 PCR_PFE = 4U,
585
596 PCR_ODE = 5U,
597
608 PCR_DSE = 6U,
609
620 PCR_DSE1 = 7U,
621
656 PCR_MUX = 8U,
657
668 PCR_IBE = 12U,
669
680 PCR_INV = 13U,
681
692 PCR_LK = 15U
693};
694
695/* ***************************************************************************************
696 * End of file
697 */
698
699#endif /* MCXA153_BBD6B536_1670_42A7_8CD2_2C94F33F057D */
Definition Config.h:36
Shift
Shift Enumeration for Port Control Register Bit Positions.
Definition port/Shift.h:55
@ GPCLR_GPWE13
GPCLR - GPWE13.
@ GPCLR_GPWE15
GPCLR - GPWE15.
@ GPCLR_GPWE8
GPCLR - GPWE8.
@ GPCLR_GPWE3
GPCLR - GPWE3.
@ GPCHR_GPWE25
GPCHR - GPWE25.
@ GPCHR_GPWE23
GPCHR - GPWE23.
@ GPCLR_GPWE5
GPCLR - GPWE5.
@ GPCHR_GPWE24
GPCHR - GPWE24.
@ GPCHR_GPWE22
GPCHR - GPWE22.
@ CALIB1_NCAL
CALIB1 - NCAL.
@ GPCLR_GPWE10
GPCLR - GPWE10.
@ GPCHR_GPWE30
GPCHR - GPWE30.
@ GPCHR_GPWD
GPCHR - GPWD.
@ CALIB0_PCAL
CALIB0 - PCAL.
@ GPCHR_GPWE20
GPCHR - GPWE20.
@ GPCHR_GPWE31
GPCHR - GPWE31.
@ GPCLR_GPWE2
GPCLR - GPWE2.
@ GPCLR_GPWE1
GPCLR - GPWE1.
@ GPCLR_GPWE11
GPCLR - GPWE11.
@ GPCLR_GPWE7
GPCLR - GPWE7.
@ GPCLR_GPWE12
GPCLR - GPWE12.
@ GPCLR_GPWE14
GPCLR - GPWE14.
@ GPCHR_GPWE28
GPCHR - GPWE28.
@ GPCHR_GPWE27
GPCHR - GPWE27.
@ GPCHR_GPWE16
GPCHR - GPWE16.
@ GPCHR_GPWE19
GPCHR - GPWE19.
@ CALIB0_NCAL
CALIB0 - NCAL.
@ GPCLR_GPWD
GPCLR - GPWD.
@ GPCHR_GPWE18
GPCHR - GPWE18.
@ GPCLR_GPWE0
GPCLR - GPWE0.
@ CALIB1_PCAL
CALIB1 - PCAL.
@ GPCHR_GPWE17
GPCHR - GPWE17.
@ GPCLR_GPWE9
GPCLR - GPWE9.
@ GPCLR_GPWE4
GPCLR - GPWE4.
@ GPCHR_GPWE26
GPCHR - GPWE26.
@ CONFIG_RANGE
CONFIG - RANGE.
@ GPCHR_GPWE29
GPCHR - GPWE29.
@ GPCHR_GPWE21
GPCHR - GPWE21.
@ GPCLR_GPWE6
GPCLR - GPWE6.