mcxa153::chip::reset 命名空間(Namespace)參考文件

複合項目
class	Reset
	MCXA153 周邊模組重設控制靜態工具類別 更多...

列舉型態
enum struct	Control : unsigned short {   Typical , INPUTMUX0 = (0U | (0U)) , I3C , I3C0 = (0U | (1U)) ,   Timer , CTIMER0 = (0U | (2U)) , Multi-Timer , CTIMER1 = (0U | (3U)) ,   CTIMER2 = (0U | (4U)) , Clock , FREQME = (0U | (5U)) , System ,   UTICK0 = (0U | (6U)) , DMA , DMA = (0U | (8U)) , Logic ,   AOI0 = (0U | (9U)) , Data , CRC = (0U | (10U)) , EIM = (0U | (11U)) ,   ERM = (0U | (12U)) , I2C , LPI2C0 = (0U | (16U)) , SPI ,   LPSPI0 = (0U | (17U)) , LPSPI1 = (0U | (18U)) , Debug , LPUART0 = (0U | (19U)) ,   LPUART1 = (0U | (20U)) , LPUART2 = (0U | (21U)) , USB , USB0 = (0U | (22U)) ,   Motor , QDC0 = (0U | (23U)) , Motor , FLEXPWM0 = (0U | (24U)) ,   OSTIMER0 = (0U | (25U)) , Sensor , ADC0 = (0U | (26U)) , Threshold ,   CMP1 = (0U | (28U)) , Pin , PORT0 = (0U | (29U)) , PORT1 = (0U | (30U)) ,   PORT2 = (0U | (31U)) , PORT3 = ((1U << 8U) | (0U)) , ATX0 = ((1U << 8U) | (1U)) , GPIO ,   GPIO0 = ((1U << 8U) | (5U)) , GPIO1 = ((1U << 8U) | (6U)) , GPIO2 = ((1U << 8U) | (7U)) , GPIO3 = ((1U << 8U) | (8U)) ,   Reset , NOT_AVAIL = (0xFFFFU) }
	MCXA153 Peripheral Reset Control Identifiers. 更多...

函式
constexpr unsigned short	operator+ (Control e)

詳細描述

Copyright (c) 2020 ZxyKira All rights reserved.

SPDX-License-Identifier: MIT

列舉型態說明文件

Control

enum struct mcxa153::chip::reset::Control : unsigned short

strong

MCXA153 Peripheral Reset Control Identifiers.

Defines reset control identifiers for all peripheral modules in the MCXA153 microcontroller. Each enum value represents a specific peripheral that can be individually reset through the system reset controller. The values encode both the register index and bit position within the reset control registers.

MCXA153 外設重置控制識別符，用於控制各個外設模組的重置狀態

Register Encoding:

• Bits [7:0]: Bit position within the reset control register
• Bits [15:8]: Register index (0 = first register, 1 = second register, etc.)
• Value 0xFFFF: Indicates no reset control available for the peripheral

Reset Control Process:

1. Assert reset: Set corresponding bit to disable peripheral clock and hold in reset
2. Clock gating: Peripheral clock is automatically gated when in reset state
3. Release reset: Clear corresponding bit to enable peripheral clock and release from reset
4. Initialization: Peripheral registers return to default values after reset release

註

Reset Control Registers:

• Register 0: Controls peripherals with bit positions 0-31
• Register 1: Controls peripherals with bit positions encoded as (1<<8)|bit
• Additional registers follow the same pattern for system expansion

警告

Reset Sequence Requirements:

• Always assert reset before changing peripheral configuration
• Ensure adequate time for reset propagation (typically 2-4 clock cycles)
• Release reset only after all related system components are properly configured
• Some peripherals may require specific initialization sequences after reset release

列舉值
Typical	Input Multiplexer 0 Reset Control. Controls reset state of the Input Multiplexer 0 (INPUTMUX0) peripheral. INPUTMUX0 provides configurable routing of signals between peripherals and enables flexible interconnection of internal system components. 輸入多工器 0 重置控制，用於信號路由和外設互連 INPUTMUX0 Functions: Trigger signal routing for timers and DMA Interrupt source multiplexing and prioritization Pin-to-peripheral signal connection management Cross-peripheral communication signal routing 註 Reset Effects: All multiplexer connections return to default routing Signal routing tables are cleared to safe defaults Interrupt routing returns to standard configuration Usage: // Reconfigure input multiplexer routing reset_ctrl.assert_reset(Control::INPUTMUX0); inputmux_configure_routing(); reset_ctrl.release_reset(Control::INPUTMUX0);
I3C	I3C0 Interface Reset Control. Controls reset state of the Improved Inter-Integrated Circuit 0 (I3C0) peripheral. I3C0 provides high-speed serial communication with advanced features including in-band interrupts, dynamic addressing, and backward compatibility with I2C. I3C0 介面重置控制，高速串列通訊外設 I3C0 Capabilities: High-speed serial communication (up to 12.5 Mbps) Dynamic address assignment and hot-join capability In-band interrupt (IBI) support for real-time signaling I2C backward compatibility for legacy device support Common Command Codes (CCC) for advanced bus management 註 Reset Effects: Bus interface returns to idle state Dynamic addresses are cleared, requiring reassignment All pending transactions are aborted Interrupt and event configurations are reset 警告 I3C Bus Considerations: Reset may affect other devices on the shared I3C bus Ensure proper bus recovery sequence after reset May require bus mastership transfer if acting as current master Initialization: // Initialize I3C0 with proper reset sequence reset_ctrl.assert_reset(Control::I3C0); configure_i3c_pins_and_clocking(); reset_ctrl.release_reset(Control::I3C0); i3c0_initialize_as_master();
Timer	Counter/Timer 0 Reset Control. Controls reset state of the Counter/Timer 0 (CTIMER0) peripheral. CTIMER0 provides versatile timing capabilities including PWM generation, input capture, output compare, and general-purpose timing functions. 計數器/定時器 0 重置控制，多功能計時外設 CTIMER0 Functions: 32-bit counter with programmable prescaler Multiple match registers for precise timing events PWM output generation with configurable duty cycles Input capture for measuring external signal timing Interrupt generation on match, capture, and overflow events 註 Reset Effects: Counter value resets to 0 All match registers cleared to default values PWM outputs return to inactive state Timer configuration registers reset to defaults All pending interrupts are cleared Initialization: // Configure CTIMER0 for PWM generation reset_ctrl.assert_reset(Control::CTIMER0); setup_ctimer0_clock_source(); reset_ctrl.release_reset(Control::CTIMER0); ctimer0_configure_pwm(frequency, duty_cycle);
Multi-Timer	Counter/Timer 1 Reset Control. Controls reset state of the Counter/Timer 1 (CTIMER1) peripheral. CTIMER1 provides identical functionality to CTIMER0, enabling multiple independent timing operations and complex timing sequence generation. 計數器/定時器 1 重置控制，獨立計時功能 Identical to CTIMER0: Independent 32-bit counter operation Separate match registers and PWM outputs Individual interrupt sources and configuration Can be synchronized with other timers for complex timing Coordination: // Synchronized reset of multiple timers reset_ctrl.assert_reset(Control::CTIMER0); reset_ctrl.assert_reset(Control::CTIMER1); configure_synchronized_timing(); reset_ctrl.release_reset(Control::CTIMER0); reset_ctrl.release_reset(Control::CTIMER1);
CTIMER2	Counter/Timer 2 Reset Control. Controls reset state of the Counter/Timer 2 (CTIMER2) peripheral. CTIMER2 provides additional timing capability for applications requiring multiple independent or coordinated timing functions. 計數器/定時器 2 重置控制，額外計時能力
Clock	Frequency Measurement Reset Control. Controls reset state of the Frequency Measurement (FREQME) peripheral. FREQME provides accurate measurement of clock frequencies using a reference clock, essential for clock monitoring and system diagnostics. 頻率測量重置控制，用於時脈頻率測量和診斷 FREQME Functions: Accurate frequency measurement using reference clock Multiple clock source selection for measurement Real-time clock monitoring and validation System clock integrity verification 註 Reset Effects: Measurement in progress is aborted Reference and target clock selections reset Measurement results registers cleared Monitoring: // Verify system clock frequency reset_ctrl.assert_reset(Control::FREQME); reset_ctrl.release_reset(Control::FREQME); uint32_t measured_freq = freqme_measure_clock(SYSTEM_CLOCK);
System	Micro Tick Timer 0 Reset Control. Controls reset state of the Micro Tick Timer 0 (UTICK0) peripheral. UTICK0 provides high-resolution timing capability optimized for system tick generation and precise time-base functions. 微秒滴答定時器 0 重置控制，高解析度系統時基 UTICK0 Functions: High-resolution system tick generation Low-power timer operation in sleep modes Precise timing for real-time applications System time-base and scheduling support 註 Reset Effects: Timer counter resets to initial value Tick interval configuration returns to default All pending tick interrupts are cleared Tick Setup: // Configure system tick timer reset_ctrl.assert_reset(Control::UTICK0); reset_ctrl.release_reset(Control::UTICK0); utick0_configure_systick(1000); // 1ms tick interval
DMA	Direct Memory Access Reset Control. Controls reset state of the Direct Memory Access (DMA) controller. DMA enables high-speed data transfer between memory and peripherals without CPU intervention, improving system performance and efficiency. 直接記憶體存取重置控制，高速資料傳輸控制器 DMA Functions: High-speed memory-to-memory and peripheral-to-memory transfers Multiple independent DMA channels with priority management Scatter-gather operation for complex transfer patterns Interrupt generation on transfer completion or error Bandwidth optimization for high-throughput applications 註 Reset Effects: All active DMA transfers are immediately terminated Channel descriptors and control registers reset to defaults Transfer queues are cleared and must be reprogrammed All pending DMA interrupts are cleared 警告 Reset Impact: Active data transfers will be corrupted if reset during operation Ensure all critical transfers complete before asserting reset May affect multiple peripherals that depend on DMA services Reinitialization: // Safely reset and reconfigure DMA dma_wait_for_transfers_complete(); reset_ctrl.assert_reset(Control::DMA); configure_dma_channels(); reset_ctrl.release_reset(Control::DMA);
Logic	AND-OR-Invert Logic 0 Reset Control. Controls reset state of the AND-OR-Invert Logic 0 (AOI0) peripheral. AOI0 provides configurable combinatorial logic functions that can be used for signal processing, event detection, and system control logic. AND-OR-反相邏輯 0 重置控制，可配置組合邏輯功能 AOI0 Functions: Configurable boolean logic operations (AND, OR, NOT combinations) Multiple input signal processing and event generation Real-time logic operations without CPU intervention Trigger generation for other peripherals based on logic conditions 註 Reset Effects: Logic function configurations return to default (typically pass-through) Input selections reset to default mappings Output states return to inactive/default levels Configuration: // Configure AOI for event detection reset_ctrl.assert_reset(Control::AOI0); reset_ctrl.release_reset(Control::AOI0); aoi0_configure_logic_function(input_mask, logic_operation);
Data	Cyclic Redundancy Check Reset Control. Controls reset state of the Cyclic Redundancy Check (CRC) engine. CRC provides hardware-accelerated error detection for data integrity verification in communication and storage applications. 循環冗餘檢查重置控制，硬體錯誤檢測引擎 CRC Functions: High-speed CRC calculation for data integrity verification Multiple CRC polynomial support (CRC-16, CRC-32, custom) Programmable seed values and bit/byte reversal options DMA integration for automatic data stream processing 註 Reset Effects: CRC calculation in progress is terminated Accumulator and result registers cleared Polynomial and configuration registers reset to defaults Integrity Check: // Initialize CRC for data verification reset_ctrl.assert_reset(Control::CRC); reset_ctrl.release_reset(Control::CRC); crc_configure_polynomial(CRC32_IEEE); uint32_t checksum = crc_calculate(data_buffer, length);
EIM	Error Injection Module Reset Control. Controls reset state of the Error Injection Module (EIM). EIM enables controlled error injection for system testing, fault tolerance validation, and safety-critical system verification. 錯誤注入模組重置控制，用於系統測試和安全驗證 EIM Functions: Controlled error injection into memory and peripheral accesses Single and multiple bit error generation for testing Error detection and correction system validation Safety-critical system fault tolerance verification 註 Reset Effects: All active error injection scenarios are disabled Error injection configuration registers cleared Test mode flags and error counters reset 警告 Safety Considerations: Only use in controlled test environments Disable error injection in production systems Verify error injection is inactive before system operation
ERM	Error Reporting Module Reset Control. Controls reset state of the Error Reporting Module (ERM). ERM provides comprehensive error logging and reporting capabilities for system diagnostics and fault analysis. 錯誤報告模組重置控制，綜合錯誤記錄和診斷 ERM Functions: Centralized error event collection and logging Error classification and priority management Fault analysis data collection and storage Integration with system safety and diagnostic functions 註 Reset Effects: Error log buffers and counters are cleared Error reporting configuration returns to defaults All pending error reports are lost 警告 Data Loss: Critical error information may be lost during reset Consider reading error logs before asserting reset Ensure error data is preserved if needed for analysis
I2C	Low Power I2C 0 Reset Control. Controls reset state of the Low Power Inter-Integrated Circuit 0 (LPI2C0) peripheral. LPI2C0 provides I2C communication capability optimized for low-power operation with advanced features for battery-powered and energy-efficient applications. 低功耗 I2C 0 重置控制，節能型串列通訊介面 LPI2C0 Functions: Standard I2C master and slave operation modes Low-power operation with reduced power consumption Multi-master support with bus arbitration Clock stretching and NACK handling DMA integration for efficient data transfer 註 Reset Effects: Bus interface returns to idle state All pending transactions are aborted Master/slave configuration reset to default Address match and filtering settings cleared Communication Setup: // Initialize LPI2C0 for sensor communication reset_ctrl.assert_reset(Control::LPI2C0); configure_i2c_pins_and_clocking(); reset_ctrl.release_reset(Control::LPI2C0); lpi2c0_initialize_master(100000); // 100kHz
SPI	Low Power SPI 0 Reset Control. Controls reset state of the Low Power Serial Peripheral Interface 0 (LPSPI0). LPSPI0 provides SPI communication with power optimization features for efficient data exchange in low-power applications. 低功耗 SPI 0 重置控制，節能型串列外設介面 LPSPI0 Functions: Full-duplex serial communication up to several MHz Master and slave operation modes Configurable frame size (4-32 bits) and protocols Low-power operation with clock gating DMA and interrupt-driven data transfer support 註 Reset Effects: SPI interface returns to idle state Transmit and receive buffers are cleared Clock polarity and phase settings reset Chip select configurations return to defaults Flash Communication: // Setup LPSPI0 for external flash memory reset_ctrl.assert_reset(Control::LPSPI0); configure_spi_pins_and_clocking(); reset_ctrl.release_reset(Control::LPSPI0); lpspi0_configure_master(8000000, SPI_MODE_0);
LPSPI1	Low Power SPI 1 Reset Control. Controls reset state of the Low Power Serial Peripheral Interface 1 (LPSPI1). LPSPI1 provides additional SPI communication capability for applications requiring multiple independent SPI interfaces. 低功耗 SPI 1 重置控制，額外的串列外設介面
Debug	Low Power UART 0 Reset Control. Controls reset state of the Low Power Universal Asynchronous Receiver-Transmitter 0 (LPUART0). LPUART0 provides serial communication optimized for low-power operation with advanced features for reliable data transmission. 低功耗通用非同步收發器 0 重置控制，節能型串列通訊 LPUART0 Functions: Asynchronous serial communication (UART protocol) Configurable baud rates and data formats Hardware flow control (RTS/CTS) support Low-power operation with wake-up capabilities Error detection (parity, framing, overrun) 註 Reset Effects: Serial interface returns to idle state Transmit and receive buffers cleared Baud rate and format settings reset All pending interrupts are cleared Console Setup: // Configure LPUART0 for debug output reset_ctrl.assert_reset(Control::LPUART0); configure_uart_pins(); reset_ctrl.release_reset(Control::LPUART0); lpuart0_configure(115200, UART_8N1);
LPUART1	Low Power UART 1 Reset Control. Controls reset state of the Low Power UART 1 (LPUART1). LPUART1 provides additional serial communication capability for applications requiring multiple UART interfaces. 低功耗通用非同步收發器 1 重置控制
LPUART2	Low Power UART 2 Reset Control. Controls reset state of the Low Power UART 2 (LPUART2). LPUART2 provides third UART interface for complex communication applications. 低功耗通用非同步收發器 2 重置控制
USB	USB 0 Controller Reset Control. Controls reset state of the Universal Serial Bus 0 (USB0) controller. USB0 provides high-speed USB communication capability for device and host applications with comprehensive USB protocol support. USB 0 控制器重置控制，高速USB通訊功能 USB0 Functions: USB 2.0 Full-Speed (12 Mbps) communication Device and host operation modes Multiple endpoints for complex USB devices USB protocol handling and enumeration support Power management and suspend/resume functionality 註 Reset Effects: USB controller returns to disconnected state All USB endpoints are disabled and cleared Device/host configuration registers reset USB PHY may require reinitialization 警告 USB Reset Considerations: Reset disconnects device from USB host May interrupt ongoing USB communications Host may need to re-enumerate device after reset Ensure proper USB cable handling during reset Device Setup: // Initialize USB0 as a device reset_ctrl.assert_reset(Control::USB0); configure_usb_pins_and_phy(); reset_ctrl.release_reset(Control::USB0); usb0_initialize_device_mode();
Motor	Quadrature Decoder 0 Reset Control. Controls reset state of the Quadrature Decoder 0 (QDC0) peripheral. QDC0 provides hardware decoding of quadrature encoder signals for motor control and position sensing applications. 正交解碼器 0 重置控制，馬達控制和位置感測 QDC0 Functions: Hardware quadrature signal decoding (Phase A/B) Position and velocity measurement Index signal support for absolute positioning Direction detection and counting modes Interrupt generation on position thresholds 註 Reset Effects: Position counters reset to zero or initial values Quadrature decoder configuration returns to defaults All pending interrupts and flags are cleared Position Control: // Setup QDC0 for motor encoder feedback reset_ctrl.assert_reset(Control::QDC0); configure_encoder_pins(); reset_ctrl.release_reset(Control::QDC0); qdc0_configure_quadrature_mode();
Motor	FlexPWM 0 Reset Control. Controls reset state of the Flexible Pulse Width Modulator 0 (FLEXPWM0). FLEXPWM0 provides advanced PWM generation capabilities for motor control, power conversion, and precision timing applications. 彈性脈衝寬度調變器 0 重置控制，先進PWM生成功能 FLEXPWM0 Functions: Multi-channel PWM generation with independent control Advanced motor control features (dead-time, complementary outputs) Fault protection and emergency shutdown capability Synchronized PWM generation across multiple channels Capture functionality for input signal measurement 註 Reset Effects: All PWM outputs return to inactive/safe state PWM counters and match registers cleared Fault protection settings reset to safe defaults Dead-time and complementary output configurations cleared 警告 Motor Control Safety: PWM outputs return to safe state during reset Ensure motor drivers are properly configured for safe reset state Consider emergency shutdown requirements during reset Control Setup: // Configure FLEXPWM0 for 3-phase motor control reset_ctrl.assert_reset(Control::FLEXPWM0); configure_motor_control_pins(); reset_ctrl.release_reset(Control::FLEXPWM0); flexpwm0_configure_3phase_motor_control();
OSTIMER0	OS Timer 0 Reset Control. Controls reset state of the Operating System Timer 0 (OSTIMER0). OSTIMER0 provides high-precision 64-bit timing capability for operating system scheduling and real-time applications. 作業系統定時器 0 重置控制，高精度64位元計時
Sensor	Analog-to-Digital Converter 0 Reset Control. Controls reset state of the Analog-to-Digital Converter 0 (ADC0). ADC0 provides high-resolution analog signal conversion for sensor interfacing and analog signal processing applications. 類比數位轉換器 0 重置控制，高解析度類比信號轉換 ADC0 Functions: High-resolution analog-to-digital conversion Multiple input channels with multiplexer Programmable gain and reference voltage selection Continuous and triggered conversion modes DMA integration for efficient data collection 註 Reset Effects: Conversion in progress is terminated Channel selection and configuration reset Calibration data may need to be restored All pending conversion results are lost Data Acquisition: // Initialize ADC0 for temperature sensor reset_ctrl.assert_reset(Control::ADC0); configure_adc_pins_and_references(); reset_ctrl.release_reset(Control::ADC0); adc0_calibrate_and_configure();
Threshold	Comparator 1 Reset Control. Controls reset state of the Analog Comparator 1 (CMP1). CMP1 provides high-speed analog signal comparison for threshold detection and analog signal processing applications. 比較器 1 重置控制，高速類比信號比較 CMP1 Functions: High-speed analog voltage comparison Programmable reference voltage and hysteresis Output inversion and filtering options Interrupt generation on comparison state changes Low-power operation modes 註 Reset Effects: Comparator output returns to default state Reference voltage and threshold settings cleared All pending interrupts are cleared Detection: // Configure CMP1 for overvoltage detection reset_ctrl.assert_reset(Control::CMP1); reset_ctrl.release_reset(Control::CMP1); cmp1_configure_threshold_detection(overvoltage_level);
Pin	PORT 0 Reset Control. Controls reset state of the PORT 0 peripheral controller. PORT 0 manages pin multiplexing, electrical characteristics, and configuration for the first group of GPIO pins. 埠 0 重置控制，管理第一組GPIO引腳配置 PORT0 Functions: Pin multiplexer control and function selection Electrical characteristics configuration (drive strength, pull resistors) Digital filter and slew rate control Pin interrupt and event configuration 註 Reset Effects: All pins return to default function (typically GPIO) Electrical characteristics reset to default values Pin interrupts and filters are disabled Configuration: // Reconfigure PORT0 pins for specific application reset_ctrl.assert_reset(Control::PORT0); reset_ctrl.release_reset(Control::PORT0); configure_port0_pin_functions();
PORT1	PORT 1 Reset Control. Controls reset state of the PORT 1 peripheral controller. PORT 1 manages the second group of GPIO pins with identical functionality to PORT 0. 埠 1 重置控制，管理第二組GPIO引腳配置
PORT2	PORT 2 Reset Control. Controls reset state of the PORT 2 peripheral controller. PORT 2 manages the third group of GPIO pins with identical functionality to other PORT peripherals. 埠 2 重置控制，管理第三組GPIO引腳配置
PORT3	PORT 3 Reset Control. Controls reset state of the PORT 3 peripheral controller. PORT 3 manages the fourth group of GPIO pins. Note the encoding uses register 1 (bit 8 set) with bit position 0. 埠 3 重置控制，管理第四組GPIO引腳配置 註 Register Encoding: Uses reset control register 1 (indicated by bit 8 = 1) Bit position 0 within register 1 This demonstrates the register indexing scheme used in the enum
ATX0	ATX 0 Reset Control. Controls reset state of the ATX 0 peripheral. ATX0 provides advanced timing and trigger capabilities for complex system coordination and event management. ATX 0 重置控制，先進計時和觸發功能 ATX0 Functions: Advanced timing and trigger generation Multi-channel event coordination Complex timing sequence management Integration with other timing peripherals 註 Reset Effects: All timing sequences and triggers are stopped Event coordination configurations cleared Output states return to inactive levels
GPIO	GPIO 0 Reset Control. Controls reset state of the General Purpose Input/Output 0 (GPIO0) controller. GPIO0 provides direct digital I/O control for the first bank of GPIO pins. 通用輸入輸出 0 重置控制，第一組GPIO直接數位控制 GPIO0 Functions: Digital input and output control Individual pin direction and state control Input/output data register management Pin state reading and writing 註 Reset Effects: All GPIO pins configured as inputs (high impedance) Output data registers cleared to 0 Direction registers reset to input mode Initialization: // Initialize GPIO0 for digital I/O reset_ctrl.assert_reset(Control::GPIO0); reset_ctrl.release_reset(Control::GPIO0); gpio0_configure_pins(pin_mask, directions);
GPIO1	GPIO 1 Reset Control. Controls reset state of the GPIO 1 controller. GPIO1 provides digital I/O control for the second bank of GPIO pins. 通用輸入輸出 1 重置控制，第二組GPIO控制
GPIO2	GPIO 2 Reset Control. Controls reset state of the GPIO 2 controller. GPIO2 provides digital I/O control for the third bank of GPIO pins. 通用輸入輸出 2 重置控制，第三組GPIO控制
GPIO3	GPIO 3 Reset Control. Controls reset state of the GPIO 3 controller. GPIO3 provides digital I/O control for the fourth bank of GPIO pins. 通用輸入輸出 3 重置控制，第四組GPIO控制
Reset	No Reset Control Available. Indicates that reset control is not available for a particular peripheral or system component. This value (0xFFFF) serves as a sentinel to identify peripherals that cannot be individually reset through the reset controller. 無重置控制可用，表示特定外設無法單獨重置 Usage: Used as a placeholder for peripherals without reset control Enables uniform reset control interface even for non-resettable components Allows software to detect unavailable reset functionality Prevents accidental reset attempts on unsupported peripherals 註 Implementation Considerations: Reset controller should check for this value and handle appropriately May indicate peripherals that are reset only during system reset Some critical system components may use this to prevent accidental reset Could represent peripherals that are always active or have special reset requirements Availability Check: bool can_reset_peripheral(Control peripheral) { return peripheral != Control::NOT_AVAIL; } void safe_reset_peripheral(Control peripheral) { if (can_reset_peripheral(peripheral)) { reset_ctrl.assert_reset(peripheral); reset_ctrl.release_reset(peripheral); } else { // Handle non-resettable peripheral handle_non_resettable_peripheral(peripheral); } } 警告 Do Not Use for Reset Operations: This value should never be used in actual reset control operations Always check for this value before attempting reset May indicate system-critical components that should not be reset