mcxa153::chip::lpadc 命名空間(Namespace)參考文件

複合項目
class	LPADC
	MCXA153 低功耗類比數位轉換器 (Low Power Analog-to-Digital Converter) 靜態工具類別 更多...
struct	Register
	LPADC 週邊暫存器存取層 更多...

列舉型態
enum struct	Count : unsigned int {   TCTRL = 4U , GCC = 1U , GCR = 1U , CMDL = 7U ,   CMDH = 7U , CV = 15U }
	LPADC (Low Power Analog-to-Digital Converter) 計數器枚舉 更多...
enum struct	Mask : unsigned int {   VERID_RES = 0x1U , VERID_DIFFEN = 0x2U , VERID_MVI = 0x8U , VERID_CSW = 0x70U ,   VERID_VR1RNGI = 0x100U , VERID_IADCKI = 0x200U , VERID_CALOFSI = 0x400U , VERID_NUM_SEC = 0x800U ,   VERID_NUM_FIFO = 0x7000U , VERID_MINOR = 0xFF0000U , VERID_MAJOR = 0xFF000000U , PARAM_TRIG_NUM = 0xFFU ,   PARAM_FIFOSIZE = 0xFF00U , PARAM_CV_NUM = 0xFF0000U , PARAM_CMD_NUM = 0xFF000000U , CTRL_ADCEN = 0x1U ,   CTRL_RST = 0x2U , CTRL_DOZEN = 0x4U , CTRL_CAL_REQ = 0x8U , CTRL_CALOFS = 0x10U ,   CTRL_CALHS = 0x40U , CTRL_RSTFIFO0 = 0x100U , CTRL_CAL_AVGS = 0xF0000U , STAT_RDY0 = 0x1U ,   STAT_FOF0 = 0x2U , STAT_TEXC_INT = 0x100U , STAT_TCOMP_INT = 0x200U , STAT_CAL_RDY = 0x400U ,   STAT_ACTIVE = 0x800U , STAT_TRGACT = 0x30000U , STAT_CMDACT = 0x7000000U , IE_FWMIE0 = 0x1U ,   IE_FOFIE0 = 0x2U , IE_TEXC_IE = 0x100U , IE_TCOMP_IE = 0xF0000U , DE_FWMDE0 = 0x1U ,   CFG_TPRICTRL = 0x3U , CFG_PWRSEL = 0x20U , CFG_REFSEL = 0xC0U , CFG_TRES = 0x100U ,   CFG_TCMDRES = 0x200U , CFG_HPT_EXDI = 0x400U , CFG_PUDLY = 0xFF0000U , CFG_PWREN = 0x10000000U ,   PAUSE_PAUSEDLY = 0x1FFU , PAUSE_PAUSEEN = 0x80000000U , SWTRIG_SWT0 = 0x1U , SWTRIG_SWT1 = 0x2U ,   SWTRIG_SWT2 = 0x4U , SWTRIG_SWT3 = 0x8U , TSTAT_TEXC_NUM = 0xFU , TSTAT_TCOMP_FLAG = 0xF0000U ,   OFSTRIM_OFSTRIM = 0x3FFU , HSTRIM_HSTRIM = 0x1FU , TCTRL_HTEN = 0x1U , TCTRL_TPRI = 0x300U ,   TCTRL_RSYNC = 0x8000U , TCTRL_TDLY = 0xF0000U , TCTRL_TSYNC = 0x800000U , TCTRL_TCMD = 0x7000000U ,   FCTRL_FCOUNT = 0xFU , FCTRL_FWMARK = 0x70000U , GCC_GAIN_CAL = 0xFFFFU , GCC_RDY = 0x1000000U ,   GCR_GCALR = 0x1FFFFU , GCR_RDY = 0x1000000U , CMDL_ADCH = 0x1FU , CMDL_CTYPE = 0x60U ,   CMDL_MODE = 0x80U , CMDH - Command High Buffer Register , CMDH_CMPEN = 0x3U , CMDH_WAIT_TRIG = 0x4U ,   CMDH_LWI = 0x80U , CMDH_STS = 0x700U , CMDH_AVGS = 0xF000U , CMDH_LOOP = 0xF0000U ,   CMDH_NEXT = 0x7000000U , CV_CVL = 0xFFFFU , CV_CVH = 0xFFFF0000U , RESFIFO_D = 0xFFFFU ,   RESFIFO_TSRC = 0x30000U , RESFIFO_LOOPCNT = 0xF00000U , RESFIFO_CMDSRC = 0x7000000U , RESFIFO_VALID = 0x80000000U ,   CAL_GAR0_CAL_GAR_VAL = 0xFFFFU , CAL_GAR1_CAL_GAR_VAL = 0xFFFFU , CAL_GAR2_CAL_GAR_VAL = 0xFFFFU , CAL_GAR3_CAL_GAR_VAL = 0xFFFFU ,   CAL_GAR4_CAL_GAR_VAL = 0xFFFFU , CAL_GAR5_CAL_GAR_VAL = 0xFFFFU , CAL_GAR6_CAL_GAR_VAL = 0xFFFFU , CAL_GAR7_CAL_GAR_VAL = 0xFFFFU ,   CAL_GAR8_CAL_GAR_VAL = 0xFFFFU , CAL_GAR9_CAL_GAR_VAL = 0xFFFFU , CAL_GAR10_CAL_GAR_VAL = 0xFFFFU , CAL_GAR11_CAL_GAR_VAL = 0xFFFFU ,   CAL_GAR12_CAL_GAR_VAL = 0xFFFFU , CAL_GAR13_CAL_GAR_VAL = 0xFFFFU , CAL_GAR14_CAL_GAR_VAL = 0xFFFFU , CAL_GAR15_CAL_GAR_VAL = 0xFFFFU ,   CAL_GAR16_CAL_GAR_VAL = 0xFFFFU , CAL_GAR17_CAL_GAR_VAL = 0xFFFFU , CAL_GAR18_CAL_GAR_VAL = 0xFFFFU , CAL_GAR19_CAL_GAR_VAL = 0xFFFFU ,   CAL_GAR20_CAL_GAR_VAL = 0xFFFFU , CAL_GAR21_CAL_GAR_VAL = 0xFFFFU , CAL_GAR22_CAL_GAR_VAL = 0xFFFFU , CAL_GAR23_CAL_GAR_VAL = 0xFFFFU ,   CAL_GAR24_CAL_GAR_VAL = 0xFFFFU , CAL_GAR25_CAL_GAR_VAL = 0xFFFFU , CAL_GAR26_CAL_GAR_VAL = 0xFFFFU , CAL_GAR27_CAL_GAR_VAL = 0xFFFFU ,   CAL_GAR28_CAL_GAR_VAL = 0xFFFFU , CAL_GAR29_CAL_GAR_VAL = 0xFFFFU , CAL_GAR30_CAL_GAR_VAL = 0xFFFFU , CAL_GAR31_CAL_GAR_VAL = 0xFFFFU ,   CAL_GAR32_CAL_GAR_VAL = 0xFFFFU , CFG2_JLEFT = 0x100U , CFG2_HS = 0x200U , CFG2_HSEXTRA = 0x400U ,   CFG2_TUNE = 0x3000U }
	LPADC Shift - Register Bit Mask. 更多...
enum struct	Shift : unsigned int {   VERID_RES = 0U , VERID_DIFFEN = 1U , VERID_MVI = 3U , VERID_CSW = 4U ,   VERID_VR1RNGI = 8U , VERID_IADCKI = 9U , VERID_CALOFSI = 10U , VERID_NUM_SEC = 11U ,   VERID_NUM_FIFO = 12U , VERID_MINOR = 16U , VERID_MAJOR = 24U , PARAM_TRIG_NUM = 0U ,   PARAM_FIFOSIZE = 8U , PARAM_CV_NUM = 16U , PARAM_CMD_NUM = 24U , CTRL_ADCEN = 0U ,   CTRL_RST = 1U , CTRL_DOZEN = 2U , CTRL_CAL_REQ = 3U , CTRL_CALOFS = 4U ,   CTRL_CALHS = 6U , CTRL_RSTFIFO0 = 8U , CTRL_CAL_AVGS = 16U , STAT_RDY0 = 0U ,   STAT_FOF0 = 1U , STAT_TEXC_INT = 8U , STAT_TCOMP_INT = 9U , STAT_CAL_RDY = 10U ,   STAT_ACTIVE = 11U , STAT_TRGACT = 16U , STAT_CMDACT = 24U , IE_FWMIE0 = 0U ,   IE_FOFIE0 = 1U , IE_TEXC_IE = 8U , IE_TCOMP_IE = 16U , DE_FWMDE0 = 0U ,   CFG_TPRICTRL = 0U , CFG_PWRSEL = 5U , CFG_REFSEL = 6U , CFG_TRES = 8U ,   CFG_TCMDRES = 9U , CFG_HPT_EXDI = 10U , CFG_PUDLY = 16U , CFG_PWREN = 28U ,   PAUSE_PAUSEDLY = 0U , PAUSE_PAUSEEN = 31U , SWTRIG_SWT0 = 0U , SWTRIG_SWT1 = 1U ,   SWTRIG_SWT2 = 2U , SWTRIG_SWT3 = 3U , TSTAT_TEXC_NUM = 0U , TSTAT_TCOMP_FLAG = 16U ,   OFSTRIM_OFSTRIM = 0U , HSTRIM_HSTRIM = 0U , TCTRL_HTEN = 0U , TCTRL_TPRI = 8U ,   TCTRL_RSYNC = 15U , TCTRL_TDLY = 16U , TCTRL_TSYNC = 23U , TCTRL_TCMD = 24U ,   FCTRL_FCOUNT = 0U , FCTRL_FWMARK = 16U , GCC_GAIN_CAL = 0U , GCC_RDY = 24U ,   GCR_GCALR = 0U , GCR_RDY = 24U , CMDL_ADCH = 0U , CMDL_CTYPE = 5U ,   CMDL_MODE = 7U , CMDH - Command High Buffer Register , CMDH_CMPEN = 0U , CMDH_WAIT_TRIG = 2U ,   CMDH_LWI = 7U , CMDH_STS = 8U , CMDH_AVGS = 12U , CMDH_LOOP = 16U ,   CMDH_NEXT = 24U , CV_CVL = 0U , CV_CVH = 16U , RESFIFO_D = 0U ,   RESFIFO_TSRC = 16U , RESFIFO_LOOPCNT = 20U , RESFIFO_CMDSRC = 24U , RESFIFO_VALID = 31U ,   CAL_GAR0_CAL_GAR_VAL = 0U , CAL_GAR1_CAL_GAR_VAL = 0U , CAL_GAR2_CAL_GAR_VAL = 0U , CAL_GAR3_CAL_GAR_VAL = 0U ,   CAL_GAR4_CAL_GAR_VAL = 0U , CAL_GAR5_CAL_GAR_VAL = 0U , CAL_GAR6_CAL_GAR_VAL = 0U , CAL_GAR7_CAL_GAR_VAL = 0U ,   CAL_GAR8_CAL_GAR_VAL = 0U , CAL_GAR9_CAL_GAR_VAL = 0U , CAL_GAR10_CAL_GAR_VAL = 0U , CAL_GAR11_CAL_GAR_VAL = 0U ,   CAL_GAR12_CAL_GAR_VAL = 0U , CAL_GAR13_CAL_GAR_VAL = 0U , CAL_GAR14_CAL_GAR_VAL = 0U , CAL_GAR15_CAL_GAR_VAL = 0U ,   CAL_GAR16_CAL_GAR_VAL = 0U , CAL_GAR17_CAL_GAR_VAL = 0U , CAL_GAR18_CAL_GAR_VAL = 0U , CAL_GAR19_CAL_GAR_VAL = 0U ,   CAL_GAR20_CAL_GAR_VAL = 0U , CAL_GAR21_CAL_GAR_VAL = 0U , CAL_GAR22_CAL_GAR_VAL = 0U , CAL_GAR23_CAL_GAR_VAL = 0U ,   CAL_GAR24_CAL_GAR_VAL = 0U , CAL_GAR25_CAL_GAR_VAL = 0U , CAL_GAR26_CAL_GAR_VAL = 0U , CAL_GAR27_CAL_GAR_VAL = 0U ,   CAL_GAR28_CAL_GAR_VAL = 0U , CAL_GAR29_CAL_GAR_VAL = 0U , CAL_GAR30_CAL_GAR_VAL = 0U , CAL_GAR31_CAL_GAR_VAL = 0U ,   CAL_GAR32_CAL_GAR_VAL = 0U , CFG2_JLEFT = 8U , CFG2_HS = 9U , CFG2_HSEXTRA = 10U ,   CFG2_TUNE = 12U }
	LPADC Shift - Register Bit Shift Positions. 更多...

函式
constexpr unsigned int	operator+ (Count e)
constexpr unsigned int	operator+ (Mask e)
constexpr unsigned int	operator+ (Shift e)
	Shift Operator - Convert Shift Enum to Integer.

變數
Register &	LPADC0

詳細描述

Copyright (c) 2020 ZxyKira All rights reserved.

SPDX-License-Identifier: MIT

列舉型態說明文件

Count

enum struct mcxa153::chip::lpadc::Count : unsigned int

strong

LPADC (Low Power Analog-to-Digital Converter) 計數器枚舉

此枚舉定義了 LPADC 週邊的各種計數器和暫存器的數量。 每個枚舉值代表一個特定的計數器或暫存器的數量。

自

v1.0.0

Mask

enum struct mcxa153::chip::lpadc::Mask : unsigned int

strong

LPADC Shift - Register Bit Mask.

Defines bit Mask for LPADC (Low Power Digital Analog Convertor) registers 定義LPADC寄存器的位元遮罩

自

v1.0.0

列舉值
VERID_RES	VERID - RES. Version ID Register - Resolution [0b0] Up to 12-bit single ended resolution supported (and 13-bit differential resolution if VERID[DIFFEN] = 1b). [0b1] Up to 16-bit single ended resolution supported (and 16-bit differential resolution if VERID[DIFFEN] = 1b).
VERID_DIFFEN	VERID - DIFFEN. Version ID Register - Differential Supported [0b0] Differential operation not supported. [0b1] Differential operation supported.
VERID_MVI	VERID - MVI. Version ID Register - Multi Vref Implemented [0b0] Single voltage reference high (VREFH) input supported. [0b1] Multiple voltage reference high (VREFH) inputs supported.
VERID_CSW	VERID - CSW. Version ID Register - Channel Scale Width [0b000] Channel scaling not supported. [0b001] Channel scaling supported. 1-bit CSCALE control field. [0b110] Channel scaling supported. 6-bit CSCALE control field.
VERID_VR1RNGI	VERID - VR1RNGI. Version ID Register - Voltage Reference 1 Range Control Bit Implemented [0b0] Range control not required. CFG[VREF1RNG] is not implemented. [0b1] Range control required. CFG[VREF1RNG] is implemented.
VERID_IADCKI	VERID - IADCKI. Version ID Register - Internal ADC Clock Implemented [0b0] Internal clock source not implemented. [0b1] Internal clock source (and CFG[ADCKEN]) implemented.
VERID_CALOFSI	VERID - CALOFSI. Version ID Register - Calibration Function Implemented [0b0] Calibration Not Implemented. [0b1] Calibration Implemented.
VERID_NUM_SEC	VERID - NUM_SEC. Version ID Register - Number of Single Ended Outputs Supported [0b0] This design supports one single ended conversion at a time. [0b1] This design supports two simultaneous single ended conversions.
VERID_NUM_FIFO	VERID - NUM_FIFO. Version ID Register - Number of FIFOs [0b000] N/A [0b001] This design supports one result FIFO. [0b010] This design supports two result FIFOs. [0b011] This design supports three result FIFOs. [0b100] This design supports four result FIFOs.
VERID_MINOR	VERID - MINOR. Version ID Register - Minor Version Number
VERID_MAJOR	VERID - MAJOR -. Version ID Register - Major Version Number
PARAM_TRIG_NUM	PARAM - TRIG_NUM. Parameter Register - Trigger Number
PARAM_FIFOSIZE	PARAM - FIFOSIZE. Parameter Register - Result FIFO Depth [0b00000001] Result FIFO depth = 2 dataword. [0b00000100] Result FIFO depth = 4 datawords. [0b00001000] Result FIFO depth = 8 datawords. [0b00010000] Result FIFO depth = 16 datawords. [0b00100000] Result FIFO depth = 32 datawords. [0b01000000] Result FIFO depth = 64 datawords.
PARAM_CV_NUM	PARAM - CV_NUM. Parameter Register - Compare Value Number
PARAM_CMD_NUM	PARAM - CMD_NUM. Parameter Register - Command Buffer Number
CTRL_ADCEN	CTRL - ADCEN. Control Register - ADC Enable [0b0] ADC is disabled. [0b1] ADC is enabled.
CTRL_RST	CTRL - RST. Control Register - Software Reset [0b0] ADC logic is not reset. [0b1] ADC logic is reset.
CTRL_DOZEN	CTRL - DOZEN. Control Register - Doze Enable [0b0] ADC is enabled in low power mode. [0b1] ADC is disabled in low power mode.
CTRL_CAL_REQ	CTRL - CAL_REQ. Control Register - Auto-Calibration Request [0b0] No request for hardware calibration has been made [0b1] A request for hardware calibration has been made
CTRL_CALOFS	CTRL - CALOFS. Control Register - Offset Calibration Request [0b0] No request for offset calibration has been made [0b1] Request for offset calibration function
CTRL_CALHS	CTRL - CALHS. Control Register - High Speed Mode Trim Request [0b0] No request for high speed mode trim has been made [0b1] Request for high speed mode trim has been made
CTRL_RSTFIFO0	CTRL - RSTFIFO0. Control Register - Reset FIFO 0 [0b0] No effect. [0b1] FIFO 0 is reset.
CTRL_CAL_AVGS	CTRL - CAL_AVGS. Control Register - Auto-Calibration Averages [0b0000] Single conversion. [0b0001] 2 conversions averaged. [0b0010] 4 conversions averaged. [0b0011] 8 conversions averaged. [0b0100] 16 conversions averaged. [0b0101] 32 conversions averaged. [0b0110] 64 conversions averaged. [0b0111] 128 conversions averaged. [0b1000] 256 conversions averaged. [0b1001] 512 conversions averaged. [0b1010] 1024 conversions averaged.
STAT_RDY0	STAT - RDY0. Status Register - Result FIFO 0 Ready Flag [0b0] Result FIFO 0 data level not above watermark level. [0b1] Result FIFO 0 holding data above watermark level.
STAT_FOF0	STAT - FOF0. Status Register - Result FIFO 0 Overflow Flag [0b0] No result FIFO 0 overflow has occurred since the last time the flag was cleared. [0b1] At least one result FIFO 0 overflow has occurred since the last time the flag was cleared.
STAT_TEXC_INT	STAT - TEXC_INT. Status Register - Interrupt Flag For High Priority Trigger Exception [0b0] No trigger exceptions have occurred. [0b1] A trigger exception has occurred and is pending acknowledgement.
STAT_TCOMP_INT	STAT - TCOMP_INT. Status Register - Interrupt Flag For Trigger Completion [0b0] Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion. [0b1] Trigger sequence has been completed and all data is stored in the associated FIFO.
STAT_CAL_RDY	STAT - CAL_RDY. Status Register - Calibration Ready [0b0] Calibration is incomplete or hasn't been ran. [0b1] The ADC is calibrated.
STAT_ACTIVE	STAT - ACTIVE. Status Register - ADC Active [0b0] The ADC is IDLE. There are no pending triggers to service and no active commands are being processed. [0b1] The ADC is processing a conversion, running through the power up delay, or servicing a trigger.
STAT_TRGACT	STAT - TRGACT. Status Register - Trigger Active [0b00] Command (sequence) associated with Trigger 0 currently being executed. [0b01] Command (sequence) associated with Trigger 1 currently being executed. [0b10] Command (sequence) associated with Trigger 2 currently being executed. [0b11] Command (sequence) associated with Trigger 3 currently being executed.
STAT_CMDACT	STAT - CMDACT. Status Register - Command Active [0b000] No command is currently in progress. [0b001] Command 1 currently being executed. [0b010] Command 2 currently being executed. [0b011-0b111] Associated command number is currently being executed.
IE_FWMIE0	IE - FWMIE0. Interrupt Enable Register - FIFO 0 Watermark Interrupt Enable [0b0] FIFO 0 watermark interrupts are not enabled. [0b1] FIFO 0 watermark interrupts are enabled.
IE_FOFIE0	IE - FOFIE0. Interrupt Enable Register - Result FIFO 0 Overflow Interrupt Enable [0b0] FIFO 0 overflow interrupts are not enabled. [0b1] FIFO 0 overflow interrupts are enabled.
IE_TEXC_IE	IE - TEXC_IE. Interrupt Enable Register - Trigger Exception Interrupt Enable [0b0] Trigger exception interrupts are disabled. [0b1] Trigger exception interrupts are enabled.
IE_TCOMP_IE	IE - TCOMP_IE. Interrupt Enable Register - Trigger Completion Interrupt Enable [0b0000] Trigger completion interrupts are disabled. [0b0001] Trigger completion interrupts are enabled for trigger source 0 only. [0b0010] Trigger completion interrupts are enabled for trigger source 1 only. [0b0011-0b1110] Associated trigger completion interrupts are enabled. [0b1111] Trigger completion interrupts are enabled for every trigger source.
DE_FWMDE0	DE - FWMDE0. DMA Enable Register - FIFO 0 Watermark DMA Enable [0b0] DMA request disabled. [0b1] DMA request enabled.
CFG_TPRICTRL	CFG - TPRICTRL. Configuration Register - ADC Trigger Priority Control [0b00] If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started. [0b01] If a higher priority trigger is received during command processing, the current command is stopped after completing the current conversion. If averaging is enabled, the averaging loop will be completed. However, CMDHa[LOOP] will be ignored and the higher priority trigger will be serviced. [0b10] If a higher priority trigger is received during command processing, the current command will be completed (averaging, looping, compare) before servicing the higher priority trigger. [0b11]
CFG_PWRSEL	CFG - PWRSEL. Configuration Register - Power Configuration Select [0b0] Low power [0b1] High power
CFG_REFSEL	CFG - REFSEL. Configuration Register - Voltage Reference Selection [0b00] (Default) Option 1 setting. [0b01] Option 2 setting. [0b10] Option 3 setting. [0b11] Reserved
CFG_TRES	CFG - TRES. Configuration Register - Trigger Resume Enable [0b0] Trigger sequences interrupted by a high priority trigger exception are not automatically resumed or restarted. [0b1] Trigger sequences interrupted by a high priority trigger exception are automatically resumed or restarted.
CFG_TCMDRES	CFG - TCMDRES. Configuration Register - Trigger Command Resume [0b0] Trigger sequences interrupted by a high priority trigger exception is automatically restarted. [0b1] Trigger sequences interrupted by a high priority trigger exception is resumed from the command executing before the exception.
CFG_HPT_EXDI	CFG - HPT_EXDI. Configuration Register - High Priority Trigger Exception Disable [0b0] High priority trigger exceptions are enabled. [0b1] High priority trigger exceptions are disabled.
CFG_PUDLY	CFG - PUDLY - Power Up Delay.
CFG_PWREN	CFG - PWREN. Configuration Register - ADC Analog Pre-Enable [0b0] ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays. [0b1] ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost of higher DC current consumption). Note that a single power up delay (CFG[PUDLY]) is executed immediately once PWREN is set, and any detected trigger does not begin ADC operation until the power up delay time has passed. After this initial delay expires the analog remains pre-enabled and no additional delays are executed.
PAUSE_PAUSEDLY	PAUSE - PAUSEDLY. Pause Register - Pause Delay
PAUSE_PAUSEEN	PAUSE - PAUSEEN. Pause Register - PAUSE Option Enable [0b0] Pause operation disabled [0b1] Pause operation enabled
SWTRIG_SWT0	SWTRIG - SWT0. Software Trigger Register - Software Trigger 0 Event [0b0] No trigger 0 event generated. [0b1] Trigger 0 event generated.
SWTRIG_SWT1	SWTRIG - SWT1. Software Trigger Register - Software Trigger 1 Event [0b0] No trigger 1 event generated. [0b1] Trigger 1 event generated.
SWTRIG_SWT2	SWTRIG - SWT2. Software Trigger Register - Software Trigger 2 Event [0b0] No trigger 2 event generated. [0b1] Trigger 2 event generated.
SWTRIG_SWT3	SWTRIG - SWT3. Software Trigger Register - Software Trigger 3 Event [0b0] No trigger 3 event generated. [0b1] Trigger 3 event generated.
TSTAT_TEXC_NUM	TSTAT - TEXC_NUM. Trigger Status Register - Trigger Exception Number [0b0000] No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1. [0b0001] Trigger 0 has been interrupted by a high priority exception. [0b0010] Trigger 1 has been interrupted by a high priority exception. [0b0011-0b1110] Associated trigger sequence has interrupted by a high priority exception. [0b1111] Every trigger sequence has been interrupted by a high priority exception.
TSTAT_TCOMP_FLAG	TSTAT - TCOMP_FLAG. Trigger Status Register - Trigger Completion Flag [0b0000] No triggers have been completed. Trigger completion interrupts are disabled. [0b0001] Trigger 0 has been completed and trigger 0 has enabled completion interrupts. [0b0010] Trigger 1 has been completed and trigger 1 has enabled completion interrupts. [0b0011-0b1110] Associated trigger sequence has completed and has enabled completion interrupts. [0b1111] Every trigger sequence has been completed and every trigger has enabled completion interrupts.
OFSTRIM_OFSTRIM	OFSTRIM - OFSTRIM. Offset Trim Register - Trim for Offset
HSTRIM_HSTRIM	HSTRIM - HSTRIM. High Speed Trim Register - Trim for High Speed Conversions
TCTRL_HTEN	TCTRL - HTEN. Trigger Control Register - Trigger Enable [0b0] Hardware trigger source disabled [0b1] Hardware trigger source enabled
TCTRL_TPRI	TCTRL - TPRI. Trigger Control Register - Trigger Priority Setting [0b00] Set to highest priority, Level 1 [0b01-0b10] Set to corresponding priority level [0b11] Set to lowest priority, Level 4
TCTRL_RSYNC	TCTRL - RSYNC. Trigger Control Register - Trigger Resync
TCTRL_TDLY	TCTRL - TDLY. Trigger Control Register - Trigger Delay Select
TCTRL_TSYNC	TCTRL - TSYNC. Trigger Control Register - Trigger Synchronous Select
TCTRL_TCMD	TCTRL - TCMD. Trigger Control Register - Trigger Command Select [0b000] Not a valid selection from the command buffer. Trigger event is ignored. [0b001] CMD1 is executed [0b010-0b110] Corresponding CMD is executed [0b111] CMD7 is executed
FCTRL_FCOUNT	FCTRL - FCOUNT. FIFO Control Register - Result FIFO Counter
FCTRL_FWMARK	FCTRL - FWMARK. FIFO Control Register - Watermark Level Selection
GCC_GAIN_CAL	GCC - GAIN_CAL. Gain Calibration Control - Gain Calibration Value
GCC_RDY	GCC - RDY. Gain Calibration Control - Gain Calibration Value Valid [0b0] The GAIN_CAL value is invalid. Run the hardware calibration routine for this value to be set. [0b1] The GAIN_CAL value is valid. GAIN_CAL should be used by software to derive GCRa[GCALR].
GCR_GCALR	GCR - GCALR. Gain Calculation Result - Gain Calculation Result
GCR_RDY	GCR - RDY. Gain Calculation Result - Gain Calculation Ready [0b0] The GCALR value is invalid. [0b1] The GCALR value is valid.
CMDL_ADCH	CMDL - ADCH. Command Low Buffer Register - Input Channel Select [0b00000] Select CH0A. [0b00001] Select CH1A. [0b00010] Select CH2A. [0b00011] Select CH3A. [0b00100-0b11101] Select corresponding channel CHnA. [0b11110] Select CH30A. [0b11111] Select CH31A.
CMDL_CTYPE	CMDL - CTYPE. Command Low Buffer Register - Conversion Type [0b00] Single-Ended Mode. Only A side channel is converted. [0b01-0b11] Reserved.
CMDL_MODE	CMDL - MODE. Command Low Buffer Register - Select Resolution of Conversions [0b0] Standard resolution. Single-ended 12-bit conversion. [0b1] High resolution. Single-ended 16-bit conversion.
CMDH_CMPEN	CMDH - CMPEN. Command High Buffer Register - Compare Function Enable [0b00] Compare disabled. [0b01] Reserved [0b10] Compare enabled. Store on true. [0b11] Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.
CMDH_WAIT_TRIG	CMDH - WAIT_TRIG. Command High Buffer Register - Wait for Trigger Assertion before Execution. [0b0] This command will be automatically executed. [0b1] The active trigger must be asserted again before executing this command.
CMDH_LWI	CMDH - LWI. Command High Buffer Register - Loop with Increment [0b0] Auto channel increment disabled [0b1] Auto channel increment enabled
CMDH_STS	CMDH - STS. Command High Buffer Register - Sample Time Select [0b000] Minimum sample time of 3.5 ADCK cycles. [0b001] 3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time. [0b010] 3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time. [0b011] 3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time. [0b100] 3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time. [0b101] 3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time. [0b110] 3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time. [0b111] 3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time.
CMDH_AVGS	CMDH - AVGS. Command High Buffer Register - Hardware Average Select [0b0000] Single conversion. [0b0001] 2 conversions averaged. [0b0010] 4 conversions averaged. [0b0011] 8 conversions averaged. [0b0100] 16 conversions averaged. [0b0101] 32 conversions averaged. [0b0110] 64 conversions averaged. [0b0111] 128 conversions averaged. [0b1000] 256 conversions averaged. [0b1001] 512 conversions averaged. [0b1010] 1024 conversions averaged.
CMDH_LOOP	CMDH - LOOP. Command High Buffer Register - Loop Count Select [0b0000] Looping not enabled. Command executes 1 time. [0b0001] Loop 1 time. Command executes 2 times. [0b0010] Loop 2 times. Command executes 3 times. [0b0011-0b1110] Loop corresponding number of times. Command executes LOOP+1 times. [0b1111] Loop 15 times. Command executes 16 times.
CMDH_NEXT	CMDH - NEXT. Command High Buffer Register - Next Command Select [0b000] No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. [0b001] Select CMD1 command buffer register as next command. [0b010-0b110] Select corresponding CMD command buffer register as next command [0b111] Select CMD7 command buffer register as next command.
CV_CVL	CV - CVL. Compare Value Register - Compare Value Low
CV_CVH	CV - CVH. Compare Value Register - Compare Value High
RESFIFO_D	RESFIFO - D. Data Result FIFO Register - Data Result
RESFIFO_TSRC	RESFIFO - TSRC. Data Result FIFO Register - Trigger Source [0b00] Trigger source 0 initiated this conversion. [0b01] Trigger source 1 initiated this conversion. [0b10-0b10] Corresponding trigger source initiated this conversion. [0b11] Trigger source 3 initiated this conversion.
RESFIFO_LOOPCNT	RESFIFO - LOOPCNT. Data Result FIFO Register - Loop Count Value [0b0000] Result is from initial conversion in command. [0b0001] Result is from second conversion in command. [0b0010-0b1110] Result is from LOOPCNT+1 conversion in command. [0b1111] Result is from 16th conversion in command.
RESFIFO_CMDSRC	RESFIFO - CMDSRC. Data Result FIFO Register - Command Buffer Source [0b000] Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state prior to an ADC conversion result dataword being stored to a RESFIFO buffer. [0b001] CMD1 buffer used as control settings for this conversion. [0b010-0b110] Corresponding command buffer used as control settings for this conversion. [0b111] CMD7 buffer used as control settings for this conversion.
RESFIFO_VALID	RESFIFO - VALID. Data Result FIFO Register - FIFO Entry is Valid [0b0] FIFO is empty. Discard any read from RESFIFO. [0b1] FIFO record read from RESFIFO is valid.
CAL_GAR0_CAL_GAR_VAL	CAL_GAR0 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR1_CAL_GAR_VAL	CAL_GAR1 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR2_CAL_GAR_VAL	CAL_GAR2 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR3_CAL_GAR_VAL	CAL_GAR3 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR4_CAL_GAR_VAL	CAL_GAR4 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR5_CAL_GAR_VAL	CAL_GAR5 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR6_CAL_GAR_VAL	CAL_GAR6 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR7_CAL_GAR_VAL	CAL_GAR7 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR8_CAL_GAR_VAL	CAL_GAR8 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR9_CAL_GAR_VAL	CAL_GAR9 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR10_CAL_GAR_VAL	CAL_GAR10 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR11_CAL_GAR_VAL	CAL_GAR11 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR12_CAL_GAR_VAL	CAL_GAR12 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR13_CAL_GAR_VAL	CAL_GAR13 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR14_CAL_GAR_VAL	CAL_GAR14 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR15_CAL_GAR_VAL	CAL_GAR15 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR16_CAL_GAR_VAL	CAL_GAR16 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR17_CAL_GAR_VAL	CAL_GAR17 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR18_CAL_GAR_VAL	CAL_GAR18 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR19_CAL_GAR_VAL	CAL_GAR19 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR20_CAL_GAR_VAL	CAL_GAR20 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR21_CAL_GAR_VAL	CAL_GAR21 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR22_CAL_GAR_VAL	CAL_GAR22 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR23_CAL_GAR_VAL	CAL_GAR23 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR24_CAL_GAR_VAL	CAL_GAR24 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR25_CAL_GAR_VAL	CAL_GAR25 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR26_CAL_GAR_VAL	CAL_GAR26 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR27_CAL_GAR_VAL	CAL_GAR27 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR28_CAL_GAR_VAL	CAL_GAR28 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR29_CAL_GAR_VAL	CAL_GAR29 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR30_CAL_GAR_VAL	CAL_GAR30 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR31_CAL_GAR_VAL	CAL_GAR31 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR32_CAL_GAR_VAL	CAL_GAR32 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CFG2_JLEFT	CFG2 - JLEFT. Configuration 2 Register - Justified Left Enable register
CFG2_HS	CFG2 - HS. Configuration 2 Register - High Speed Enable register [0b0] High speed conversion mode disabled [0b1] High speed conversion mode enabled
CFG2_HSEXTRA	CFG2 - HSEXTRA. Configuration 2 Register - High Speed Extra register [0b0] No extra cycle added [0b1] Extra cycle added
CFG2_TUNE	CFG2 - TUNE. Configuration 2 Register - Tune Mode register

Shift

enum struct mcxa153::chip::lpadc::Shift : unsigned int

strong

LPADC Shift - Register Bit Shift Positions.

Defines bit shift positions for LPADC (Low Power Digital Analog Convertor) registers 定義LPADC寄存器的位元位移位置

自

v1.0.0

列舉值
VERID_RES	VERID - RES. Version ID Register - Resolution [0b0] Up to 12-bit single ended resolution supported (and 13-bit differential resolution if VERID[DIFFEN] = 1b). [0b1] Up to 16-bit single ended resolution supported (and 16-bit differential resolution if VERID[DIFFEN] = 1b).
VERID_DIFFEN	VERID - DIFFEN. Version ID Register - Differential Supported [0b0] Differential operation not supported. [0b1] Differential operation supported.
VERID_MVI	VERID - MVI. Version ID Register - Multi Vref Implemented [0b0] Single voltage reference high (VREFH) input supported. [0b1] Multiple voltage reference high (VREFH) inputs supported.
VERID_CSW	VERID - CSW. Version ID Register - Channel Scale Width [0b000] Channel scaling not supported. [0b001] Channel scaling supported. 1-bit CSCALE control field. [0b110] Channel scaling supported. 6-bit CSCALE control field.
VERID_VR1RNGI	VERID - VR1RNGI. Version ID Register - Voltage Reference 1 Range Control Bit Implemented [0b0] Range control not required. CFG[VREF1RNG] is not implemented. [0b1] Range control required. CFG[VREF1RNG] is implemented.
VERID_IADCKI	VERID - IADCKI. Version ID Register - Internal ADC Clock Implemented [0b0] Internal clock source not implemented. [0b1] Internal clock source (and CFG[ADCKEN]) implemented.
VERID_CALOFSI	VERID - CALOFSI. Version ID Register - Calibration Function Implemented [0b0] Calibration Not Implemented. [0b1] Calibration Implemented.
VERID_NUM_SEC	VERID - NUM_SEC. Version ID Register - Number of Single Ended Outputs Supported [0b0] This design supports one single ended conversion at a time. [0b1] This design supports two simultaneous single ended conversions.
VERID_NUM_FIFO	VERID - NUM_FIFO. Version ID Register - Number of FIFOs [0b000] N/A [0b001] This design supports one result FIFO. [0b010] This design supports two result FIFOs. [0b011] This design supports three result FIFOs. [0b100] This design supports four result FIFOs.
VERID_MINOR	VERID - MINOR. Version ID Register - Minor Version Number
VERID_MAJOR	VERID - MAJOR -. Version ID Register - Major Version Number
PARAM_TRIG_NUM	PARAM - TRIG_NUM. Parameter Register - Trigger Number
PARAM_FIFOSIZE	PARAM - FIFOSIZE. Parameter Register - Result FIFO Depth [0b00000001] Result FIFO depth = 2 dataword. [0b00000100] Result FIFO depth = 4 datawords. [0b00001000] Result FIFO depth = 8 datawords. [0b00010000] Result FIFO depth = 16 datawords. [0b00100000] Result FIFO depth = 32 datawords. [0b01000000] Result FIFO depth = 64 datawords.
PARAM_CV_NUM	PARAM - CV_NUM. Parameter Register - Compare Value Number
PARAM_CMD_NUM	PARAM - CMD_NUM. Parameter Register - Command Buffer Number
CTRL_ADCEN	CTRL - ADCEN. Control Register - ADC Enable [0b0] ADC is disabled. [0b1] ADC is enabled.
CTRL_RST	CTRL - RST. Control Register - Software Reset [0b0] ADC logic is not reset. [0b1] ADC logic is reset.
CTRL_DOZEN	CTRL - DOZEN. Control Register - Doze Enable [0b0] ADC is enabled in low power mode. [0b1] ADC is disabled in low power mode.
CTRL_CAL_REQ	CTRL - CAL_REQ. Control Register - Auto-Calibration Request [0b0] No request for hardware calibration has been made [0b1] A request for hardware calibration has been made
CTRL_CALOFS	CTRL - CALOFS. Control Register - Offset Calibration Request [0b0] No request for offset calibration has been made [0b1] Request for offset calibration function
CTRL_CALHS	CTRL - CALHS. Control Register - High Speed Mode Trim Request [0b0] No request for high speed mode trim has been made [0b1] Request for high speed mode trim has been made
CTRL_RSTFIFO0	CTRL - RSTFIFO0. Control Register - Reset FIFO 0 [0b0] No effect. [0b1] FIFO 0 is reset.
CTRL_CAL_AVGS	CTRL - CAL_AVGS. Control Register - Auto-Calibration Averages [0b0000] Single conversion. [0b0001] 2 conversions averaged. [0b0010] 4 conversions averaged. [0b0011] 8 conversions averaged. [0b0100] 16 conversions averaged. [0b0101] 32 conversions averaged. [0b0110] 64 conversions averaged. [0b0111] 128 conversions averaged. [0b1000] 256 conversions averaged. [0b1001] 512 conversions averaged. [0b1010] 1024 conversions averaged.
STAT_RDY0	STAT - RDY0. Status Register - Result FIFO 0 Ready Flag [0b0] Result FIFO 0 data level not above watermark level. [0b1] Result FIFO 0 holding data above watermark level.
STAT_FOF0	STAT - FOF0. Status Register - Result FIFO 0 Overflow Flag [0b0] No result FIFO 0 overflow has occurred since the last time the flag was cleared. [0b1] At least one result FIFO 0 overflow has occurred since the last time the flag was cleared.
STAT_TEXC_INT	STAT - TEXC_INT. Status Register - Interrupt Flag For High Priority Trigger Exception [0b0] No trigger exceptions have occurred. [0b1] A trigger exception has occurred and is pending acknowledgement.
STAT_TCOMP_INT	STAT - TCOMP_INT. Status Register - Interrupt Flag For Trigger Completion [0b0] Either IE[TCOMP_IE] is set to 0, or no trigger sequences have run to completion. [0b1] Trigger sequence has been completed and all data is stored in the associated FIFO.
STAT_CAL_RDY	STAT - CAL_RDY. Status Register - Calibration Ready [0b0] Calibration is incomplete or hasn't been ran. [0b1] The ADC is calibrated.
STAT_ACTIVE	STAT - ACTIVE. Status Register - ADC Active [0b0] The ADC is IDLE. There are no pending triggers to service and no active commands are being processed. [0b1] The ADC is processing a conversion, running through the power up delay, or servicing a trigger.
STAT_TRGACT	STAT - TRGACT. Status Register - Trigger Active [0b00] Command (sequence) associated with Trigger 0 currently being executed. [0b01] Command (sequence) associated with Trigger 1 currently being executed. [0b10] Command (sequence) associated with Trigger 2 currently being executed. [0b11] Command (sequence) associated with Trigger 3 currently being executed.
STAT_CMDACT	STAT - CMDACT. Status Register - Command Active [0b000] No command is currently in progress. [0b001] Command 1 currently being executed. [0b010] Command 2 currently being executed. [0b011-0b111] Associated command number is currently being executed.
IE_FWMIE0	IE - FWMIE0. Interrupt Enable Register - FIFO 0 Watermark Interrupt Enable [0b0] FIFO 0 watermark interrupts are not enabled. [0b1] FIFO 0 watermark interrupts are enabled.
IE_FOFIE0	IE - FOFIE0. Interrupt Enable Register - Result FIFO 0 Overflow Interrupt Enable [0b0] FIFO 0 overflow interrupts are not enabled. [0b1] FIFO 0 overflow interrupts are enabled.
IE_TEXC_IE	IE - TEXC_IE. Interrupt Enable Register - Trigger Exception Interrupt Enable [0b0] Trigger exception interrupts are disabled. [0b1] Trigger exception interrupts are enabled.
IE_TCOMP_IE	IE - TCOMP_IE. Interrupt Enable Register - Trigger Completion Interrupt Enable [0b0000] Trigger completion interrupts are disabled. [0b0001] Trigger completion interrupts are enabled for trigger source 0 only. [0b0010] Trigger completion interrupts are enabled for trigger source 1 only. [0b0011-0b1110] Associated trigger completion interrupts are enabled. [0b1111] Trigger completion interrupts are enabled for every trigger source.
DE_FWMDE0	DE - FWMDE0. DMA Enable Register - FIFO 0 Watermark DMA Enable [0b0] DMA request disabled. [0b1] DMA request enabled.
CFG_TPRICTRL	CFG - TPRICTRL. Configuration Register - ADC Trigger Priority Control [0b00] If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started. [0b01] If a higher priority trigger is received during command processing, the current command is stopped after completing the current conversion. If averaging is enabled, the averaging loop will be completed. However, CMDHa[LOOP] will be ignored and the higher priority trigger will be serviced. [0b10] If a higher priority trigger is received during command processing, the current command will be completed (averaging, looping, compare) before servicing the higher priority trigger. [0b11]
CFG_PWRSEL	CFG - PWRSEL. Configuration Register - Power Configuration Select [0b0] Low power [0b1] High power
CFG_REFSEL	CFG - REFSEL. Configuration Register - Voltage Reference Selection [0b00] (Default) Option 1 setting. [0b01] Option 2 setting. [0b10] Option 3 setting. [0b11] Reserved
CFG_TRES	CFG - TRES. Configuration Register - Trigger Resume Enable [0b0] Trigger sequences interrupted by a high priority trigger exception are not automatically resumed or restarted. [0b1] Trigger sequences interrupted by a high priority trigger exception are automatically resumed or restarted.
CFG_TCMDRES	CFG - TCMDRES. Configuration Register - Trigger Command Resume [0b0] Trigger sequences interrupted by a high priority trigger exception is automatically restarted. [0b1] Trigger sequences interrupted by a high priority trigger exception is resumed from the command executing before the exception.
CFG_HPT_EXDI	CFG - HPT_EXDI. Configuration Register - High Priority Trigger Exception Disable [0b0] High priority trigger exceptions are enabled. [0b1] High priority trigger exceptions are disabled.
CFG_PUDLY	CFG - PUDLY - Power Up Delay.
CFG_PWREN	CFG - PWREN. Configuration Register - ADC Analog Pre-Enable [0b0] ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays. [0b1] ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost of higher DC current consumption). Note that a single power up delay (CFG[PUDLY]) is executed immediately once PWREN is set, and any detected trigger does not begin ADC operation until the power up delay time has passed. After this initial delay expires the analog remains pre-enabled and no additional delays are executed.
PAUSE_PAUSEDLY	PAUSE - PAUSEDLY. Pause Register - Pause Delay
PAUSE_PAUSEEN	PAUSE - PAUSEEN. Pause Register - PAUSE Option Enable [0b0] Pause operation disabled [0b1] Pause operation enabled
SWTRIG_SWT0	SWTRIG - SWT0. Software Trigger Register - Software Trigger 0 Event [0b0] No trigger 0 event generated. [0b1] Trigger 0 event generated.
SWTRIG_SWT1	SWTRIG - SWT1. Software Trigger Register - Software Trigger 1 Event [0b0] No trigger 1 event generated. [0b1] Trigger 1 event generated.
SWTRIG_SWT2	SWTRIG - SWT2. Software Trigger Register - Software Trigger 2 Event [0b0] No trigger 2 event generated. [0b1] Trigger 2 event generated.
SWTRIG_SWT3	SWTRIG - SWT3. Software Trigger Register - Software Trigger 3 Event [0b0] No trigger 3 event generated. [0b1] Trigger 3 event generated.
TSTAT_TEXC_NUM	TSTAT - TEXC_NUM. Trigger Status Register - Trigger Exception Number [0b0000] No triggers have been interrupted by a high priority exception. Or CFG[TRES] = 1. [0b0001] Trigger 0 has been interrupted by a high priority exception. [0b0010] Trigger 1 has been interrupted by a high priority exception. [0b0011-0b1110] Associated trigger sequence has interrupted by a high priority exception. [0b1111] Every trigger sequence has been interrupted by a high priority exception.
TSTAT_TCOMP_FLAG	TSTAT - TCOMP_FLAG. Trigger Status Register - Trigger Completion Flag [0b0000] No triggers have been completed. Trigger completion interrupts are disabled. [0b0001] Trigger 0 has been completed and trigger 0 has enabled completion interrupts. [0b0010] Trigger 1 has been completed and trigger 1 has enabled completion interrupts. [0b0011-0b1110] Associated trigger sequence has completed and has enabled completion interrupts. [0b1111] Every trigger sequence has been completed and every trigger has enabled completion interrupts.
OFSTRIM_OFSTRIM	OFSTRIM - OFSTRIM. Offset Trim Register - Trim for Offset
HSTRIM_HSTRIM	HSTRIM - HSTRIM. High Speed Trim Register - Trim for High Speed Conversions
TCTRL_HTEN	TCTRL - HTEN. Trigger Control Register - Trigger Enable [0b0] Hardware trigger source disabled [0b1] Hardware trigger source enabled
TCTRL_TPRI	TCTRL - TPRI. Trigger Control Register - Trigger Priority Setting [0b00] Set to highest priority, Level 1 [0b01-0b10] Set to corresponding priority level [0b11] Set to lowest priority, Level 4
TCTRL_RSYNC	TCTRL - RSYNC. Trigger Control Register - Trigger Resync
TCTRL_TDLY	TCTRL - TDLY. Trigger Control Register - Trigger Delay Select
TCTRL_TSYNC	TCTRL - TSYNC. Trigger Control Register - Trigger Synchronous Select
TCTRL_TCMD	TCTRL - TCMD. Trigger Control Register - Trigger Command Select [0b000] Not a valid selection from the command buffer. Trigger event is ignored. [0b001] CMD1 is executed [0b010-0b110] Corresponding CMD is executed [0b111] CMD7 is executed
FCTRL_FCOUNT	FCTRL - FCOUNT. FIFO Control Register - Result FIFO Counter
FCTRL_FWMARK	FCTRL - FWMARK. FIFO Control Register - Watermark Level Selection
GCC_GAIN_CAL	GCC - GAIN_CAL. Gain Calibration Control - Gain Calibration Value
GCC_RDY	GCC - RDY. Gain Calibration Control - Gain Calibration Value Valid [0b0] The GAIN_CAL value is invalid. Run the hardware calibration routine for this value to be set. [0b1] The GAIN_CAL value is valid. GAIN_CAL should be used by software to derive GCRa[GCALR].
GCR_GCALR	GCR - GCALR. Gain Calculation Result - Gain Calculation Result
GCR_RDY	GCR - RDY. Gain Calculation Result - Gain Calculation Ready [0b0] The GCALR value is invalid. [0b1] The GCALR value is valid.
CMDL_ADCH	CMDL - ADCH. Command Low Buffer Register - Input Channel Select [0b00000] Select CH0A. [0b00001] Select CH1A. [0b00010] Select CH2A. [0b00011] Select CH3A. [0b00100-0b11101] Select corresponding channel CHnA. [0b11110] Select CH30A. [0b11111] Select CH31A.
CMDL_CTYPE	CMDL - CTYPE. Command Low Buffer Register - Conversion Type [0b00] Single-Ended Mode. Only A side channel is converted. [0b01-0b11] Reserved.
CMDL_MODE	CMDL - MODE. Command Low Buffer Register - Select Resolution of Conversions [0b0] Standard resolution. Single-ended 12-bit conversion. [0b1] High resolution. Single-ended 16-bit conversion.
CMDH_CMPEN	CMDH - CMPEN. Command High Buffer Register - Compare Function Enable [0b00] Compare disabled. [0b01] Reserved [0b10] Compare enabled. Store on true. [0b11] Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.
CMDH_WAIT_TRIG	CMDH - WAIT_TRIG. Command High Buffer Register - Wait for Trigger Assertion before Execution. [0b0] This command will be automatically executed. [0b1] The active trigger must be asserted again before executing this command.
CMDH_LWI	CMDH - LWI. Command High Buffer Register - Loop with Increment [0b0] Auto channel increment disabled [0b1] Auto channel increment enabled
CMDH_STS	CMDH - STS. Command High Buffer Register - Sample Time Select [0b000] Minimum sample time of 3.5 ADCK cycles. [0b001] 3.5 + 21 ADCK cycles; 5.5 ADCK cycles total sample time. [0b010] 3.5 + 22 ADCK cycles; 7.5 ADCK cycles total sample time. [0b011] 3.5 + 23 ADCK cycles; 11.5 ADCK cycles total sample time. [0b100] 3.5 + 24 ADCK cycles; 19.5 ADCK cycles total sample time. [0b101] 3.5 + 25 ADCK cycles; 35.5 ADCK cycles total sample time. [0b110] 3.5 + 26 ADCK cycles; 67.5 ADCK cycles total sample time. [0b111] 3.5 + 27 ADCK cycles; 131.5 ADCK cycles total sample time.
CMDH_AVGS	CMDH - AVGS. Command High Buffer Register - Hardware Average Select [0b0000] Single conversion. [0b0001] 2 conversions averaged. [0b0010] 4 conversions averaged. [0b0011] 8 conversions averaged. [0b0100] 16 conversions averaged. [0b0101] 32 conversions averaged. [0b0110] 64 conversions averaged. [0b0111] 128 conversions averaged. [0b1000] 256 conversions averaged. [0b1001] 512 conversions averaged. [0b1010] 1024 conversions averaged.
CMDH_LOOP	CMDH - LOOP. Command High Buffer Register - Loop Count Select [0b0000] Looping not enabled. Command executes 1 time. [0b0001] Loop 1 time. Command executes 2 times. [0b0010] Loop 2 times. Command executes 3 times. [0b0011-0b1110] Loop corresponding number of times. Command executes LOOP+1 times. [0b1111] Loop 15 times. Command executes 16 times.
CMDH_NEXT	CMDH - NEXT. Command High Buffer Register - Next Command Select [0b000] No next command defined. Terminate conversions at completion of current command. If lower priority trigger pending, begin command associated with lower priority trigger. [0b001] Select CMD1 command buffer register as next command. [0b010-0b110] Select corresponding CMD command buffer register as next command [0b111] Select CMD7 command buffer register as next command.
CV_CVL	CV - CVL. Compare Value Register - Compare Value Low
CV_CVH	CV - CVH. Compare Value Register - Compare Value High
RESFIFO_D	RESFIFO - D. Data Result FIFO Register - Data Result
RESFIFO_TSRC	RESFIFO - TSRC. Data Result FIFO Register - Trigger Source [0b00] Trigger source 0 initiated this conversion. [0b01] Trigger source 1 initiated this conversion. [0b10-0b10] Corresponding trigger source initiated this conversion. [0b11] Trigger source 3 initiated this conversion.
RESFIFO_LOOPCNT	RESFIFO - LOOPCNT. Data Result FIFO Register - Loop Count Value [0b0000] Result is from initial conversion in command. [0b0001] Result is from second conversion in command. [0b0010-0b1110] Result is from LOOPCNT+1 conversion in command. [0b1111] Result is from 16th conversion in command.
RESFIFO_CMDSRC	RESFIFO - CMDSRC. Data Result FIFO Register - Command Buffer Source [0b000] Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state prior to an ADC conversion result dataword being stored to a RESFIFO buffer. [0b001] CMD1 buffer used as control settings for this conversion. [0b010-0b110] Corresponding command buffer used as control settings for this conversion. [0b111] CMD7 buffer used as control settings for this conversion.
RESFIFO_VALID	RESFIFO - VALID. Data Result FIFO Register - FIFO Entry is Valid [0b0] FIFO is empty. Discard any read from RESFIFO. [0b1] FIFO record read from RESFIFO is valid.
CAL_GAR0_CAL_GAR_VAL	CAL_GAR0 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR1_CAL_GAR_VAL	CAL_GAR1 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR2_CAL_GAR_VAL	CAL_GAR2 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR3_CAL_GAR_VAL	CAL_GAR3 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR4_CAL_GAR_VAL	CAL_GAR4 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR5_CAL_GAR_VAL	CAL_GAR5 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR6_CAL_GAR_VAL	CAL_GAR6 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR7_CAL_GAR_VAL	CAL_GAR7 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR8_CAL_GAR_VAL	CAL_GAR8 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR9_CAL_GAR_VAL	CAL_GAR9 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR10_CAL_GAR_VAL	CAL_GAR10 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR11_CAL_GAR_VAL	CAL_GAR11 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR12_CAL_GAR_VAL	CAL_GAR12 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR13_CAL_GAR_VAL	CAL_GAR13 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR14_CAL_GAR_VAL	CAL_GAR14 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR15_CAL_GAR_VAL	CAL_GAR15 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR16_CAL_GAR_VAL	CAL_GAR16 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR17_CAL_GAR_VAL	CAL_GAR17 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR18_CAL_GAR_VAL	CAL_GAR18 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR19_CAL_GAR_VAL	CAL_GAR19 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR20_CAL_GAR_VAL	CAL_GAR20 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR21_CAL_GAR_VAL	CAL_GAR21 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR22_CAL_GAR_VAL	CAL_GAR22 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR23_CAL_GAR_VAL	CAL_GAR23 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR24_CAL_GAR_VAL	CAL_GAR24 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR25_CAL_GAR_VAL	CAL_GAR25 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR26_CAL_GAR_VAL	CAL_GAR26 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR27_CAL_GAR_VAL	CAL_GAR27 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR28_CAL_GAR_VAL	CAL_GAR28 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR29_CAL_GAR_VAL	CAL_GAR29 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR30_CAL_GAR_VAL	CAL_GAR30 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR31_CAL_GAR_VAL	CAL_GAR31 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CAL_GAR32_CAL_GAR_VAL	CAL_GAR32 - CAL_GAR_VAL. Calibration General A-Side Registers - Calibration General A Side Register Element
CFG2_JLEFT	CFG2 - JLEFT. Configuration 2 Register - Justified Left Enable register
CFG2_HS	CFG2 - HS. Configuration 2 Register - High Speed Enable register [0b0] High speed conversion mode disabled [0b1] High speed conversion mode enabled
CFG2_HSEXTRA	CFG2 - HSEXTRA. Configuration 2 Register - High Speed Extra register [0b0] No extra cycle added [0b1] Extra cycle added
CFG2_TUNE	CFG2 - TUNE. Configuration 2 Register - Tune Mode register

函式說明文件

operator+()

unsigned int mcxa153::chip::lpadc::operator+ ( Shift e )

constexpr

Shift Operator - Convert Shift Enum to Integer.

Convert LPADC shift enumeration to unsigned integer value 將LPADC位移列舉轉換為無符號整數值

參數

e	Shift enumeration value 位移列舉值

傳回值

constexpr unsigned int Converted integer value 轉換後的整數值