lpspi/Shift.h

 
#ifndef MCXA153_37E12C2E_7714_47E0_8CAC_1BC5A2176BC9
#define MCXA153_37E12C2E_7714_47E0_8CAC_1BC5A2176BC9
 
/* ***************************************************************************************
 * Include
 */
#include "mframe.h"
 
//----------------------------------------------------------------------------------------
 
//----------------------------------------------------------------------------------------
 
/* ***************************************************************************************
 * Namespace
 */
namespace mcxa153::chip::lpspi {
  enum struct Shift : uint32;
 
  constexpr unsigned int operator+(Shift e) {
    return static_cast<unsigned int>(e);
  }
}  // namespace mcxa153::chip::lpspi
 
/* ***************************************************************************************
 * Class/Interface/Struct/Enum
 */
 
enum struct mcxa153::chip::lpspi::Shift : uint32 {
  VERID_FEATURE = 0U,
 
  VERID_MINOR = 16U,
 
  VERID_MAJOR = 24U,
 
  PARAM_TXFIFO = 0U,
 
  PARAM_RXFIFO = 8U,
 
  PARAM_PCSNUM = 16U,
 
  CR_MEN = 0U,
 
  CR_RST = 1U,
 
  CR_DBGEN = 3U,
 
  CR_RTF = 8U,
 
  CR_RRF = 9U,
 
  SR_TDF = 0U,
 
  SR_RDF = 1U,
 
  SR_WCF = 8U,
 
  SR_FCF = 9U,
 
  SR_TCF = 10U,
 
  SR_TEF = 11U,
 
  SR_REF = 12U,
 
  SR_DMF = 13U,
 
  SR_MBF = 24U,
 
  IER_TDIE = 0U,
 
  IER_RDIE = 1U,
 
  IER_WCIE = 8U,
 
  IER_FCIE = 9U,
 
  IER_TCIE = 10U,
 
  IER_TEIE = 11U,
 
  IER_REIE = 12U,
 
  IER_DMIE = 13U,
 
  DER_TDDE = 0U,
 
  DER_RDDE = 1U,
 
  DER_FCDE = 9U,
 
  CFGR0_HREN = 0U,
 
  CFGR0_HRPOL = 1U,
 
  CFGR0_HRSEL = 2U,
 
  CFGR0_HRDIR = 3U,
 
  CFGR0_CIRFIFO = 8U,
 
  CFGR0_RDMO = 9U,
 
  CFGR1_MASTER = 0U,
 
  CFGR1_SAMPLE = 1U,
 
  CFGR1_AUTOPCS = 2U,
 
  CFGR1_NOSTALL = 3U,
 
  CFGR1_PARTIAL = 4U,
 
  CFGR1_PCSPOL = 8U,
 
  CFGR1_MATCFG = 16U,
 
  CFGR1_PINCFG = 24U,
 
  CFGR1_OUTCFG = 26U,
 
  CFGR1_PCSCFG = 27U,
 
  DMR0_MATCH0 = 0U,
 
  /*
   * @brief DMR1 - MATCH1
   *
   * Data Match 1 - Match 1 Value
   */
  DMR1_MATCH1 = 0U,
 
  CCR_SCKDIV = 0U,
 
  CCR_DBT = 8U,
 
  CCR_PCSSCK = 16U,
 
  CCR_SCKPCS = 24U,
 
  CCR1_SCKSET = 0U,
 
  CCR1_SCKHLD = 8U,
 
  CCR1_PCSPCS = 16U,
 
  CCR1_SCKSCK = 24U,
 
  FCR_TXWATER = 0U,
 
  FCR_RXWATER = 16U,
 
  FSR_TXCOUNT = 0U,
 
  FSR_RXCOUNT = 16U,
 
  TCR_FRAMESZ = 0U,
 
  TCR_WIDTH = 16U,
 
  TCR_TXMSK = 18U,
 
  TCR_RXMSK = 19U,
 
  TCR_CONTC = 20U,
 
  TCR_CONT = 21U,
 
  TCR_BYSW = 22U,
 
  TCR_LSBF = 23U,
 
  TCR_PCS = 24U,
 
  TCR_PRESCALE = 27U,
 
  TCR_CPHA = 30U,
 
  TCR_CPOL = 31U,
 
  TDR_DATA = 0U,
 
  RSR_SOF = 0U,
 
  RSR_RXEMPTY = 1U,
 
  RDR_DATA = 0U,
 
  RDROR_DATA = 0U,
 
  TCBR_DATA = 0U,
 
  TDBR_DATA = 0U,
 
  RDBR_DATA = 0U
};
 
/* ***************************************************************************************
 * End of file
 */
 
#endif /* MCXA153_37E12C2E_7714_47E0_8CAC_1BC5A2176BC9 */