mcxa153::chip::lpspi 命名空間(Namespace)參考文件

複合項目
class	LPSPI
	MCXA153 低功耗串列周邊介面 (Low Power Serial Peripheral Interface) 控制器靜態工具類別 更多...
struct	Register
	LPSPI 週邊暫存器存取層 更多...

列舉型態
enum struct	Count : uint32 { TDBR = (128U) , RDBR = (128U) }
	LPSPI (Low Power Serial Peripheral Interface) 週邊計數器枚舉 更多...
enum struct	Mask : uint32 {   VERID_FEATURE = 0xFFFFU , VERID_MINOR = 0xFF0000U , VERID_MAJOR = 0xFF000000U , PARAM_TXFIFO = 0xFFU ,   PARAM_RXFIFO = 0xFF00U , PARAM_PCSNUM = 0xFF0000U , CR_MEN = 0x1U , CR_RST = 0x2U ,   CR_DBGEN = 0x8U , CR_RTF = 0x100U , CR_RRF = 0x200U , SR_TDF = 0x1U ,   SR_RDF = 0x2U , SR_WCF = 0x100U , SR_FCF = 0x200U , SR_TCF = 0x400U ,   SR_TEF = 0x800U , SR_REF = 0x1000U , SR_DMF = 0x2000U , SR_MBF = 0x1000000U ,   IER_TDIE = 0x1U , IER_RDIE = 0x2U , IER_WCIE = 0x100U , IER_FCIE = 0x200U ,   IER_TCIE = 0x400U , IER_TEIE = 0x800U , IER_REIE = 0x1000U , IER_DMIE = 0x2000U ,   DER_TDDE = 0x1U , DER_RDDE = 0x2U , DER_FCDE = 0x200U , CFGR0_HREN = 0x1U ,   CFGR0_HRPOL = 0x2U , CFGR0_HRSEL = 0x4U , CFGR0_HRDIR = 0x8U , CFGR0_CIRFIFO = 0x100U ,   CFGR0_RDMO = 0x200U , CFGR1_MASTER = 0x1U , CFGR1_SAMPLE = 0x2U , CFGR1_AUTOPCS = 0x4U ,   CFGR1_NOSTALL = 0x8U , CFGR1_PARTIAL = 0x10U , CFGR1_PCSPOL = 0xF00U , CFGR1_MATCFG = 0x70000U ,   CFGR1_PINCFG = 0x3000000U , CFGR1_OUTCFG = 0x4000000U , CFGR1_PCSCFG = 0x8000000U , DMR0_MATCH0 = 0xFFFFFFFFU ,   DMR1_MATCH1 = 0xFFFFFFFFU , CCR_SCKDIV = 0xFFU , CCR_DBT = 0xFF00U , CCR_PCSSCK = 0xFF0000U ,   CCR_SCKPCS = 0xFF000000U , CCR1_SCKSET = 0xFFU , CCR1_SCKHLD = 0xFF00U , CCR1_PCSPCS = 0xFF0000U ,   CCR1_SCKSCK = 0xFF000000U , FCR_TXWATER = 0x3U , FCR_RXWATER = 0x30000U , FSR_TXCOUNT = 0x7U ,   FSR_RXCOUNT = 0x70000U , TCR_FRAMESZ = 0xFFFU , TCR_WIDTH = 0x30000U , TCR_TXMSK = 0x40000U ,   TCR_RXMSK = 0x80000U , TCR_CONTC = 0x100000U , TCR_CONT = 0x200000U , TCR_BYSW = 0x400000U ,   TCR_LSBF = 0x800000U , TCR_PCS = 0x3000000U , TCR_PRESCALE = 0x38000000U , TCR_CPHA = 0x40000000U ,   TCR_CPOL = 0x80000000U , TDR_DATA = 0xFFFFFFFFU , RSR_SOF = 0x1U , RSR_RXEMPTY = 0x2U ,   RDR_DATA = 0xFFFFFFFFU , RDROR_DATA = 0xFFFFFFFFU , TCBR_DATA = 0xFFFFFFFFU , TDBR_DATA = 0xFFFFFFFFU ,   RDBR_DATA = 0xFFFFFFFFU }
	LPSPI 暫存器位元遮罩枚舉 更多...
enum struct	Shift : uint32 {   VERID_FEATURE = 0U , VERID_MINOR = 16U , VERID_MAJOR = 24U , PARAM_TXFIFO = 0U ,   PARAM_RXFIFO = 8U , PARAM_PCSNUM = 16U , CR_MEN = 0U , CR_RST = 1U ,   CR_DBGEN = 3U , CR_RTF = 8U , CR_RRF = 9U , SR_TDF = 0U ,   SR_RDF = 1U , SR_WCF = 8U , SR_FCF = 9U , SR_TCF = 10U ,   SR_TEF = 11U , SR_REF = 12U , SR_DMF = 13U , SR_MBF = 24U ,   IER_TDIE = 0U , IER_RDIE = 1U , IER_WCIE = 8U , IER_FCIE = 9U ,   IER_TCIE = 10U , IER_TEIE = 11U , IER_REIE = 12U , IER_DMIE = 13U ,   DER_TDDE = 0U , DER_RDDE = 1U , DER_FCDE = 9U , CFGR0_HREN = 0U ,   CFGR0_HRPOL = 1U , CFGR0_HRSEL = 2U , CFGR0_HRDIR = 3U , CFGR0_CIRFIFO = 8U ,   CFGR0_RDMO = 9U , CFGR1_MASTER = 0U , CFGR1_SAMPLE = 1U , CFGR1_AUTOPCS = 2U ,   CFGR1_NOSTALL = 3U , CFGR1_PARTIAL = 4U , CFGR1_PCSPOL = 8U , CFGR1_MATCFG = 16U ,   CFGR1_PINCFG = 24U , CFGR1_OUTCFG = 26U , CFGR1_PCSCFG = 27U , DMR0_MATCH0 = 0U ,   DMR1_MATCH1 = 0U , CCR_SCKDIV = 0U , CCR_DBT = 8U , CCR_PCSSCK = 16U ,   CCR_SCKPCS = 24U , CCR1_SCKSET = 0U , CCR1_SCKHLD = 8U , CCR1_PCSPCS = 16U ,   CCR1_SCKSCK = 24U , FCR_TXWATER = 0U , FCR_RXWATER = 16U , FSR_TXCOUNT = 0U ,   FSR_RXCOUNT = 16U , TCR_FRAMESZ = 0U , TCR_WIDTH = 16U , TCR_TXMSK = 18U ,   TCR_RXMSK = 19U , TCR_CONTC = 20U , TCR_CONT = 21U , TCR_BYSW = 22U ,   TCR_LSBF = 23U , TCR_PCS = 24U , TCR_PRESCALE = 27U , TCR_CPHA = 30U ,   TCR_CPOL = 31U , TDR_DATA = 0U , RSR_SOF = 0U , RSR_RXEMPTY = 1U ,   RDR_DATA = 0U , RDROR_DATA = 0U , TCBR_DATA = 0U , TDBR_DATA = 0U ,   RDBR_DATA = 0U }
	LPSPI (Low Power Serial Peripheral Interface) 位移枚舉 更多...

函式
constexpr uint32	operator+ (Count e)
constexpr unsigned int	operator+ (Mask e)
constexpr unsigned int	operator+ (Shift e)
	Shift Operator - Convert Shift Enum to Integer.

變數
Register &	LPSPI0
Register &	LPSPI1

詳細描述

Copyright (c) 2020 ZxyKira All rights reserved.

SPDX-License-Identifier: MIT

列舉型態說明文件

Count

enum struct mcxa153::chip::lpspi::Count : uint32

strong

LPSPI (Low Power Serial Peripheral Interface) 週邊計數器枚舉

此枚舉定義了 LPSPI 週邊的計數器數量， 包括 TDBR (Transmit Data Buffer Register) 和 RDBR (Receive Data Buffer Register) 的計數。

註

每個計數器的值表示對應暫存器的數量。

自

v1.0.0

Mask

enum struct mcxa153::chip::lpspi::Mask : uint32

strong

LPSPI 暫存器位元遮罩枚舉

定義了 LPSPI (Low Power SPI) 週邊各暫存器的位元欄位遮罩值， 用於位元操作、欄位存取和暫存器配置。每個遮罩對應特定暫存器的特定位元欄位。

註

使用 uint32 作為底層型別以匹配 32 位元暫存器

遮罩值可用於位元運算，如 AND、OR、XOR 等操作

列舉值
VERID_FEATURE	VERID - FEATURE. Version ID - Module Identification Number [0b0000000000000100] Standard feature set supporting a 32-bit shift register.
VERID_MINOR	MINOR - Minor. Version ID - Version Number
VERID_MAJOR	MAJOR - Major. Version ID - Version Number
PARAM_TXFIFO	PARAM - TXFIFO. Parameter - Transmit FIFO Size
PARAM_RXFIFO	PARAM - RXFIFO. Parameter - Receive FIFO Size
PARAM_PCSNUM	PARAM. Parameter - PCSNUM - PCS Number
CR_MEN	CR - MEN. Control - Module Enable [0b0] Disable [0b1] Enable
CR_RST	CR - RST. Control - Software Reset [0b0] Not reset [0b1] Reset
CR_DBGEN	CR - DBGEN. Control - Debug Enable [0b0] Disable [0b1] Enable
CR_RTF	CR - RTF. Control - Reset Transmit FIFO [0b0] No effect [0b1] Reset
CR_RRF	CR - RRF. Control - Reset Receive FIFO [0b0] No effect [0b1] Reset
SR_TDF	SR - TDF. Status - Transmit Data Flag [0b0] Transmit data not requested [0b1] Transmit data requested
SR_RDF	SR - RDF. Status - Receive Data Flag [0b0] Receive data not ready [0b1] Receive data ready
SR_WCF	SR - WCF. Status - Word Complete Flag [0b0] Not complete [0b1] Complete [0b0] No effect [0b1] Clear the flag
SR_FCF	SR - FCF. Status - Frame Complete Flag [0b0] Not complete [0b1] Complete [0b0] No effect [0b1] Clear the flag
SR_TCF	SR - TCF. Status - Transfer Complete Flag [0b0] Not complete [0b1] Complete [0b0] No effect [0b1] Clear the flag
SR_TEF	SR - TEF. Status - Transmit Error Flag [0b0] No underrun [0b1] Underrun [0b0] No effect [0b1] Clear the flag
SR_REF	SR - REF. Status - Receive Error Flag [0b0] No overflow [0b1] Overflow [0b0] No effect [0b1] Clear the flag
SR_DMF	SR - DMF. Status - Data Match Flag [0b0] No match [0b1] Match [0b0] No effect [0b1] Clear the flag
SR_MBF	SR - MBF. Status - Module Busy Flag [0b0] LPSPI is idle [0b1] LPSPI is busy
IER_TDIE	IER - TDIE. Interrupt Enable - Transmit Data Interrupt Enable [0b0] Disable [0b1] Enable
IER_RDIE	IER - RDIE. Interrupt Enable - Receive Data Interrupt Enable [0b0] Disable [0b1] Enable
IER_WCIE	IER - WCIE. Interrupt Enable - Word Complete Interrupt Enable [0b0] Disable [0b1] Enable
IER_FCIE	IER - FCIE. Interrupt Enable - Frame Complete Interrupt Enable [0b0] Disable [0b1] Enable
IER_TCIE	IER - TCIE. Interrupt Enable - Transfer Complete Interrupt Enable [0b0] Disable [0b1] Enable
IER_TEIE	IER - TEIE. Interrupt Enable - Transmit Error Interrupt Enable [0b0] Disable [0b1] Enable
IER_REIE	IER - REIE. Interrupt Enable - Receive Error Interrupt Enable [0b0] Disable [0b1] Enable
IER_DMIE	IER - DMIE. Interrupt Enable - Data Match Interrupt Enable [0b0] Disable [0b1] Enable
DER_TDDE	DER - TDDE. DMA Enable - Transmit Data DMA Enable [0b0] Disable [0b1] Enable
DER_RDDE	DER - RDDE. DMA Enable - Receive Data DMA Enable [0b0] Disable [0b1] Enable
DER_FCDE	DER - FCDE. DMA Enable - Frame Complete DMA Enable [0b0] Disable [0b1] Enable
CFGR0_HREN	CFGR0 - HREN. Configuration 0 - Host Request Enable [0b0] Disable [0b1] Enable
CFGR0_HRPOL	CFGR0 - HRPOL. Configuration 0 - Host Request Polarity [0b0] Active high [0b1] Active low
CFGR0_HRSEL	CFGR0 - HRSEL. Configuration 0 - Host Request Select [0b0] HREQ pin [0b1] Input trigger
CFGR0_HRDIR	CFGR0 - HRDIR. Configuration 0 - Host Request Direction [0b0] Input [0b1] Output
CFGR0_CIRFIFO	CFGR0 - CIRFIFO. Configuration 0 - Circular FIFO Enable [0b0] Disable [0b1] Enable
CFGR0_RDMO	CFGR0 - RDMO. Configuration 0 - Receive Data Match Only [0b0] Disable [0b1] Enable
CFGR1_MASTER	CFGR1 - MASTER. Configuration 1 - Master Mode [0b0] Slave mode [0b1] Master mode
CFGR1_SAMPLE	CFGR1 - SAMPLE. Configuration 1 - Sample Point [0b0] SCK edge [0b1] Delayed SCK edge
CFGR1_AUTOPCS	CFGR1 - AUTOPCS. Configuration 1 - Automatic PCS [0b0] Disable [0b1] Enable
CFGR1_NOSTALL	CFGR1 - NOSTALL. Configuration 1 - No Stall [0b0] Disable [0b1] Enable
CFGR1_PARTIAL	CFGR1 - PARTIAL. Configuration 1 - Partial Enable [0b0] Discard [0b1] Store
CFGR1_PCSPOL	CFGR1 - PCSPOL. Configuration 1 - Peripheral Chip Select Polarity [0b0000] Active low [0b0001] Active high
CFGR1_MATCFG	CFGR1 - MATCFG. Configuration 1 - Match Configuration [0b000] Match is disabled [0b001] [0b010] Match first data word with compare word [0b011] Match any data word with compare word [0b100] Sequential match, first data word [0b101] Sequential match, any data word [0b110] Match first data word (masked) with compare word (masked) [0b111] Match any data word (masked) with compare word (masked)
CFGR1_PINCFG	CFGR1 - PINCFG. Configuration 1 - Pin Configuration [0b00] SIN is used for input data; SOUT is used for output data [0b01] SIN is used for both input and output data; only half-duplex serial transfers are supported [0b10] SOUT is used for both input and output data; only half-duplex serial transfers are supported [0b11] SOUT is used for input data; SIN is used for output data
CFGR1_OUTCFG	CFGR1 - OUTCFG. Configuration 1 - Output Configuration [0b0] Retain last value [0b1] 3-stated
CFGR1_PCSCFG	CFGR1 - PCSCFG. Configuration 1 - Peripheral Chip Select Configuration [0b0] PCS[3:2] configured for chip select function [0b1] PCS[3:2] configured for half-duplex 4-bit transfers (PCS[3:2] = DATA[3:2])
DMR0_MATCH0	DMR0 - MATCH0. Data Match 0 - Match 0 Value
CCR_SCKDIV	CCR - SCKDIV. Clock Configuration - SCK Divider
CCR_DBT	CCR - DBT. Clock Configuration - Delay Between Transfers
CCR_PCSSCK	CCR - PCSSCK. Clock Configuration - PCS-to-SCK Delay
CCR_SCKPCS	CCR - SCKPCS. Clock Configuration - SCK-to-PCS Delay
CCR1_SCKSET	CCR1 - SCKSET. Clock Configuration 1 - SCK Setup
CCR1_SCKHLD	CCR1 - SCKHLD. Clock Configuration 1 - SCK Hold
CCR1_PCSPCS	CCR1 - PCSPCS. Clock Configuration 1 - PCS to PCS Delay
CCR1_SCKSCK	CCR1 - SCKSCK. Clock Configuration 1 - SCK Inter-Frame Delay
FCR_TXWATER	FCR - TXWATER. FIFO Control - Transmit FIFO Watermark
FCR_RXWATER	FCR - RXWATER. FIFO Control - Receive FIFO Watermark
FSR_TXCOUNT	FSR - TXCOUNT. FIFO Status - Transmit FIFO Count
FSR_RXCOUNT	FSR - RXCOUNT. FIFO Status - Receive FIFO Count
TCR_FRAMESZ	TCR - FRAMESZ. Transmit Command - Frame Size
TCR_WIDTH	TCR - WIDTH. Transmit Command - Transfer Width [0b00] 1-bit transfer [0b01] 2-bit transfer [0b10] 4-bit transfer [0b11] Reserved
TCR_TXMSK	TCR - TXMSK. Transmit Command - Transmit Data Mask [0b0] Normal transfer [0b1] Mask transmit data
TCR_RXMSK	TCR - RXMSK. Transmit Command - Receive Data Mask [0b0] Normal transfer [0b1] Mask receive data
TCR_CONTC	TCR - CONTC. Transmit Command - Continuing Command [0b0] Command word for start of new transfer [0b1] Command word for continuing transfer
TCR_CONT	TCR - CONT. Transmit Command - Continuous Transfer [0b0] Disable [0b1] Enable
TCR_BYSW	TCR - BYSW. Transmit Command - Byte Swap [0b0] Disable byte swap [0b1] Enable byte swap
TCR_LSBF	TCR - LSBF. Transmit Command - LSB First [0b0] MSB first [0b1] LSB first
TCR_PCS	TCR - PCS. Transmit Command - Peripheral Chip Select [0b00] Transfer using PCS[0] [0b01] Transfer using PCS[1] [0b10] Transfer using PCS[2] [0b11] Transfer using PCS[3]
TCR_PRESCALE	TCR - PRESCALE. Transmit Command - Prescaler Value [0b000] Divide by 1 [0b001] Divide by 2 [0b010] Divide by 4 [0b011] Divide by 8 [0b100] Divide by 16 [0b101] Divide by 32 [0b110] Divide by 64 [0b111] Divide by 128
TCR_CPHA	TCR - CPHA. Transmit Command - Clock Phase [0b0] Captured [0b1] Changed
TCR_CPOL	TCR - CPOL. Transmit Command - Clock Polarity [0b0] Inactive low [0b1] Inactive high
TDR_DATA	TDR - DATA. Transmit Data - Transmit Data
RSR_SOF	RSR - SOF. Receive Status - Start of Frame [0b0] Subsequent data word [0b1] First data word
RSR_RXEMPTY	RSR - RXEMPTY. Receive Status - RX FIFO Empty [0b0] Not empty [0b1] Empty
RDR_DATA	RDR - DATA. Receive Data - Receive Data
RDROR_DATA	RDROR - DATA. Receive Data Read Only - Receive Data
TCBR_DATA	TCBR - DATA. Transmit Command Burst - Command Data
TDBR_DATA	TDBR - DATA. Transmit Data Burst - Data
RDBR_DATA	RDBR - DATA. Receive Data Burst - Data

Shift

enum struct mcxa153::chip::lpspi::Shift : uint32

strong

LPSPI (Low Power Serial Peripheral Interface) 位移枚舉

此枚舉定義了 LPSPI 週邊各暫存器的位移值，用於位元操作和暫存器配置。

註

使用 uint32 作為底層型別以匹配 32 位元暫存器

位移值可用於位元運算，如 AND、OR、XOR 等操作

自

v1.0.0

列舉值
VERID_FEATURE	VERID - FEATURE. Version ID - Module Identification Number [0b0000000000000100] Standard feature set supporting a 32-bit shift register.
VERID_MINOR	MINOR - Minor. Version ID - Version Number
VERID_MAJOR	MAJOR - Major. Version ID - Version Number
PARAM_TXFIFO	PARAM - TXFIFO. Parameter - Transmit FIFO Size
PARAM_RXFIFO	PARAM - RXFIFO. Parameter - Receive FIFO Size
PARAM_PCSNUM	PARAM. Parameter - PCSNUM - PCS Number
CR_MEN	CR - MEN. Control - Module Enable [0b0] Disable [0b1] Enable
CR_RST	CR - RST. Control - Software Reset [0b0] Not reset [0b1] Reset
CR_DBGEN	CR - DBGEN. Control - Debug Enable [0b0] Disable [0b1] Enable
CR_RTF	CR - RTF. Control - Reset Transmit FIFO [0b0] No effect [0b1] Reset
CR_RRF	CR - RRF. Control - Reset Receive FIFO [0b0] No effect [0b1] Reset
SR_TDF	SR - TDF. Status - Transmit Data Flag [0b0] Transmit data not requested [0b1] Transmit data requested
SR_RDF	SR - RDF. Status - Receive Data Flag [0b0] Receive data not ready [0b1] Receive data ready
SR_WCF	SR - WCF. Status - Word Complete Flag [0b0] Not complete [0b1] Complete [0b0] No effect [0b1] Clear the flag
SR_FCF	SR - FCF. Status - Frame Complete Flag [0b0] Not complete [0b1] Complete [0b0] No effect [0b1] Clear the flag
SR_TCF	SR - TCF. Status - Transfer Complete Flag [0b0] Not complete [0b1] Complete [0b0] No effect [0b1] Clear the flag
SR_TEF	SR - TEF. Status - Transmit Error Flag [0b0] No underrun [0b1] Underrun [0b0] No effect [0b1] Clear the flag
SR_REF	SR - REF. Status - Receive Error Flag [0b0] No overflow [0b1] Overflow [0b0] No effect [0b1] Clear the flag
SR_DMF	SR - DMF. Status - Data Match Flag [0b0] No match [0b1] Match [0b0] No effect [0b1] Clear the flag
SR_MBF	SR - MBF. Status - Module Busy Flag [0b0] LPSPI is idle [0b1] LPSPI is busy
IER_TDIE	IER - TDIE. Interrupt Enable - Transmit Data Interrupt Enable [0b0] Disable [0b1] Enable
IER_RDIE	IER - RDIE. Interrupt Enable - Receive Data Interrupt Enable [0b0] Disable [0b1] Enable
IER_WCIE	IER - WCIE. Interrupt Enable - Word Complete Interrupt Enable [0b0] Disable [0b1] Enable
IER_FCIE	IER - FCIE. Interrupt Enable - Frame Complete Interrupt Enable [0b0] Disable [0b1] Enable
IER_TCIE	IER - TCIE. Interrupt Enable - Transfer Complete Interrupt Enable [0b0] Disable [0b1] Enable
IER_TEIE	IER - TEIE. Interrupt Enable - Transmit Error Interrupt Enable [0b0] Disable [0b1] Enable
IER_REIE	IER - REIE. Interrupt Enable - Receive Error Interrupt Enable [0b0] Disable [0b1] Enable
IER_DMIE	IER - DMIE. Interrupt Enable - Data Match Interrupt Enable [0b0] Disable [0b1] Enable
DER_TDDE	DER - TDDE. DMA Enable - Transmit Data DMA Enable [0b0] Disable [0b1] Enable
DER_RDDE	DER - RDDE. DMA Enable - Receive Data DMA Enable [0b0] Disable [0b1] Enable
DER_FCDE	DER - FCDE. DMA Enable - Frame Complete DMA Enable [0b0] Disable [0b1] Enable
CFGR0_HREN	CFGR0 - HREN. Configuration 0 - Host Request Enable [0b0] Disable [0b1] Enable
CFGR0_HRPOL	CFGR0 - HRPOL. Configuration 0 - Host Request Polarity [0b0] Active high [0b1] Active low
CFGR0_HRSEL	CFGR0 - HRSEL. Configuration 0 - Host Request Select [0b0] HREQ pin [0b1] Input trigger
CFGR0_HRDIR	CFGR0 - HRDIR. Configuration 0 - Host Request Direction [0b0] Input [0b1] Output
CFGR0_CIRFIFO	CFGR0 - CIRFIFO. Configuration 0 - Circular FIFO Enable [0b0] Disable [0b1] Enable
CFGR0_RDMO	CFGR0 - RDMO. Configuration 0 - Receive Data Match Only [0b0] Disable [0b1] Enable
CFGR1_MASTER	CFGR1 - MASTER. Configuration 1 - Master Mode [0b0] Slave mode [0b1] Master mode
CFGR1_SAMPLE	CFGR1 - SAMPLE. Configuration 1 - Sample Point [0b0] SCK edge [0b1] Delayed SCK edge
CFGR1_AUTOPCS	CFGR1 - AUTOPCS. Configuration 1 - Automatic PCS [0b0] Disable [0b1] Enable
CFGR1_NOSTALL	CFGR1 - NOSTALL. Configuration 1 - No Stall [0b0] Disable [0b1] Enable
CFGR1_PARTIAL	CFGR1 - PARTIAL. Configuration 1 - Partial Enable [0b0] Discard [0b1] Store
CFGR1_PCSPOL	CFGR1 - PCSPOL. Configuration 1 - Peripheral Chip Select Polarity [0b0000] Active low [0b0001] Active high
CFGR1_MATCFG	CFGR1 - MATCFG. Configuration 1 - Match Configuration [0b000] Match is disabled [0b001] [0b010] Match first data word with compare word [0b011] Match any data word with compare word [0b100] Sequential match, first data word [0b101] Sequential match, any data word [0b110] Match first data word (masked) with compare word (masked) [0b111] Match any data word (masked) with compare word (masked)
CFGR1_PINCFG	CFGR1 - PINCFG. Configuration 1 - Pin Configuration [0b00] SIN is used for input data; SOUT is used for output data [0b01] SIN is used for both input and output data; only half-duplex serial transfers are supported [0b10] SOUT is used for both input and output data; only half-duplex serial transfers are supported [0b11] SOUT is used for input data; SIN is used for output data
CFGR1_OUTCFG	CFGR1 - OUTCFG. Configuration 1 - Output Configuration [0b0] Retain last value [0b1] 3-stated
CFGR1_PCSCFG	CFGR1 - PCSCFG. Configuration 1 - Peripheral Chip Select Configuration [0b0] PCS[3:2] configured for chip select function [0b1] PCS[3:2] configured for half-duplex 4-bit transfers (PCS[3:2] = DATA[3:2])
DMR0_MATCH0	DMR0 - MATCH0. Data Match 0 - Match 0 Value
CCR_SCKDIV	CCR - SCKDIV. Clock Configuration - SCK Divider
CCR_DBT	CCR - DBT. Clock Configuration - Delay Between Transfers
CCR_PCSSCK	CCR - PCSSCK. Clock Configuration - PCS-to-SCK Delay
CCR_SCKPCS	CCR - SCKPCS. Clock Configuration - SCK-to-PCS Delay
CCR1_SCKSET	CCR1 - SCKSET. Clock Configuration 1 - SCK Setup
CCR1_SCKHLD	CCR1 - SCKHLD. Clock Configuration 1 - SCK Hold
CCR1_PCSPCS	CCR1 - PCSPCS. Clock Configuration 1 - PCS to PCS Delay
CCR1_SCKSCK	CCR1 - SCKSCK. Clock Configuration 1 - SCK Inter-Frame Delay
FCR_TXWATER	FCR - TXWATER. FIFO Control - Transmit FIFO Watermark
FCR_RXWATER	FCR - RXWATER. FIFO Control - Receive FIFO Watermark
FSR_TXCOUNT	FSR - TXCOUNT. FIFO Status - Transmit FIFO Count
FSR_RXCOUNT	FSR - RXCOUNT. FIFO Status - Receive FIFO Count
TCR_FRAMESZ	TCR - FRAMESZ. Transmit Command - Frame Size
TCR_WIDTH	TCR - WIDTH. Transmit Command - Transfer Width [0b00] 1-bit transfer [0b01] 2-bit transfer [0b10] 4-bit transfer [0b11] Reserved
TCR_TXMSK	TCR - TXMSK. Transmit Command - Transmit Data Mask [0b0] Normal transfer [0b1] Mask transmit data
TCR_RXMSK	TCR - RXMSK. Transmit Command - Receive Data Mask [0b0] Normal transfer [0b1] Mask receive data
TCR_CONTC	TCR - CONTC. Transmit Command - Continuing Command [0b0] Command word for start of new transfer [0b1] Command word for continuing transfer
TCR_CONT	TCR - CONT. Transmit Command - Continuous Transfer [0b0] Disable [0b1] Enable
TCR_BYSW	TCR - BYSW. Transmit Command - Byte Swap [0b0] Disable byte swap [0b1] Enable byte swap
TCR_LSBF	TCR - LSBF. Transmit Command - LSB First [0b0] MSB first [0b1] LSB first
TCR_PCS	TCR - PCS. Transmit Command - Peripheral Chip Select [0b00] Transfer using PCS[0] [0b01] Transfer using PCS[1] [0b10] Transfer using PCS[2] [0b11] Transfer using PCS[3]
TCR_PRESCALE	TCR - PRESCALE. Transmit Command - Prescaler Value [0b000] Divide by 1 [0b001] Divide by 2 [0b010] Divide by 4 [0b011] Divide by 8 [0b100] Divide by 16 [0b101] Divide by 32 [0b110] Divide by 64 [0b111] Divide by 128
TCR_CPHA	TCR - CPHA. Transmit Command - Clock Phase [0b0] Captured [0b1] Changed
TCR_CPOL	TCR - CPOL. Transmit Command - Clock Polarity [0b0] Inactive low [0b1] Inactive high
TDR_DATA	TDR - DATA. Transmit Data - Transmit Data
RSR_SOF	RSR - SOF. Receive Status - Start of Frame [0b0] Subsequent data word [0b1] First data word
RSR_RXEMPTY	RSR - RXEMPTY. Receive Status - RX FIFO Empty [0b0] Not empty [0b1] Empty
RDR_DATA	RDR - DATA. Receive Data - Receive Data
RDROR_DATA	RDROR - DATA. Receive Data Read Only - Receive Data
TCBR_DATA	TCBR - DATA. Transmit Command Burst - Command Data
TDBR_DATA	TDBR - DATA. Transmit Data Burst - Data
RDBR_DATA	RDBR - DATA. Receive Data Burst - Data

函式說明文件

operator+()

unsigned int mcxa153::chip::lpspi::operator+ ( Shift e )

constexpr

Shift Operator - Convert Shift Enum to Integer.

Convert LPI2C shift enumeration to unsigned integer value 將LPSPI位移列舉轉換為無符號整數值

參數

e	Shift enumeration value 位移列舉值

傳回值

constexpr unsigned int Converted integer value 轉換後的整數值