lpspi/Mask.h

 
#ifndef MCXA153_170C708E_8018_40F9_88EB_E2B88E638381
#define MCXA153_170C708E_8018_40F9_88EB_E2B88E638381
 
/* ***************************************************************************************
 * Include
 */
#include "mframe.h"
 
//----------------------------------------------------------------------------------------
 
//----------------------------------------------------------------------------------------
 
/* ***************************************************************************************
 * Namespace
 */
namespace mcxa153::chip::lpspi {
  enum struct Mask : uint32;
 
  constexpr unsigned int operator+(Mask e) {
    return static_cast<unsigned int>(e);
  }
}  // namespace mcxa153::chip::lpspi
 
/* ***************************************************************************************
 * Class/Interface/Struct/Enum
 */
 
enum struct mcxa153::chip::lpspi::Mask : uint32 {
  VERID_FEATURE = 0xFFFFU,
 
  VERID_MINOR = 0xFF0000U,
 
  VERID_MAJOR = 0xFF000000U,
 
  PARAM_TXFIFO = 0xFFU,
 
  PARAM_RXFIFO = 0xFF00U,
 
  PARAM_PCSNUM = 0xFF0000U,
 
  CR_MEN = 0x1U,
 
  CR_RST = 0x2U,
 
  CR_DBGEN = 0x8U,
 
  CR_RTF = 0x100U,
 
  CR_RRF = 0x200U,
 
  SR_TDF = 0x1U,
 
  SR_RDF = 0x2U,
 
  SR_WCF = 0x100U,
 
  SR_FCF = 0x200U,
 
  SR_TCF = 0x400U,
 
  SR_TEF = 0x800U,
 
  SR_REF = 0x1000U,
 
  SR_DMF = 0x2000U,
 
  SR_MBF = 0x1000000U,
 
  IER_TDIE = 0x1U,
 
  IER_RDIE = 0x2U,
 
  IER_WCIE = 0x100U,
 
  IER_FCIE = 0x200U,
 
  IER_TCIE = 0x400U,
 
  IER_TEIE = 0x800U,
 
  IER_REIE = 0x1000U,
 
  IER_DMIE = 0x2000U,
 
  DER_TDDE = 0x1U,
 
  DER_RDDE = 0x2U,
 
  DER_FCDE = 0x200U,
 
  CFGR0_HREN = 0x1U,
 
  CFGR0_HRPOL = 0x2U,
 
  CFGR0_HRSEL = 0x4U,
 
  CFGR0_HRDIR = 0x8U,
 
  CFGR0_CIRFIFO = 0x100U,
 
  CFGR0_RDMO = 0x200U,
 
  CFGR1_MASTER = 0x1U,
 
  CFGR1_SAMPLE = 0x2U,
 
  CFGR1_AUTOPCS = 0x4U,
 
  CFGR1_NOSTALL = 0x8U,
 
  CFGR1_PARTIAL = 0x10U,
 
  CFGR1_PCSPOL = 0xF00U,
 
  CFGR1_MATCFG = 0x70000U,
 
  CFGR1_PINCFG = 0x3000000U,
 
  CFGR1_OUTCFG = 0x4000000U,
 
  CFGR1_PCSCFG = 0x8000000U,
 
  DMR0_MATCH0 = 0xFFFFFFFFU,
 
  /*
   * @brief DMR1 - MATCH1
   *
   * Data Match 1 - Match 1 Value
   */
  DMR1_MATCH1 = 0xFFFFFFFFU,
 
  CCR_SCKDIV = 0xFFU,
 
  CCR_DBT = 0xFF00U,
 
  CCR_PCSSCK = 0xFF0000U,
 
  CCR_SCKPCS = 0xFF000000U,
 
  CCR1_SCKSET = 0xFFU,
 
  CCR1_SCKHLD = 0xFF00U,
 
  CCR1_PCSPCS = 0xFF0000U,
 
  CCR1_SCKSCK = 0xFF000000U,
 
  FCR_TXWATER = 0x3U,
 
  FCR_RXWATER = 0x30000U,
 
  FSR_TXCOUNT = 0x7U,
 
  FSR_RXCOUNT = 0x70000U,
 
  TCR_FRAMESZ = 0xFFFU,
 
  TCR_WIDTH = 0x30000U,
 
  TCR_TXMSK = 0x40000U,
 
  TCR_RXMSK = 0x80000U,
 
  TCR_CONTC = 0x100000U,
 
  TCR_CONT = 0x200000U,
 
  TCR_BYSW = 0x400000U,
 
  TCR_LSBF = 0x800000U,
 
  TCR_PCS = 0x3000000U,
 
  TCR_PRESCALE = 0x38000000U,
 
  TCR_CPHA = 0x40000000U,
 
  TCR_CPOL = 0x80000000U,
 
  TDR_DATA = 0xFFFFFFFFU,
 
  RSR_SOF = 0x1U,
 
  RSR_RXEMPTY = 0x2U,
 
  RDR_DATA = 0xFFFFFFFFU,
 
  RDROR_DATA = 0xFFFFFFFFU,
 
  TCBR_DATA = 0xFFFFFFFFU,
 
  TDBR_DATA = 0xFFFFFFFFU,
 
  RDBR_DATA = 0xFFFFFFFFU
};
 
/* ***************************************************************************************
 * End of file
 */
 
#endif /* MCXA153_170C708E_8018_40F9_88EB_E2B88E638381 */