Pin Control Register Array.

Pin Control Register ArrayArray of Pin Control Registers (PCR) for individual pin configuration. Each PCR controls the complete electrical and functional configuration of a single pin including multiplexing, pull resistors, drive strength, and other characteristics.

引腳控制暫存器陣列，用於個別引腳的完整配置

Base Offset: 0x80
Array Step: 0x4 (4 bytes per register)
Access: Read/Write (__IO)
Width: 32-bit per register
Array Size: 32 registers (pcr[0] through pcr[31])
Reset: Device and pin-specific values

Each PCR contains bit fields for:

[1:0] PS: Pull Select (Pull resistor configuration)
[2] PE: Pull Enable (Pull resistor enable)
[3] SRE: Slew Rate Enable (Fast/slow slew rate)
[4] PFE: Passive Filter Enable (Input noise filtering)
[5] ODE: Open Drain Enable (Open drain output mode)
[6] DSE: Drive Strength Enable (Drive strength selection)
[11:8] MUX: Pin Mux Control (Function selection)
[15] LK: Lock (Write protect configuration)

註: Array is irregular - not all indices correspond to valid pins; Pin availability varies by package and PORT instance; Register index directly corresponds to physical pin number; Locked registers (LK=1) cannot be modified until reset

:

// Configure pin 5 as GPIO with pull-up
port->pcr[5] = (GPIO << 8) | (1 << 2) | (3 << 0);
 
// Configure pin 10 for alternate function 2 with high drive strength
port->pcr[10] = (ALT2 << 8) | (1 << 6);

警告: Verify pin availability before accessing PCR array elements; Respect lock status - locked pins cannot be reconfigured; Invalid pin indices may cause bus faults or undefined behavior

參閱: mcxa153::chip::port::Config for structured PCR configuration; MCXA153 Pin Mapping Tables for valid pin assignments; Individual pin configuration enumerations for bit field values