ctimer/Mask.h

 
#ifndef CHIP_40EDD8E8_B003_495D_9461_65FC07D71841
#define CHIP_40EDD8E8_B003_495D_9461_65FC07D71841
 
/* ***************************************************************************************
 * Include
 */
 
//----------------------------------------------------------------------------------------
#include "mframe.h"
 
//----------------------------------------------------------------------------------------
 
/* ***************************************************************************************
 * Namespace
 */
namespace chip::ctimer {
  enum struct Mask : unsigned int;
 
  constexpr unsigned int operator+(Mask e) {
    return static_cast<unsigned int>(e);
  }
}  // namespace chip::ctimer
 
/* ***************************************************************************************
 * Class/Interface/Struct/Enum
 */
enum struct chip::ctimer::Mask : unsigned int {
 
  IR_MR0INT = 0x1U,
 
  IR_MR1INT = 0x2U,
 
  IR_MR2INT = 0x4U,
 
  IR_MR3INT = 0x8U,
 
  IR_CR0INT = 0x10U,
 
  IR_CR1INT = 0x20U,
 
  IR_CR2INT = 0x40U,
 
  IR_CR3INT = 0x80U,
 
  TCR_CEN = 0x1U,
 
  TCR_CRST = 0x2U,
 
  TCR_AGCEN = 0x10U,
 
  TCR_ATCEN = 0x20U,
 
  TC_TCVAL = 0xFFFFFFFFU,
 
  PR_PRVAL = 0xFFFFFFFFU,
 
  PC_PCVAL = 0xFFFFFFFFU,
 
  MCR_MR0I = 0x1U,
 
  MCR_MR0R = 0x2U,
 
  MCR_MR0S = 0x4U,
 
  MCR_MR1I = 0x8U,
 
  MCR_MR1R = 0x10U,
 
  MCR_MR1S = 0x20U,
 
  MCR_MR2I = 0x40U,
 
  MCR_MR2R = 0x80U,
 
  MCR_MR2S = 0x100U,
 
  MCR_MR3I = 0x200U,
 
  MCR_MR3R = 0x400U,
 
  MCR_MR3S = 0x800U,
 
  MCR_MR0RL = 0x1000000U,
 
  MCR_MR1RL = 0x2000000U,
 
  MCR_MR2RL = 0x4000000U,
 
  MCR_MR3RL = 0x8000000U,
 
  MR_MATCH = 0xFFFFFFFFU,
 
  CCR_CAP0RE = 0x1U,
 
  CCR_CAP0FE = 0x2U,
 
  CCR_CAP0I = 0x4U,
 
  CCR_CAP1RE = 0x8U,
 
  CCR_CAP1FE = 0x10U,
 
  CCR_CAP1I = 0x20U,
 
  CCR_CAP2RE = 0x40U,
 
  CCR_CAP2FE = 0x80U,
 
  CCR_CAP2I = 0x100U,
 
  CCR_CAP3RE = 0x200U,
 
  CCR_CAP3FE = 0x400U,
 
  CCR_CAP3I = 0x800U,
 
  CR_CAP = 0xFFFFFFFFU,
 
  EMR_EM0 = 0x1U,
 
  EMR_EM1 = 0x2U,
 
  EMR_EM2 = 0x4U,
  EMR_EM3 = 0x8U,
 
  EMR_EMC0 = 0x30U,
 
  EMR_EMC1 = 0xC0U,
 
  EMR_EMC2 = 0x300U,
 
  EMR_EMC3 = 0xC00U,
 
  CTCR_CTMODE = 0x3U,
 
  CTCR_CINSEL = 0xCU,
 
  CTCR_ENCC = 0x10U,
 
  CTCR_SELCC = 0xE0U,
 
  PWMC_PWMEN0 = 0x1U,
 
  PWMC_PWMEN1 = 0x2U,
 
  PWMC_PWMEN2 = 0x4U,
 
  PWMC_PWMEN3 = 0x8U,
 
  MSR_MATCH_SHADOW = 0xFFFFFFFFU
 
};
 
/* ***************************************************************************************
 * End of file
 */
 
#endif /* CHIP_40EDD8E8_B003_495D_9461_65FC07D71841 */