7#ifndef CORE_64666743_B91A_4EB7_B6DA_C82F07360F38
8#define CORE_64666743_B91A_4EB7_B6DA_C82F07360F38
23 enum struct MuxPortPin : uint16;
25 constexpr uint16 operator+(MuxPortPin e) {
26 return static_cast<uint16
>(e);
29 static inline constexpr uint8 getMuxPort(MuxPortPin e) {
30 return static_cast<uint8
>((+e & 0x0300) >> 8U);
33 static inline constexpr uint8 getMuxPin(MuxPortPin e) {
34 return static_cast<uint8
>(+e & 0x001F);
37 static inline constexpr uint16 genMuxPortPin(uint8 port, uint8 pin) {
38 return static_cast<uint16
>(
static_cast<uint16
>(
39 static_cast<uint16
>(port & 0x03U) << 8U) +
48enum struct core::mux::MuxPortPin : uint16 {
49 P0_0 = genMuxPortPin(0, 0),
50 P0_1 = genMuxPortPin(0, 1),
51 P0_2 = genMuxPortPin(0, 2),
52 P0_3 = genMuxPortPin(0, 3),
53 P0_6 = genMuxPortPin(0, 6),
54 P0_16 = genMuxPortPin(0, 16),
55 P0_17 = genMuxPortPin(0, 17),
56 P1_0 = genMuxPortPin(1, 0),
57 P1_1 = genMuxPortPin(1, 1),
58 P1_2 = genMuxPortPin(1, 2),
59 P1_3 = genMuxPortPin(1, 3),
60 P1_4 = genMuxPortPin(1, 4),
61 P1_5 = genMuxPortPin(1, 5),
62 P1_6 = genMuxPortPin(1, 6),
63 P1_7 = genMuxPortPin(1, 7),
64 P1_8 = genMuxPortPin(1, 8),
65 P1_9 = genMuxPortPin(1, 9),
66 P1_10 = genMuxPortPin(1, 10),
67 P1_11 = genMuxPortPin(1, 11),
68 P1_12 = genMuxPortPin(1, 12),
69 P1_13 = genMuxPortPin(1, 13),
70 P1_29 = genMuxPortPin(1, 29),
71 P1_30 = genMuxPortPin(1, 30),
72 P1_31 = genMuxPortPin(1, 31),
73 P2_0 = genMuxPortPin(2, 0),
74 P2_1 = genMuxPortPin(2, 1),
75 P2_2 = genMuxPortPin(2, 2),
76 P2_3 = genMuxPortPin(2, 3),
77 P2_4 = genMuxPortPin(2, 4),
78 P2_5 = genMuxPortPin(2, 5),
79 P2_6 = genMuxPortPin(2, 6),
80 P2_7 = genMuxPortPin(2, 7),
81 P2_12 = genMuxPortPin(2, 12),
82 P2_13 = genMuxPortPin(2, 13),
83 P2_16 = genMuxPortPin(2, 16),
84 P3_0 = genMuxPortPin(3, 0),
85 P3_1 = genMuxPortPin(3, 1),
86 P3_6 = genMuxPortPin(3, 6),
87 P3_7 = genMuxPortPin(3, 7),
88 P3_8 = genMuxPortPin(3, 8),
89 P3_9 = genMuxPortPin(3, 9),
90 P3_10 = genMuxPortPin(3, 10),
91 P3_11 = genMuxPortPin(3, 11),
92 P3_12 = genMuxPortPin(3, 12),
93 P3_13 = genMuxPortPin(3, 13),
94 P3_14 = genMuxPortPin(3, 14),
95 P3_15 = genMuxPortPin(3, 15),
96 P3_27 = genMuxPortPin(3, 27),
97 P3_28 = genMuxPortPin(3, 28),
98 P3_29 = genMuxPortPin(3, 29),
99 P3_30 = genMuxPortPin(3, 30),
100 P3_31 = genMuxPortPin(3, 31)
Definition ctimer0/MAT0.h:23